JPH0587180B2 - - Google Patents

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to multilayer plastic chip carriers used for packaging electronic components.

[Conventional technology]

Multi-layer plastic chip carriers are used as chip carriers such as plastic pin grid arrays (PPGAs) and plastic cleedless chip carriers (PLCCs) used to package electronic components such as IC chips. There is. As shown in FIG. 7, this multilayer plastic chip carrier A consists of a lower substrate 3 with a cavity recess 2 in the center and an upper substrate 9 with an opening 8 larger than the cavity 2 in the center. It is formed by laminating and adhering (one or more sheets) using an adhesive layer 7, and a circuit 5 serving as an inner layer circuit is on the upper surface of the lower substrate 3, and a circuit 5 that is an inner layer circuit is formed on the lower surface of the lower substrate 3 and the upper substrate 9. Outer layer circuits 11 are formed on the upper surface by etching copper foil or the like. A large number of circuits 5 formed on the upper surface of the lower substrate 3 are formed radially around the cavity recess 2 as shown in FIG. 6, and the end of the circuit 5 on the cavity recess 2 side The inner lead portion 4 is arranged along the edge of the cavity recess 2, and the opposite end is provided with a through hole portion and a land portion 16.
(In FIG. 6, the circuit 5 is shown only in a part of the lower board 3, and the other parts are omitted). In the multilayer plastic chip carrier A formed in this manner, an electronic component 1 such as an IC chip is mounted in the cavity recess 2, and the inner lead portion 4 of the circuit 5 of the lower board 3 and the electronic component 1 are mounted.
The electronic component 1 and the circuit 5 are electrically connected by performing wire bonding 14 or the like between them. This circuit 5 is connected to terminal pins etc. that serve as connections to the outside, and when the multilayer plastic chip carrier A is mounted on a motherboard etc., the electronic component 1 is electrically connected to the motherboard via the circuit 5. I can do it.

[Problem to be solved by the invention]

A problem with this multilayer plastic chip carrier A is that the adhesion between the upper and lower substrates 3 and 9 is poor. That is, the upper and lower substrates 3 and 9 are coated with an adhesive layer 7 such as prepreg for bonding.
By heat-pressing molding with the two layers in between, they are laminated and bonded via the adhesive layer 7 as shown in FIG. However, when forming the circuit 5 on the upper surface of the lower substrate 3, the cavity recess 2 has a rectangular planar shape, and the inner lead portion 4 of the circuit 5 is arranged along the edge of the cavity recess 2. Therefore, as shown in FIG. 7, a space 12 in which the circuit 5 is not provided is formed near the corner of the cavity recess 2. Then, the upper and lower substrates 3 and 9 are bonded with adhesive layer 7 by heating and pressure molding.
When laminating and bonding the circuits, since the circuit 5 is formed thickly on the upper surface of the lower substrate 3, the pressure force does not act much in the space 12 where the circuit 5 is not formed, and this circuit Poor adhesion occurs between the adhesive layer 7 and the substrates 3 and 9 at the space 12 where the space 5 is not formed, resulting in a gap, and impurities and foreign matter enter this gap, resulting in decreased performance and reliability. A problem arises in that there is a risk that the Therefore, in order to improve the adhesion between the adhesive layer 7 and the substrates 3 and 9 and prevent gaps from forming, the adhesive layer 7
However, when the thickness of the adhesive layer 7 is increased in this way, the adhesive resin of the adhesive layer 7 protrudes, covering the entire surface of the inner lead portion 4 of the circuit 5, and the electronic component 1 There is a possibility that it may become impossible to perform wire bonding 14 between the two. The present invention has been made in view of the above points, and there is no need to make the adhesive layer 7 thick.
It is an object of the present invention to provide a multilayer plastic chip carrier that can prevent the formation of a gap between the upper and lower substrates 3 and 9.

[Means to solve the problem]

In the multilayer plastic chip carrier according to the present invention, a cavity recess 2 having a rectangular planar shape for accommodating an electronic component 1 is provided in the center of the upper surface of a lower substrate 3, and an inner lead portion 4 at one end is provided in the cavity recess 2. A large number of circuits 5, 5, . It is characterized in that an upper substrate 9 having a planar opening 8 larger than the cavity recess 2 formed in the center thereof is laminated and bonded to the upper surface of the lower substrate 3 via an adhesive layer 7.

[Effect]

In the present invention, by providing the circuit section 6 on the upper surface of the lower substrate 3 near the corner of the cavity recess 2, a space where no circuit is provided near the corner of the cavity recess 2 can be created. It is possible to prevent the occurrence of poor adhesion between the adhesive layer 7 and the upper and lower substrates 3 and 9 at this portion.

【Example】

The present invention will be explained in detail below using examples. The lower substrate 3 and the upper substrate 9 are made of a resin laminate covered with metal foil, such as a copper-clad epoxy laminate, and each substrate 3, 9 has a large number of etchings formed by etching the metal foil. The circuit of the book is formed. Here, in the center of the upper surface of the lower substrate 3 located below the multilayer plastic chip carrier A, there is a cavity recess 2 having a rectangular planar shape.
is recessed. As already described in FIG. 6, the circuits 5 formed on the upper surface of the lower substrate 3 are provided in a radial pattern centered on the cavity recess 2, and one end of each circuit 5 is arranged as an inner lead part 4 along the edge of the cavity recess 2, and the other end is arranged at the end of the lower substrate 3 as a land 16 provided with a through hole. Further, an outer layer circuit 11 is formed on the lower surface of the lower substrate 3 and the upper surface of the upper substrate 9. Here, when providing the circuit 5 on the lower substrate 3 as described above, the inner lead portion 4 of the circuit 5 is arranged along the edge of the cavity recess 2, as described above. Thus, a space 12 in which the circuit 5 is not provided is formed near the corner of the cavity recess 2. Therefore, in the present invention, metal foil such as copper foil is etched to form the circuit 5.
When forming the circuit 5, the metal foil is not removed even in the space 12 where the circuit 5 is not required, but is left as the circuit part 6, so that the space 12 where no circuit is not provided is not formed. This circuit section 6 can be formed as an independent circuit independent of the circuit 5 as shown in FIGS. 1a and 1b, or by making the circuit 5 thicker as shown in FIG. The circuit section 6 can also be formed in the space 12. When laminating and bonding the lower substrate 3 and the upper substrate 9, the insulating layer 13 is first formed on the upper surface of the lower substrate 3. The insulating layer 13 can be formed using a solder resist or the like, and the insulating layer 13 is formed by applying a liquid solder resist to the upper surface of the lower substrate 3 and heating and curing it as necessary. can be formed. By coating and forming the insulating layer 13 in this way, the gap between adjacent circuits 5 formed on the upper surface of the lower substrate 3 and the gap between the circuit 5 and the circuit section 6 can be removed by the insulating layer 13. The upper surface of the lower substrate 3 can be made smooth. Here, the narrower the gap between the circuits 5 or between the circuit 5 and the circuit part 6, the smaller the gap, so the gap can be reliably filled with the insulating layer 13, and the gap l between these is 2 mm. It is best to set it below (preferably 1.7 mm or below). After the insulating layer 13 is applied and formed on the upper surface of the lower substrate 3 as described above, the upper substrate 9 in which the opening 8 is provided is laminated and bonded on the lower substrate 3 via the adhesive layer 7. The adhesive layer 7 can be formed of, for example, prepreg (resin-impregnated dry base material) for bonding, and is formed by sandwiching the prepreg between the upper and lower substrates 3 and 9 and molding it under heat and pressure. By laminating and adhering 3 and 9 with an adhesive layer 7, a multilayer plastic chip carrier A as shown in FIG. 2a can be obtained. Since the space 12 of the lower substrate 3 is provided with a rotary compression element, the pressure force applied during lamination is uniform, and the surface of the lower substrate 3 is smoothed by the application of the insulating layer 13. In addition, there is no risk of insufficient adhesion between the adhesive layer 7 and the upper and lower substrates 3 and 9, resulting in poor adhesion and the creation of a gap. In addition, since it is possible to prevent gaps from forming between the adhesive layer 7 and the upper and lower substrates 3 and 9 in this way, there is no need to use a thick adhesive layer 7, and it is possible to prevent the formation of gaps between the adhesive layer 7 and the upper and lower substrates 3 and 9. There is no fear that the entire surface of the protruding inner lead portion 4 of the circuit 5 will be covered by the protruding adhesive layer 7. In the embodiments shown in FIGS. 1a, b, and c, the circuit section 6 is formed to be slightly retracted from the edge of the opening 8 of the upper substrate 9 (the retraction dimension m is 2 mm or less). , preferably 1.7 mm or less), Figure 3a,
Conversely, the circuit portion 6 may be slightly protruded into the opening 8 as shown in b and c. Furthermore, when a circuit is formed on the lower surface of the upper substrate 9 as shown in FIG. It is preferable to apply and form the insulating layer 13 on the lower surface of the upper substrate 9 beforehand to make the lower surface of the upper substrate 9 smooth. The embodiments shown in FIGS. 4 and 5 are as follows:
The insulating layer 13 coated on the upper surface of the lower substrate 3 is made to slightly protrude into the opening 8 of the upper substrate 9. FIG. 5a shows an inner layer circuit 17 on the upper substrate 9.
FIG. 5b shows one in which the inner layer circuit 17 is provided on the upper substrate 9. Furthermore, in each of the above embodiments, the multilayer plastic pingrid array A is shown in which the electronic component 1 is mounted facing upward, but the multilayer plastic pingrid array A is designed such that the electronic component 1 is mounted downward.
Needless to say, it is also possible to form a structure in which the structure is upside down (as shown in FIG. 2, it is upside down).

【Effect of the invention】

As described above, in the present invention, the circuit portion is provided on the upper surface of the lower substrate near the corner of the cavity recess formed in a rectangular shape, so that the circuit is provided near the corner of the cavity recess. It is possible to prevent the formation of spaces that are not provided, and it is possible to prevent poor adhesion between the adhesive layer and the upper and lower substrates at this location, thereby preventing the formation of gaps.

[Brief explanation of drawings]

Figures 1a, b, and c are plan views of a portion of each embodiment of the present invention, Figures 2a and b are sectional views of a portion of the same embodiment, and Figures 3a, b, and c are sectional views of a portion of the same embodiment. FIG. 4 is a plan view of a part of another embodiment of the invention, FIG. 4 is a plan view of a part of still another embodiment of the invention, and FIGS.
FIG. 6 is a plan view of the conventional example, and FIG. 7 is a sectional view of the conventional example. 1 is an electronic component, 2 is a cavity recess, 3 is a lower substrate, 4 is an inner lead portion, 5 is a circuit, 6 is a circuit portion, 7 is an adhesive layer, 8 is an opening, and 9 is an upper substrate.

Claims (1)

[Scope of Claims] 1. A cavity recess with a rectangular planar shape for accommodating an electronic component is provided in the center of the upper surface of the lower substrate, and a plurality of inner leads at one end are made to face the edge of the cavity recess. A circuit section is formed on the upper surface of the lower substrate in a radial arrangement, a circuit section is provided on the upper surface of the lower substrate near the corner of the cavity recess, and a circuit section larger than the cavity recess is formed on the upper surface of the lower substrate via an adhesive layer. A multilayer plastic chip carrier characterized by being formed by laminating and bonding an upper substrate with a planar opening formed in the center. 2. The multilayer plastic chip carrier according to claim 1, wherein the distance between adjacent circuits is 2 mm or less.