JPH0587913B2 - - Google Patents

Description

[Detailed description of the invention]

[Summary] The system aims to improve the performance of the bitmap memory used for image processing by providing freedom in the access direction. [Industrial Application Field] The present invention relates to a multidimensional access semiconductor memory that can be accessed in any direction such as vertical, horizontal, and depth directions. [Prior Art] A semiconductor memory device generally includes a cell array consisting of a large number of word lines and bit lines, memory cells arranged at each intersection of these word lines and bit lines, a word (row) decoder for selecting a word line, It consists of a column decoder that selects bit lines. When the row decoder selects a word line according to the word address, the stored data of all memory cells belonging to the word line appears on all bit lines, and the sense amplifier amplifies it. The column decoder connects the selected bit line to the data bus according to the column address,
Since the number of bit lines to be selected is usually one,
1 of the intersection of the selected 1 word line and 1 bit line
Data in the memory cells is retrieved onto the data bus. If a plurality (M) of such semiconductor memory devices (memory chips), for example 8, are prepared, 1 word address and 1 bit address, that is, 1 address will be 8.
Memory cells (8 bits) are read. In addition, data buses are prepared for the number of bits in one word (n), and when one word is selected, the number of bits in that word is n.
It is also possible for the bits to be read simultaneously. In this case, a column decoder is not required (when one word is contained in one word line), or the bit line is selected in units of n (one word line contains m
(when word is included). [Problems to be solved by the invention] In the image display memory, the shading and lightness of each pixel of the image,
Since it has color tone information, each pixel is specified by an address, and each address has multiple bits for shading, and three planes of R, G, and B are prepared. 16× screen memory (bit map) like this
16. Consider a simple example of RGB3 planes. _M1 to _M3 in FIG. 7 are 16×16 bit memories, each for R, G, and B. This memory is 64
Bit (8 bits per word, 8 words)
Suppose it is composed of 12 pieces. Since 8 bits can be read simultaneously with one word address, the 8 bits read simultaneously can be quickly processed (read, written, and changed). Therefore, A in Figure 7,
If B, C, ... are word lines, and 0, 1, 2, ... are bit lines, 8 bits arranged in the word line direction (one set is shown with diagonal lines) can be processed quickly. , 8 bits in the bit line direction orthogonal to these must be accessed eight times, which takes time to process. For the vertical direction, there is a method of allocating the bits to another chip, but the bits cannot be used effectively for large-capacity memory elements, and the external circuit becomes complicated and power consumption increases due to simultaneous operation of a large number of bits. Also, if you include plane direction operations (color changes),
Bitmap peripheral circuits are becoming increasingly complex. The present invention is intended to enable access in any direction, such as the vertical, horizontal, and depth directions, and to improve system performance, particularly graphic processing. [Means for solving the problem] As shown in FIG. 1, in the present invention, data of a cubic image having X, Y, and Z directions is written along the word line of a cell array 10 of a memory chip, and the data of a cubic image of the cell array 10 is written. A multidimensional selection circuit 14 is provided for each line, receives the n-bit cubic image data read out by selecting one word line into a register 12, and selects one of the data in the X, Y, Z direction, etc. from the register. It can be selected and taken out using the selection circuit. For example, a cubic image has a unit of 8 bits, and its
000, 001, 010, 011, 100, 101, 110, and 111 bits are allocated as shown in FIG. This means that the first (left) bit of each 3 bits is the X coordinate, the next (center) bit is the Y coordinate, and the last (right) bit is the Z coordinate.
The coordinates were taken. Eight such image units A, B, . . . The selection circuit 14 receives the access direction instruction signal D, selects the data in the register 12 in the direction specified by the signal, and outputs the selected data. [Operation] For example, when the signal D instructs access in the X direction, the output is as shown in FIG. 3a, and when the signal D instructs access in the Y and Z directions, the output is as shown in FIGS. 3b and 3c. Since there are 8 units A to H, you can select one with 3 bits, and since each unit is 8 bits, you can select one with 3 bits, but in this case, the 8 bits of each unit are selected by 2 bits. into four groups,
Each group 00, 01, 10, 11 is arranged horizontally in FIG. 2 when the signal D indicates the X direction, vertically when the Y direction is indicated, and in the depth direction when the signal D indicates the Z direction. The following table summarizes Figure 3.

〔Example〕

FIG. 4 shows an example in which 8×8×8 cubic data is stored in one word line. This 8 is selected by word line selection.
×8×8=512 bits are read and register 12
Therefore, if we extract the data 0, 1, 2...7 along the X-axis from the 512-bit data in Figure 4, we can obtain 8-bit X-direction data, and the data 0, 1, 7 along the Y-axis. If you take out 2,...7, you get 8 bits Y.
Direction data is obtained. The same applies to the Z direction. A large 3D image is made by stacking up the required number of 8x8x8 images, and if each 512-bit data is stored in each word line, X, Y, Z
Both directions can be processed simultaneously in 8-bit units. The 8×8×8 solid in FIG. 4 corresponds to four units A, B, . . . in FIG. 2 arranged vertically, horizontally, and deep. Therefore, 8-bit data in the X direction can be selected in the manner described above. FIG. 5 shows an example of 16×16×depth direction bits. Again, simultaneous reading of 16 bits in the X direction and 16 bits in the Y direction is possible. Furthermore, simultaneous reading of S16 bits in the surface direction is also possible. That is, since the 16.times.16.times. bit data is in the register 12, the selection circuit 14 may output the data in the rectangular area marked S in FIG. FIG. 6 shows a specific example of the memory shown in FIG. 2, in which the number of bits in one word line is 64, and 2 bits are output as external data in the X, Y, and Z directions. RA ₀
~ _RA7 is a row address, _CA0 ~ _CA4 are column addresses, and _DA0 ~ _DA2 are direction addresses. X decoder 1, Y decoder 1, Z decoder 1 are addresses
CA ₀ and CA ₁ are received to produce a signal that selects a group of gates that select two bits as shown in FIG. X decoder 2, Y decoder 2, Z decoder 2
receives addresses CA ₂ to CA ₄ and selects the 2 bits selected by the X, Y, Z decoder 1, and determines from which of A to H in FIG. 2 the 2 bits are extracted. The direction decoder also uses the address
Upon receiving DA ₀ to DA ₁ , an enable signal is sent to the decoders (X, Y, Z decoders 1, 2) in the requested access direction. To explain the operation, when a row address RA ₀ to RA ₇ is given, the row decoder selects one of the cell arrays.
When a word line is selected, the stored data of all the memory cells belonging to the word line, 64 in this example, appear on the bit line, and the sense amplifiers _SA0 to _SA63 appear on the bit line.
The signal is further amplified and set in cells _SC0 to _SC63 of the register 12. The X, Y, Z decoders 1 and 2 are given column addresses CA ₀ -CA ₄ , and the direction decoders are given directional addresses DA ₀ -DA ₁ . Now, assuming that DA ₀ and DA ₁ are 0, 0, the direction decoder outputs a signal that enables the X decoders 1 and 2. Therefore, X decoder 1 has CA ₀ ~
The selection gate belonging to one of the lines ₁ to ₄ selected by CA ₁ is turned on and outputs the data of the corresponding cell in the register 12 (this output state is as shown in a in Fig. 3, but The block is 8 in Figure 6.
In addition, the selection gate belonging to one of the lines _L1 to L8 selected by the X decoder 2 by _CA2 to _CA4 is turned on, and the selection gate belonging to one of the lines L1 to _L8 selected by the
2 bits of one block of the data bus
Output to DB ₀ and DB ₁ . D ₀ and D ₁ are the 2-bit data thus output. By changing addresses CA ₂ to CA ₄ ,
The selection of blocks A to H is also the address CA ₀ to
By changing CA ₁ , blocks A, B,...
One of four combinations of two in the X direction is selected. When the direction addresses DA ₀ and DA ₁ are changed to 01 and 10, Y decoders 1 and 2 and Z decoders 1 and 2 are enabled, and by giving CA ₀ to CA ₄ in such a state, they are enabled in the Y and Z directions. The same 2-bit output as above is performed. FIG. 8 is an explanatory diagram of the access operation of the multidimensional memory according to the present invention. Using this figure, the principle of access operation using column addresses and direction addresses will be supplementarily explained. In one memory cell array shown in A of FIG. 8, one word line (WL) is selected by decoding a row address. Note that the memory cell array may be divided into a plurality of regions as long as they are accessed by a common word line (WL). Next, by decoding the column address with a column decoder, a reference bit line is determined from among a large number of bit lines (BL) related to the selected word line (WL). On the other hand, the number of bits (m) to be accessed is determined in advance by design, and the remaining (m-1) bit lines are selected based on this bit line. For example, when selecting four bit lines, the next time an access direction address is input, that address determines how far apart from the reference bit line the remaining three bit lines should be selected. It is determined. In the example shown in A., the bit lines specified by the access direction address are set at fixed intervals (fixed number of bit lines) from the reference bit line.
is selected, and a total of four bit lines .about. are selected. The fact that the interval between the selected bit lines with respect to the reference bit line is determined by the access direction address in this way is also shown in the example of accessing 2-bit data shown in FIG. 3 above. In this way, by accessing with the row address, column address, and access direction address, the reference bit line from multiple bit lines and the multiple bits at a fixed interval (determined by the access direction address) from the reference bit line are accessed. The function of selecting lines can be rewritten into a three-dimensional virtual model as shown in FIG. 8B. In this case,
It is considered that the X-axis and Y-axis coordinates correspond to the row address and column address, and the Z-axis coordinate corresponds to the access direction address. [Effect of the invention] As explained above, according to the present invention, vertical, horizontal,
It is possible to provide memory that can be accessed in multiple dimensions, such as three dimensions of depth, and to improve the performance of graphics processing.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the memory of the present invention, and FIG.
An explanatory diagram of dimensional image data, Fig. 3 is an explanatory diagram of X, Y, Z direction reading, Fig. 4 is an explanatory diagram of 8x8x8 image data, Fig. 5 is an explanatory diagram of 16x16 image data, FIG. 6 is a circuit diagram of the memory shown in FIG. 2, and FIG. 7 is a schematic explanatory diagram of the bitmap memory. FIG. 8 is an explanatory diagram of the access operation of the multidimensional memory according to the present invention. In FIGS. 1 and 6, 10 is a cell array, 14 is a selection circuit, WL is a word line, BL is a bit line, and DB is a data bus.

Claims (1)

[Claims] 1. An array including a plurality of word lines, a plurality of bit lines, and memory cells connected to the word lines and the bit lines, and a row decoder that selects a word line in response to a row address. , a column decoder that selects a plurality of bits of memory cells from a group of memory cells connected to a selected word line in response to a column address and an access direction address; A multidimensional access semiconductor is configured to select a plurality of bits in different combinations depending on an access direction indicated by an access direction address even if the bits are the same, and each combination corresponding to each access direction includes at least one common bit. memory.