JPH0588050B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a capacitor bank protection device, and particularly to a capacitor bank protection device that can perform protective operations according to the number of failures of a filter bank consisting of a large number of capacitor groups, or a capacitor bank. It is.

[Technical background of the invention and its problems] With conventional capacitor bank protection devices, it is impossible to detect the number of failed capacitors;
Immediately after the failure is detected, the circuit breaker trips. In this case, in a DC power transmission system that cannot be operated without a capacitor bank such as a filter or a capacitor bank, even a failure of one unit capacitor leads to the shutdown of the entire system. Therefore, the number of failures in the unit capacitors is detected, and if the number of failures is such that the capacitor bank can continue to operate, it does not immediately trip the circuit breaker, but only issues an alarm, and when the number of failures reaches such a level that it is impossible to continue operation, There is a need for a capacitor bank protection device that determines the number of failures in unit capacitors that would lead to a breaker trip, and outputs an alarm or a breaker trip command depending on the number of failures.

[Object of the Invention] The present invention has been made in response to the above-mentioned requirements, and an object of the present invention is to provide a capacitor bank protection device that can determine the number of unit capacitor failures.

[Summary of the Invention] In a capacitor bank in which a group of capacitors are arranged in a bridge shape, when the bridge becomes unbalanced due to a capacitor failure and an unbalanced current flows,
This unbalanced current is level 1, level 2, level 3
Based on the operating order of each output of a detection relay having three levels of detection level output, a fault determination circuit consisting of a memory circuit and other logic elements determines the number of faults in a unit capacitor, and the number of faults is 1. In the case of 3 or more, only an alarm is output; in the case of 2, a similar alarm is output and a trip command is output after a certain period of time; and in the case of 3 or more, a trip command is output immediately.

[Embodiments of the Invention] Examples will be described below with reference to the drawings. FIG. 2 is a configuration diagram of the capacitor bank. In FIG. 2, the capacitor group is divided into four groups 1, 2, 3, and 4 and arranged in a bridge shape, and the outputs I _l and I _d of the load current current transformer 5 and the unbalanced current current transformer 6 are is input to the detection relay 7, and a level output according to the unbalanced current _Id is performed. This level output includes a level 1 output that operates with unbalanced current when one unit capacitor fails, a level 2 output that operates with twice the unbalanced current when one unit fails, and a level 2 output that operates with twice the unbalanced current when one unit fails. It has three level outputs with a level 3 output operating at . Also, 8 indicates a bridge or disconnection.

FIG. 3 shows the characteristics of the detection relay 7. Detection relay 7 has characteristics (1) 9, characteristics (2) 10, and characteristics
(3) It has each of the following three characteristics. In the region below characteristic (1) 9, the detection relay 7 does not operate and is a level 0 region. Between characteristic (1) 9 and characteristic (2) 10 is level 1 output area 12, and similarly characteristic (2) 10
The area between and characteristic (3) 11 is the level 2 output area 13, and the area above characteristic (3) 11 is the level 3 output area 14.
shows.

FIG. 1 shows a block diagram of an embodiment of a failure determination circuit for determining the number of unit capacitor failures. Detection relay 7
When each level output operates, NOT circuit 15~
20, memory circuits 21-23, AND circuits 24-2
6 and OR circuits 27 and 28 are configured to memorize the operation of each level output and determine the number of failures based on the order of operation. or,
Reference numeral 29 is an on-delay circuit that gives a time limit to the trip command when two unit capacitors fail, and the memory circuits 21 to 23 are reset via an OR circuit 30.

Next, the effect will be explained. Now, if one, two, and then three unit capacitors are sequentially out of order, the following three patterns of change in the output level of the detection relay 7 can be considered.

Level 0 → Level 1 → Level 2 → Level 3…(1) Level 0 → Level 1 → Level 2 → Level 1...(2) Level 0 → Level 1 → Level 0 → Level 1...(3) The above (1), (2), and (3) will be explained in order.

In FIG. 2, case (1) is a case where one to three capacitors in the same capacitor group fail one after another. In this case, as two or three unit capacitors fail, an unbalanced current twice or three times that of one failure flows through the unbalanced current transformer 6, so the output of the detection relay 7 is Progress from level 0 to level 3. Therefore, in FIG. 1, during level 1 operation, the memory circuit 21 is set via the NOT circuits 15 and 16, and a failure alarm for one unit capacitor is output. During level 2 operation, the memory circuit 23 is connected via NOT circuits 17 and 18.
is set, a failure alarm for two unit capacitors is outputted via the OR circuit 27, and a trip command is issued after a certain period of time by the on-delay circuit 29. NOT circuit 19 during level 3 operation,
20 and an OR circuit 28, an immediate trip command is output.

In case (2), in FIG. 2, for example, two capacitors fail in the first group 1, and then one fails in the second capacitor group 2. In this case, if two capacitors fail in the first capacitor group 1, level 2 will operate as in case (1), but if one fails in the second capacitor group 2, the capacitor bank arranged in a bridge will operate. When viewed as a whole, the impedance of each capacitor group is apparently the same as if one failure occurred in the first capacitor group 1, and therefore there is one failure in the unbalanced current current transformer 6. Only unbalanced current flows, indicating that three unit capacitors are faulty, but detection relay 7
The output will be level 1. Next, in Figure 1,
The first level 1 and level 2 operations are the same as the case (1) above, but when level 2 is restored and the second level 1 operation is performed, the memory circuit 23 stores the information that level 2 has been activated. Since this output is memorized by the set output of 17, is ANDed, and through an OR circuit 28, it is determined that three are faulty and a trip command is output. Therefore, the three failures in this case are determined on the condition that level 2 is restored after being activated once.

Next, in the case of (3), in Fig. 2, if one failure occurs in the first capacitor group 1, level 1 is activated, but then, if the second failure occurs, for example, in the second capacitor group 2. When this occurs, the first capacitor group 1
Since the capacitor second group 2+ impedance becomes equal, no unbalanced current passes through the unbalanced current current transformer 6, and the outputs of the detection relays 7 become level 0, although there are two failures. Next, when a third unit capacitor failure occurs, the impedance balance is disrupted again, and only the unbalanced current at the time of one failure flows through the unbalanced current current transformer 6, and the output of the detection relay 7 is
Although there are 3 failures, it changes to level 1. Then the first
In the figure, level 1 occurs when one unit capacitor fails.
During operation, one unit capacitor failure alarm output is issued in the same way as in (1). Next, when the level changes from level 1 to level 0 due to failure of two capacitors, the fact that level 1 has been activated is memorized by the set output of the memory circuit 21, and the output is led to the input of the AND circuit 24, and then NOT the condition that there is a change from level 1 to level 0, that is, level 1 has returned.
Take this from the output of circuit 15 and apply it to AND circuit 2.
4 is led to the other input, an AND is performed, and a two-failure alarm and a trip command after a certain period of time are outputted via the memory circuit 22 and OR circuit 27. That is, after once operating at level 1, it is determined that two units have failed on the condition that level 1 is restored again. Further, this condition is held at the set output of the memory circuit 22.
Next, when one more unit capacitor fails, making a total of three failures, the output of the detection relay 7 becomes level 0.
It changes to level 1 again. In this case, since the memory circuit 22 stores that the level has returned from level 1 to level 0, that is, that there are two failures,
This output is led to one input of the AND circuit 25,
The other input indicates that level 1 has been activated again, which is derived from the outputs of NOT circuits 15 and 16 and is ANDed.
A trip command is output via the OR circuit 28. That is, on the condition that the level 1 output operates once, then returns, and then operates again, it is determined that three unit capacitors have failed.

Next, the reset of the memory circuits 21, 22, 23 is as follows.
The condition that the breaker 8 is open and the control power supply abnormality, which also includes a power cut, are combined into an OR circuit 30.
Perform an OR using the output, and apply a reset using the output.

[Effects of the Invention] As explained above, according to the present invention, in a capacitor bank arranged in a bridge shape, the number of failures of unit capacitors constituting a capacitor group is reliably determined, and an alarm and a time limit are issued according to the number of failures. It outputs signals such as trips and trip commands, making it possible to provide optimal protection according to the number of failures. In addition, with conventional protection devices, even a failure in one unit capacitor could cause the disconnector to trip immediately and stop the entire system, but with the present invention, the number of failures that can continue the capacitor bank operation, Alternatively, the trip command is not immediately output within the time period during which operation can be continued, thereby improving the reliability of the entire system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a capacitor bank protection device according to the present invention, FIG. 2 is a block diagram of a capacitor bank, and FIG. 3 is a characteristic diagram of a detection relay. 1...Capacitor 1st group, 2...Capacitor 2nd group
Group, 3...Capacitor 3rd group, 4...Capacitor 4th group
Group, 5... Load current current transformer, 6... Unbalanced current current transformer, 7... Detection relay, 8... Edge breaker, 9... Detection relay characteristic 1, 10... Detection relay characteristic 2, 11... Detection relay characteristic 3, 12...Detection relay level 1 output area, 13...Detection relay level 2 output area, 14
...Detection relay level 3 output range, 15-20...
NOT circuit, 21-23...Memory circuit, 24-26
...AND circuit, 27, 28, 30...OR circuit, 29
...On-day delay circuit.

Claims (1)

[Claims] 1. In a capacitor bank protection device in which a capacitor group consisting of a large number of unit capacitors is arranged in a bridge shape, and a failure of a unit capacitor constituting each capacitor group is detected and protected by an unbalanced current, a detection relay has a plurality of It has a current level output to detect the unbalance of the bridge according to the magnitude of the unbalanced current, and according to the number of failures of the unit capacitor according to each current level output of the detection relay and the operating order of each current level output. What is claimed is: 1. A capacitor bank protection device that derives a detection output from a faulty capacitor and outputs an alarm or a trip command depending on the number of faulty capacitors.