JPH05891B2 - - Google Patents
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- Publication number
- JPH05891B2 JPH05891B2 JP56190308A JP19030881A JPH05891B2 JP H05891 B2 JPH05891 B2 JP H05891B2 JP 56190308 A JP56190308 A JP 56190308A JP 19030881 A JP19030881 A JP 19030881A JP H05891 B2 JPH05891 B2 JP H05891B2
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- Prior art keywords
- voltage
- resistor
- power supply
- ecl
- circuit
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017545—Coupling arrangements; Impedance matching circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Logic Circuits (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Dc Digital Transmission (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Description
【発明の詳細な説明】
本発明は、ECL終端回路、特に、ECL回路で
伝送線路を駆動する場合に伝送線路の両端を終端
するためのECL終端回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an ECL termination circuit, and particularly to an ECL termination circuit for terminating both ends of a transmission line when the ECL circuit drives the transmission line.
第１図は従来のECL終端回路の一例を示す回
路図で、ECL回路１０からECL回路２０へ信号
を伝送する場合に用いられるECL終端回路を示
している。 FIG. 1 is a circuit diagram showing an example of a conventional ECL termination circuit, and shows an ECL termination circuit used when transmitting a signal from an ECL circuit 10 to an ECL circuit 20.
伝送線路３０はECL回路１０からECL回路２
０へ信号を伝送するためのものであり、第１図に
は示されていないが実際には直流抵抗ｒをもつて
いる。 The transmission line 30 connects the ECL circuit 10 to the ECL circuit 2
Although not shown in FIG. 1, it actually has a DC resistance r.
ECL回路２０には終端抵抗４０が接続されて
いる。 A terminating resistor 40 is connected to the ECL circuit 20.
ECL回路１０および２０は一般的なECL回路
であるので詳細な動作説明は省略するがECL回
路２０では入力端子１３における端子電圧V13と
比較電圧VRFEを比較して端子電圧V13が高ければ
出力端子１４における端子電圧V14が高レベルに
なり、低ければ端子電圧V14が低レベルになるよ
う動作する。 Since the ECL circuits 10 and 20 are general ECL circuits, a detailed explanation of their operation will be omitted, but in the ECL circuit 20, the terminal voltage V 13 at the input terminal 13 is compared with the comparison voltage V RFE , and if the terminal voltage V 13 is higher, then It operates so that the terminal voltage V 14 at the output terminal 14 becomes a high level, and if it is low, the terminal voltage V 14 becomes a low level.
ECL回路１０もECL回路２０と同様な動作を
する。 The ECL circuit 10 also operates in the same way as the ECL circuit 20.
いま、ECL回路１０の出力端子１２における
端子電圧V12が高レベルのとき高レベル電圧V12H
低レベルのとき低レベル電圧V12Lとし、またECL
回路２０の入力端子１３における端子電圧V13が
高レベルのとき高レベル電圧V13H、低レベルのと
き低レベル電圧V13Lとすると
△VNH＝V13H−VREF
および
ΔVNL＝VREF−V13L
で表される雑音余裕ΔVNH，△VNLが大きければ
各種雑音の影響を受けにくいため回路にとつては
都合がよいことになる。 Now, when the terminal voltage V 12 at the output terminal 12 of the ECL circuit 10 is at a high level, the high level voltage V 12H
When the level is low, the low level voltage is V 12L , and the ECL
When the terminal voltage V 13 at the input terminal 13 of the circuit 20 is at a high level, the high level voltage V 13H is set, and when it is at a low level, the low level voltage V 13L is set. △V NH = V 13H −V REF and ΔV NL = V REF −V If the noise margins ΔV NH and ΔV NL expressed by 13L are large, it is less susceptible to the effects of various noises, which is advantageous for the circuit.
電源電圧VTは終端抵抗４０の一方の端子に接
続された電源から供給されるものであり、端子電
圧V12Lより低い電圧にされる。また、比較電圧、
VREFはECL回路１０，２０の基準電圧であり雑音
余裕ΔVNH，△VNLを最大にするため一般に
１／２（V12H＋V12L）＝VREF
となるように設定される。 The power supply voltage V T is supplied from a power supply connected to one terminal of the terminating resistor 40, and is set to a voltage lower than the terminal voltage V 12L . Also, the comparison voltage,
V REF is a reference voltage for the ECL circuits 10 and 20, and is generally set so that 1/2 (V 12H +V 12L )=V REF in order to maximize the noise margins ΔV NH and ΔV NL .
第２図は第１図に示すような接続にした場合の
伝送線路３０の各部における電圧を示す電圧分布
図である。 FIG. 2 is a voltage distribution diagram showing voltages at various parts of the transmission line 30 when the connections shown in FIG. 1 are made.
第２図からわかるように出力端子の端子電圧
V12が高レベル電圧V12Hのとき入力端子１３の端
子電圧V13は高レベル電圧V13Hとなつており、
V13H＝V12H−V12H−VT／ｒ＋Ｒｒ出力端子１２の端子電
圧V12が低レベル電圧V12Lのとき入力端子１３の
端子電圧V13は低レベルV13Lとなつており、
V13L＝V12L−V12L−VT／ｒ＋Ｒｒ
となる。 As can be seen from Figure 2, the terminal voltage of the output terminal
When V 12 is a high level voltage V 12H , the terminal voltage V 13 of the input terminal 13 is a high level voltage V 13H ,
V 13H = V 12H −V 12H −V T /r+Rr When the terminal voltage V 12 of the output terminal 12 is the low level voltage V 12L , the terminal voltage V 13 of the input terminal 13 is the low level V 13L , and V 13L = V 12L −V 12L −V T /r+Rr.
つまり入力端子１３で雑音余裕ΔVNH，△VNL
は伝送線路３０の直流抵抗のために高レベル側で
はV12H−VT／ｒ＋Ｒｒだけ小さくなり、低レベル側で
は、V12L−VT／ｒ＋Ｒｒだけ大きくなる。 In other words, the noise margin ΔV NH , △V NL at input terminal 13
is reduced by V 12H -V T /r+Rr on the high level side due to the DC resistance of the transmission line 30, and becomes larger by V 12L -V T /r+Rr on the low level side.
このため、この雑音余裕はアンバランスとなり
実質的に減少する。 Therefore, this noise margin becomes unbalanced and is substantially reduced.
すなわち、従来のECL終端回路は雑音余裕が
アンバランスとなり、実質的に減少するという欠
点があつた。 In other words, the conventional ECL termination circuit has the disadvantage that the noise margin becomes unbalanced and is substantially reduced.
本発明の目的は雑音余裕をバランスさせて実質
的に雑音余裕の減少を防止できるECL終端回路
を提供することにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide an ECL termination circuit that can balance the noise margin and substantially prevent reduction in the noise margin.
すなわち、本発明の目的は伝送線路の直流抵抗
によつて高レベル側の雑音余裕が減少し低レベル
側の雑音余裕が増加するというような雑音余裕の
アンバランスをなくし直流抵抗ｒがあつても高レ
ベル側と低レベル側の雑音余裕を等しく、実質的
に最大とすることができるECL終端回路を提供
することにある。 That is, the purpose of the present invention is to eliminate the unbalance of the noise margin in which the noise margin on the high level side decreases and the noise margin on the low level side increases due to the DC resistance of the transmission line, and to An object of the present invention is to provide an ECL termination circuit that can substantially maximize the noise margins on the high level side and the low level side.
本発明のECL終端回路は、伝送線路の一端に
接続された第１のECL回路の出力端子の第１状
態を示す第１出力電圧および第２状態を示す第２
の出力電圧のいずれよりも低い電源電圧をもつ第
１の電源と、前記第１の出力電圧と前記第２の出
力電圧との中間の電源電圧をもつ第２の電源と前
記出力端子と前記第１の電源との間に接続された
第１の抵抗と、前記伝送線路の他端に接続された
第２のECL回路の入力端子と前記第２の電源と
の間に接続された第２の抵抗とを含んで構成さ減
る。 The ECL termination circuit of the present invention has a first output voltage indicating a first state of an output terminal of a first ECL circuit connected to one end of a transmission line, and a second output voltage indicating a second state.
a first power supply having a power supply voltage lower than any of the output voltages of the output terminal, a second power supply having a power supply voltage intermediate between the first output voltage and the second output voltage; a first resistor connected between the first power source and the second power source; and a second resistor connected between the input terminal of the second ECL circuit connected to the other end of the transmission line and the second power source. The resistance is reduced.
さらに、本発明のECL回路は、第２の電源お
よび第２の抵抗のかわりにこれと等価となる複数
の抵抗と電源を用いて構成される。 Further, the ECL circuit of the present invention is configured using a plurality of equivalent resistors and a power source instead of the second power source and the second resistor.
さらに、本発明のECL終端回路は、第１の電
源および第１の抵抗のかわりに定電流源回路を用
いて構成される。 Furthermore, the ECL termination circuit of the present invention is configured using a constant current source circuit instead of the first power supply and the first resistor.
すなわち、本発明のECL終端回路は、ECL回
路の低レベル側の出力電圧よりも低い第１の電源
と低レベルと高レベル出力電圧の中間の電圧にあ
る第２の電源と前記回路の出力と第１の電源との
間に接続された第１の抵抗と前記回路の出力端子
に接続された伝送線路の先端と前記第２の電源と
の間に接続された第２の抵抗とを含んで構成され
る。 That is, the ECL termination circuit of the present invention has a first power supply lower than the output voltage on the low level side of the ECL circuit, a second power supply at a voltage intermediate between the low level and high level output voltages, and the output of the circuit. a first resistor connected between a first power source and a second resistor connected between a tip of a transmission line connected to an output terminal of the circuit and the second power source; configured.
さらに、本発明のECL終端回路は、第２の抵
抗と第２の電源の代りにこれと等価となる複数の
抵抗と電源とを含んで構成される。 Furthermore, the ECL termination circuit of the present invention includes a plurality of equivalent resistors and a power source instead of the second resistor and the second power source.
さらに、本発明のECL終端回路は第１の抵抗
と第１の電源の代りに定電源を含んで構成され
る。 Further, the ECL termination circuit of the present invention includes a constant power source instead of the first resistor and the first power source.
次に、本発明の原理を第３図を用いて説明す
る。 Next, the principle of the present invention will be explained using FIG.
いま、端子電圧V12が高レベル電圧V12Hである
とき、伝送線路３０に流れる電流IHは実線に示す
向きに流れる。 Now, when the terminal voltage V 12 is a high level voltage V 12H , the current I H flowing through the transmission line 30 flows in the direction shown by the solid line.
したがつて、端子電圧V13は出力端子１２より
電圧降下分ｒ・IHだけ低い電圧となる。それゆ
え、電圧降下分ｒ・IHだけ雑音余裕が減少する。 Therefore, the terminal voltage V 13 becomes a voltage lower than the output terminal 12 by the voltage drop r·I H. Therefore, the noise margin is reduced by the voltage drop r·I H.
次に、端子電圧V12が低レベル電圧V12Hである
とき伝送線路３０に流れる電流ILは点線に示す向
きに流れる。 Next, when the terminal voltage V 12 is the low level voltage V 12H , the current I L flowing through the transmission line 30 flows in the direction shown by the dotted line.
したがつて、端子電圧V13は出力端子１２より
電圧降下分ｒ・ILだけ高い電圧となる。それゆえ
電圧降下分ｒ・ILだけ雑音余裕が減少する。 Therefore, the terminal voltage V 13 becomes a voltage higher than the output terminal 12 by the voltage drop r· IL . Therefore, the noise margin is reduced by the voltage drop r· IL .
IH＝V12H−VT／ｒ＋R2
IL＝VTＶ−12L／ｒ＋R2
であるから、
VT＝V12H＋V12L／２
とすると、、IH＝ILとなり高レベル側、低レベル
側の雑音余裕のバランスがとれ最大の雑音余裕を
得ることができる。 I H = V 12H −V T /r+R 2 I L = V T V− 12L /r+R 2 , so if V T = V 12H + V 12L /2, then I H = I L , and the high level side and low The noise margin on the level side is balanced and the maximum noise margin can be obtained.
次に、本発明の実施例について、図面を参照し
て説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第４図は本発明の第１の実施例を示す回路図で
ある。 FIG. 4 is a circuit diagram showing a first embodiment of the present invention.
なお、第４図では、伝送線路３０の直流抵抗ｒ
を線路の中央に書いてあるがこれは線路の全長に
わたつて分布しているものであり便宜上このよう
に図示した。 In addition, in FIG. 4, the DC resistance r of the transmission line 30
is written in the center of the track, but this is distributed over the entire length of the track, and is illustrated like this for convenience.
第５図は第４図に示す伝送線路３０の各部にお
ける電圧を示す電圧分布図である。 FIG. 5 is a voltage distribution diagram showing voltages at various parts of the transmission line 30 shown in FIG. 4.
抵抗R2は高レベル電圧V12Hと低レベル電圧L12H
との中間の電源電圧VT′＝−1.2V（＝
−0.8−1.6V／２）を供給する電源と入力端子１３の
間に接続される。 Resistor R 2 has high level voltage V 12H and low level voltage L 12H
The supply voltage V T ′=−1.2V (=
-0.8-1.6V/2) and the input terminal 13.
出力端子１２が高レベル電圧V12Hのときは伝送
線路３０の上を出力端子１２から入力端子１３に
向つて電流が流れるが、低レベル電圧V12Lのとき
は入力端子１３から出力端子１２に向つて流れ
る。 When the output terminal 12 has a high level voltage V 12H , current flows from the output terminal 12 to the input terminal 13 on the transmission line 30, but when the output terminal 12 has a low level voltage V 12L , the current flows from the input terminal 13 to the output terminal 12. flowing.
しかし、伝送線路３０はECL回路１０のエミ
ツタに接続されているためECL回路１０はこの
電流を引込むことができない。抵抗R1はこの電
流を流してやるため本発明により追加した抵抗で
ある。 However, since the transmission line 30 is connected to the emitter of the ECL circuit 10, the ECL circuit 10 cannot draw this current. The resistor R1 is a resistor added according to the present invention to allow this current to flow.
第４図に示す実施例で雑音余裕ΔVNH，△VNL
が最大となるようすを第５図を用いて説明する。 In the example shown in Fig. 4, the noise margin ΔV NH , ΔV NL
The manner in which the maximum value is reached will be explained using FIG.
出力端子１２における高レベル電圧V12Hは−
0.8V、低レベル電圧V12Lは−1.6V、電源電圧
VT′は本発明により高レベル電圧V12Hと低レベル
電圧、V12Lの中間の電圧−1.2Vに設定する。 The high level voltage V 12H at the output terminal 12 is -
0.8V, low level voltage V 12L is -1.6V, power supply voltage
According to the present invention, V T ' is set to −1.2V, which is an intermediate voltage between the high level voltage V 12H and the low level voltage V 12L .
出力端子１２が高レベル電圧V12Hであるとき、
入力端子１３の高レベル電圧V′13Hは直流抵抗ｒ
のために−0.84Vとなる。また、出力端子１２が
低レベル電圧V12Lであるとき、入力端子のV13L′
は−1.56Vとなる。 When the output terminal 12 is at high level voltage V 12H ,
The high level voltage V' 13H of input terminal 13 is DC resistance r
Therefore, it becomes −0.84V. Also, when the output terminal 12 is at the low level voltage V 12L , the input terminal V 13L ′
becomes −1.56V.
ここで、比較電圧VREFは−1.2Vであるので結
局雑音余裕は
高レベル側では、ΔVNH＝0.36V（＝−0.84V＋
1.2V）
低レベル側は、ΔVNL＝0.36V（＝−1.2V＋
1.56V）
となり、高レベル側と低レベル側はバランスし最
大の雑音余裕を得ることができる。 Here, since the comparison voltage V REF is -1.2V, the noise margin is ΔV NH = 0.36V (= -0.84V +
1.2V) On the low level side, ΔV NL = 0.36V (=-1.2V+
1.56V), the high level side and low level side are balanced and the maximum noise margin can be obtained.
第６図は本発明の第２の実施例を示す回路図で
ある。 FIG. 6 is a circuit diagram showing a second embodiment of the present invention.
抵抗１９はGNDと入力端子１３の間に接続さ
れ抵抗２１は入力端子１３と電源電圧VEE（＝−
5.2V）を供給する電源との間に接続されている。 The resistor 19 is connected between GND and the input terminal 13, and the resistor 21 is connected between the input terminal 13 and the power supply voltage V EE (=-
5.2V).
これは抵抗値と電源電圧の関係から第４図に示
す抵抗R2と電源電圧V′Tを供給する電源とで構成
する回路と等価であり本発明に含まれる。 This is equivalent to the circuit shown in FIG. 4 consisting of a resistor R 2 and a power supply that supplies the power supply voltage V' T from the relationship between the resistance value and the power supply voltage, and is included in the present invention.
また、トランジスタ１７、抵抗R18および定電
圧源VCCは定電流回路を構成しこれも本発明に含
まれる。 Further, the transistor 17, the resistor R18 , and the constant voltage source V CC constitute a constant current circuit, which is also included in the present invention.
本発明のECL終端回路は、出力端子に抵抗を
接続するとともに入力端子に抵抗を介して接続す
る電源の電圧を出力端子における２値状態を示す
電圧の中間に設定することにより、高レベル側と
低レベル側の雑音余裕をバランスさせ最大の雑音
余裕を得ることができるという効果がある。 The ECL termination circuit of the present invention connects a resistor to the output terminal and sets the voltage of the power supply connected to the input terminal via the resistor to be between the voltages indicating the binary state at the output terminal. This has the effect of being able to balance the noise margin on the low level side and obtain the maximum noise margin.
第１図は従来のECL終端回路の一例を含む回
路図、第２図は第１図に示す伝送線路の各部の電
圧を示す電圧分布図、第３図は本発明で得られる
効果の原理を説明するための原理説明図、第４図
は本発明の第１の実施例を含む回路図、第５図は
第４図に示す伝送線路の各部の電圧を示す電圧分
布図、第６図は本発明の第２の実施例を含む回路
図である。
１０，２０……ECL回路、３０……伝送線路、
４０，R1，R2……抵抗、ｒ……直流抵抗、１１，
１３……入力端子、１２，１４……出力端子、
V12，V13……端子電圧、V12H，V13H，V13H′……
高レベル電圧、V12L，V13L，V13L′……低レベル
電圧、VREF……比較電圧、VT，VT′，VEE……電
源電圧、IH，IL……電流。
Fig. 1 is a circuit diagram including an example of a conventional ECL termination circuit, Fig. 2 is a voltage distribution diagram showing voltages at various parts of the transmission line shown in Fig. 1, and Fig. 3 shows the principle of the effect obtained by the present invention. 4 is a circuit diagram including the first embodiment of the present invention, FIG. 5 is a voltage distribution diagram showing voltages at various parts of the transmission line shown in FIG. 4, and FIG. 6 is a diagram for explaining the principle. FIG. 3 is a circuit diagram including a second embodiment of the present invention. 10, 20...ECL circuit, 30...transmission line,
40, R 1 , R 2 ... resistance, r ... DC resistance, 11,
13...Input terminal, 12,14...Output terminal,
V 12 , V 13 ... terminal voltage, V 12H , V 13H , V 13H ′...
High level voltage, V 12L , V 13L , V 13L ′...Low level voltage, V REF ...Comparison voltage, V T , V T ', V EE ... Power supply voltage, I H , I L ... Current.
Claims (1)
路の出力端子の第１状態を示す第１の出力電圧お
よび第２状態を示す第２の出力電圧のいずれより
も低い電源電圧をもつ第１の電源と、前記第１の
出力電圧と前記第２の出力電圧との中間の電源電
圧をもつ第２の電源と、前記出力端子と前記第１
の電源との間に接続された第１の抵抗と、前記伝
送線路の他端に接続された第２のECL回路の入
力端子と前記第２の電源との間に接続された第２
の抵抗とを含むことを特徴とするECL終端回路。 ２ 伝送線路の一端に接続された第１のECL回
路の出力端子の第１状態を示す第１の出力電圧お
よび第２の状態を示す第２の出力電圧のいずれよ
りも低い電源電圧をもつ第１の電源と、前記第
1ECL回路の出力端子と前記第１の電源との間に
接続された第１の抵抗と、前記伝送線路の他端に
接続された第２のECL回路の入力端子と接地電
位との間に接続された第３の抵抗と、一端が前記
入力端子に接続された第４の抵抗と、前記第３の
抵抗と前記第４の抵抗との接続点における電圧値
が前記第１の出力電圧と前記第２の出力電圧の中
間の値となるように前記第４の抵抗の他端に接続
された第３の電源とを含むことを特徴とする
ECL終端回路。 ３ 伝送線路の一端に接続された第１のECL回
路の出力端子の第１状態を示す第１の出力電圧お
よび第２状態を示す第２の出力電圧のいずれより
も低い電圧をもつ第１の電源と、前記出力端子に
接続されたコレクタをもつ第１のトランジスタ
と、前記第１のトランジスタのエミツタと前記第
１の電源との間に接続された第４の抵抗と、前記
第１の出力電圧および前記第２の出力電圧の中間
の電圧をもつ第２の電源と、前記伝送線路の他端
に接続された第２のECL回路の入力端子と前記
第２の電源との間に接続された第２の抵抗とを含
むことを特徴とするECL終端回路。[Claims] 1. Lower than either of the first output voltage indicating the first state and the second output voltage indicating the second state of the output terminal of the first ECL circuit connected to one end of the transmission line. a first power supply having a power supply voltage; a second power supply having a power supply voltage intermediate between the first output voltage and the second output voltage;
a first resistor connected between the second power source and an input terminal of a second ECL circuit connected to the other end of the transmission line;
An ECL termination circuit comprising a resistor. 2. A first ECL circuit having a power supply voltage lower than either of the first output voltage indicating the first state and the second output voltage indicating the second state of the output terminal of the first ECL circuit connected to one end of the transmission line. 1 power supply, and the said 1st power supply.
1 A first resistor connected between an output terminal of the ECL circuit and the first power source, and a ground potential and an input terminal of a second ECL circuit connected to the other end of the transmission line. a fourth resistor whose one end is connected to the input terminal, and a voltage value at a connection point between the third resistor and the fourth resistor is equal to the first output voltage and the fourth resistor. and a third power supply connected to the other end of the fourth resistor so as to have an intermediate value of the second output voltage.
ECL termination circuit. 3. A first output voltage having a voltage lower than either of the first output voltage indicating the first state and the second output voltage indicating the second state of the output terminal of the first ECL circuit connected to one end of the transmission line. a first transistor having a collector connected to a power source; a fourth resistor connected between an emitter of the first transistor and the first power source; and a fourth resistor connected to the first output terminal. and a second power supply having a voltage intermediate between the voltage and the second output voltage, and a second power supply connected between the input terminal of the second ECL circuit connected to the other end of the transmission line and the second power supply. and a second resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56190308A JPS5892139A (en) | 1981-11-27 | 1981-11-27 | Ecl terminating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56190308A JPS5892139A (en) | 1981-11-27 | 1981-11-27 | Ecl terminating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5892139A JPS5892139A (en) | 1983-06-01 |
| JPH05891B2 true JPH05891B2 (en) | 1993-01-07 |
Family
ID=16255995
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56190308A Granted JPS5892139A (en) | 1981-11-27 | 1981-11-27 | Ecl terminating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5892139A (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61152124A (en) * | 1984-12-26 | 1986-07-10 | Hitachi Ltd | Output buffer of integrated circuit |
| JPS631113A (en) * | 1986-06-20 | 1988-01-06 | Fujitsu Ltd | Semiconductor integrated circuit |
| JPH04299613A (en) * | 1991-03-27 | 1992-10-22 | Nippon Avionics Co Ltd | Ecl termination circuit |
| JP2870288B2 (en) * | 1992-03-17 | 1999-03-17 | 株式会社日立製作所 | Bidirectional signal transmission circuit |
| JPH07135513A (en) * | 1993-09-17 | 1995-05-23 | Fujitsu Ltd | Method and device for controlling termination of current-driven circuit |
| JP3512168B2 (en) * | 1999-04-21 | 2004-03-29 | 松下電器産業株式会社 | Signal transceiver |
| EP1047149A3 (en) | 1999-04-21 | 2003-02-12 | Matsushita Electric Industrial Co., Ltd. | Signal transmitting/receiving apparatus |
-
1981
- 1981-11-27 JP JP56190308A patent/JPS5892139A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5892139A (en) | 1983-06-01 |
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