JPH0589666A - Operating-mode changeover circuit and flip-flop circuit - Google Patents

Abstract

(57) [Summary] [Object] To provide an operation mode switching circuit capable of facilitating pattern layout of a semiconductor integrated circuit device having a plurality of operation modes. A first and a second inverter whose inputs and outputs are cross-coupled to each other, a capacitor C1 connected between a first inverter output terminal and a ground node of the first inverter, and a second capacitor It includes a capacitor C2 connected between the output terminal of the inverter and the ground line. The magnitude relationship between the capacitance values of the stray capacitance C3, the capacitance C1, and the capacitance C2 between the ground node and the ground line of the first inverter is C3 <C2 <
It is set to C1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operation mode switching circuit and a flip-flop circuit incorporated in a semiconductor integrated circuit device having a plurality of operation modes and switching the plurality of operation modes to a predetermined operation mode.

[0002]

2. Description of the Related Art Semiconductor integrated circuit devices are rapidly becoming faster and more multifunctional. Such functions include a page mode and a nibble mode in a dynamic semiconductor memory device (hereinafter referred to as DRAM). The circuit for performing this nibble mode and page mode operation is
They are simultaneously assembled at the wafer stage and switched to either one of the operation modes at the assembly stage. Here, in the nibble mode, for example, in a 4-bit semiconductor memory device, when a row address and a column address are given, a 1-bit memory cell is accessed in response to the row address and the column address to obtain the row address. In this operation, the column address is strobed while the strobe signal is held in the active state, and the subsequent 3-bit memory cell is accessed. The page mode is an operation mode in which the content of the bit of each column designated during the reading and rewriting of one row is output to the outside.

FIG. 4 is a diagram showing a conventional DRAM having a circuit for switching operation modes. In FIG. 4, this D
The RAM includes a package 5, a ground terminal GND, a power supply terminal Vcc and other external terminals provided in the package 5, and a DRAM chip 4 mounted in the package 5. The circuit for switching the operation mode includes a bonding pad 1 arranged near the power supply terminal Vcc provided in the package 5, a bonding pad 2 arranged near the ground terminal GND, a bonding pad 1 and a bonding pad 2. And a connection line 3 provided between the two. The connection line 3 is connected to the nibble / page decoder. When the potential of the connection line 3 is the power supply potential Vcc (H level), the nibble / page decoder performs the operation corresponding to the above-mentioned nibble operation so that the memory cell of the designated bit and the memory cell of the bit subsequent thereto are performed. Are sequentially selected. When the potential of the connection line 3 is GND (L level), the column address is strobed for each column address strobe signal in order to perform the operation corresponding to the page mode operation described above.

Further, in FIG. 4, in order to operate in the page mode, the bonding pad 2 is connected to the ground terminal GND through the metal wiring 6 and an L level signal is given to the nibble / page decoder. However, the nibble mode operation can be performed by connecting the bonding pad 1 to the power supply terminal Vcc and applying an H level signal to the nibble / page decoder.

[0005]

However, in the circuit shown in FIG. 4, the power supply terminal Vcc and the ground terminal GND are used.
Bonding pads 1 and 2 are provided near both of them, and a connecting line 3 is provided between both bonding pads. Therefore, there is a drawback that flexibility is lacked when the pattern layout of the DRAM is performed.

It should be noted that such switching of the operation mode is performed by the D
It is also required for RAM and various other semiconductor integrated circuit devices, and similar problems occur in those integrated circuit devices.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an operation mode switching circuit and a flip-flop circuit which can solve the above-mentioned drawbacks of the conventional example and easily perform pattern layout of a semiconductor integrated circuit device. ..

[0008]

An operation mode switching circuit according to the present invention is incorporated in a semiconductor integrated circuit device having a plurality of operation modes, and is an operation mode switching circuit for switching the plurality of operation modes to a desired operation mode. It has the following features. That is, the first and second inverting amplification means, whose input terminals are connected to their output terminals, the output terminal of the first inverting amplification means, and the ground terminal or the power supply terminal of the first inverting amplification means. And a capacitance value smaller than that of the first capacitance means connected between the first capacitance means connected between the first capacitance means and the output terminal of the second inverting amplification means and the ground line or the power supply line. Second capacitance means, and the first
And a means for bringing the ground terminal or the power supply terminal of the inverting amplifier means into a floating state.

[0009]

In the present invention described above, the means for bringing the ground terminal or the power supply terminal of the first inverting amplifier means to the floating state is provided. When the ground terminal of the first inverting amplification means is not set in the floating state (grounded),
Since the capacitance value of the first capacitance means is smaller than the capacitance value of the second capacitance means, the output of the second inverting amplification means rises first, and the output of the first inverting amplification means does not rise. .. Thereby, the output level of the second inverting amplification means can be fixed to the power supply potential. With the output fixed to the power supply potential, the operation mode of the semiconductor integrated circuit device can be switched to a desired operation mode.

On the contrary, when the ground terminal of the first inverting amplification means is set in the floating state, the first inverting amplification means is grounded and the first capacitance means does not function.
The first inversion means rises faster than the second inversion amplification means. Thereby, the output level of the second inverting amplification means can be fixed to the ground potential. The operation mode of the semiconductor integrated circuit device can be switched to a desired operation mode by the output having the ground potential.

The same operation as described above can be achieved by bringing the power supply terminal of the first inverting amplifier means to the power supply potential or floating state.

[0012]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a DR equipped with the operation mode switching circuit of FIG.
It is a block diagram of AM.

Referring to FIG. 2, the DRAM of FIG. 2 is different from the DRAM of FIG. 4 in that operation mode switching circuit 7 and fuse wiring 10 are provided in place of bonding pad 1 and connection line 3. is there. The other circuits are the same as those of the circuit of FIG. 4, and the same reference numerals are given and the description thereof will be appropriately omitted. Operation mode switching circuit 7
Outputs a power supply potential signal when the bonding pad 2 is grounded by the fuse wiring 10 and outputs an L level signal when the fuse wiring 10 is blown. As a result, the nibble / page decoder can be controlled to select either the nibble mode or the page mode.

Next, referring to FIG. 1, the operation mode switching circuit includes a first inverter 8, a second inverter 9, a capacitor C1 and a capacitor C2. Reference numeral 2 is a bonding pad (see FIG. 1), and C3 is a stray capacitance between the ground node N3 and the ground line. The first inverter 8 has a P
Channel transistor 8a and N-channel transistor 8
b and. P-channel transistor 8a has its source coupled to power supply potential Vcc, and its drain together with the drain of N-channel transistor 8b at output node N.
1 and its gate is an N-channel transistor 8
It is connected to the input node N2 together with the gate of b. The source of the N-channel transistor 8b has a ground node N3.
Is connected to the bonding pad 2 via.

Second inverter 9 includes a P channel transistor 9a, an N channel transistor 9b, an input node N4 and an output node N5. The connection relationship between the P-channel transistor 9a and the N-channel transistor 9b is the same as that of the first inverter 8. However, the input node N4 is connected to the output node N1 of the first inverter 8, and the output node N5 is connected to the input node N2 of the first inverter 8. That is, the first inverter 8 and the second inverter 9 are CMOS inverters, and also form a flip-flop circuit by cross-coupled connection.

The capacitor C1 is connected between the output node N1 of the first inverter 8 and the ground node N3.

The capacitor C2 is connected between the output node N5 of the second inverter 9 and the ground line.

The capacitance values of the capacitances C1 and C2 and the stray capacitance C3 have a relationship of C3 <C2 <C1.

Next, the operation of the operation mode switching circuit shown in FIGS. 1 and 2 will be described. When the DRAM is operated in the nibble mode, the bonding pad 2 is connected to the ground terminal GND of the package 5 as shown in FIG. The potentials of the bonding pad 2 and the ground node N3 become the ground potential GND. In this state, when the power supply voltage Vcc is turned on, the output node N1 of the first inverter 8 and the second
Of the output node N5 of the inverter 9 of the power supply potential Vc
However, the capacitance value of the capacitance C1 is the capacitance C
Since it is larger than the capacitance value of 2, the output node N5 of the second inverter 9 rises earlier and the power supply potential Vcc
(H level). Since the output node N5 is connected to the input node N2 of the first inverter 8, the output of the first inverter 8 is fixed to the ground potential GND (L level).

By applying the power supply voltage Vcc in this manner, the output of the second inverter 9 can be fixed at the H level. The H level signal is applied to the nibble / page decoder, and the nibble / page decoder specifies the Nigro mode operation in response to the H level signal.

Next, in the page mode operation, the fuse line 10 is blown to set the operation mode switching circuit in a floating state. That is, the ground node N3 of the first inverter 8 is coupled to the ground potential via the series connection of the capacitance C1 and the floating capacitance C3. Since the capacitance value of the capacitance C1 is made larger than that of the capacitance C3, the coupling capacitance is determined by the capacitance value of the capacitance C3.

In this state, when the power supply potential Vcc is applied, the capacitance value of the capacitance C2 is larger than the capacitance value of the capacitance C3, so that the first inverter 8 rises first and the potential of the output node N1 changes to the power supply potential. The potential becomes Vcc (H level). The output node N5 of the second inverter 9 receives the output (H level) of the first inverter 8 and receives the ground potential GN.
It is fixed at D (L level). By applying this L level signal to the nibble / page decoder, page mode operation can be designated.

As described above, the operation mode switching circuit of this embodiment has one bonding pad,
Moreover, since it is not necessary to use the connection line 3 (see FIG. 4), there is no restriction in the layout of the circuit pattern. The first and second inverters 8 and 9 are C
Since it is composed of a MOS inverter, almost no direct current flows. Therefore, the power consumption is very low.

In the above embodiment, the ground node N3 of the first inverter 8 is connected to the bonding pad via the fuse wiring 10, and the first and second inverters are formed depending on whether or not the fuse wiring 10 is blown. The logic level of the flip-flop circuit is changed. However, instead of this, the power supply terminal of the first inverter is connected to the bonding pad via the fuse wiring 10, and the flip-flop is melted depending on whether the fuse wiring 10 is blown. The logic level of can be changed. An example of this is shown in FIG.

[0025]

As described above, according to the present invention, the ground node N3 of the first inverter 8 is connected to the ground potential (or power supply potential).
Since the operation mode can be switched depending on whether it is connected to or connected to the floating state, it is not necessary to provide wiring between two bonding pads as in the conventional example. As a result, the effect that the pattern layout can be easily performed is obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram of a DRAM including the operation mode switching circuit of FIG.

FIG. 3 is a circuit diagram showing another embodiment of the present invention.

FIG. 4 is a circuit diagram for switching a conventional operation mode.

[Explanation of symbols]

 2 bonding pad 8 first inverter 9 second inverter 10 fuse wiring C1, C2 capacitance C3 stray capacitance

Claims (2)

[Claims] 1. An operation mode switching circuit which is built in a semiconductor integrated circuit device having a plurality of operation modes and which switches the plurality of operation modes to a desired operation mode, wherein each input terminal is connected to each output terminal. First and second inverting amplification means, and first capacitance means connected between an output terminal of the first inverting amplification means and a ground terminal or a power supply terminal of the first inverting amplification means, Second capacitance means connected between the output terminal of the second inverting amplification means and a ground line or a power supply line and having a capacitance value smaller than that of the first capacitance means; and the first inversion means. And a means for bringing a ground terminal or a power supply terminal of the amplification means into a floating state. 2. A flip-flop circuit built in a semiconductor integrated circuit device, wherein first and second inverting amplification means have their input terminals connected to their output terminals, and said first inverting amplification means. First capacitance means connected between the ground terminal or the power supply terminal of the means, and between the output terminal of the second inverting amplification means and the ground line or the power supply line, and the first capacitance means A flip-flop circuit comprising: second capacitance means having a smaller capacitance value than that of the first inverting amplification means; and means for bringing the ground terminal or the power supply terminal of the first inverting amplification means into a floating state.