JPH059749B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to audio signal transmission, recording and reproduction,
The present invention relates to a display device that can display various types of information required during signal processing and the like on a display surface (hereinafter also simply referred to as a "display surface") of the display device.

[Prior art and problems to be solved by the invention]

When transmitting, recording and reproducing audio signals, and processing signals, etc., settings of the recording level and recording time of the audio signal must be made in consideration of the dynamic range and recording capacity of the signal transmission path, recording medium, and equipment used. The peak level of the audio signal and the VU
(Volume Unit) Instruments that indicate the level, indicators and timers that indicate the maximum value of the peak level within a certain period of time (for example, 3 seconds) up to the present time have been used in the past.

As such instruments and indicators, instruments with pointers and indicators with arrays of light emitting elements have generally been used, and as timers, mechanical clocks and electronic clocks have been used. Digital clocks and the like have been used as is well known.

By the way, when performing audio signal transmission, recording and playback, and other signal processing in good conditions, it is necessary to be able to know the VU level and peak level individually, and also clearly see the relationship between these levels. It is desirable that this is done, but
If each level is displayed using a separate meter, it is difficult to directly see the relationship between the VU level and the peak level.

Furthermore, recently, there has been an expectation for the appearance of display devices that can simultaneously monitor both image (video) information and audio signals related thereto.

[Means to solve the problem]

The present invention relates to the display surface (hereinafter also simply referred to as "display surface") of a display device, such as a CRT (cathode ray tube) that can display TV images and a TV receiver that often uses this. ) provides a display device that can display various types of information necessary when processing audio signals in real time.
VU level, peak level, and other information are calculated based on the digital data within a predetermined time width obtained by the converter and this AD converter, and the level is calculated based on the calculation results. a central control unit that outputs predetermined pattern information corresponding to the type and size of the image; and a video signal generator (video・Display processor) and a display device that displays the output data from this video signal generator, and displays the VU level, peak level, or other information of the audio signal on the display surface of the display device in real time. It is designed so that it can be displayed.

〔Example〕

Hereinafter, specific embodiments of the display device of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of the display device of the present invention, and in this figure, 1 and 2 are 2ch
(channel) signals, L (left) ch and R respectively
(Right) Channel input terminals, BAl, BAr are buffer amplifiers, BPFl, BPFr, etc. are band wave rectifiers, FRl, FRr are double wave rectifiers, and the subscripts l and r are for left and right channels, respectively.
Shows ch. The passbands of the bandpass filters BPFl and BPFr have the same passband characteristics so that they can pass the frequency range necessary for measuring the VU level and peak level of the audio signal.

In addition, TER in the figure is a timer, and VR is a timer.
Variable resistor for time width setting set to TER,
MPX is a multiplexer, CPU is a central controller,
RAM is the main memory, VDP is the video signal generator (video display processor),
RAM is a video ram, CRT is a display device (hereinafter simply referred to as "display", and in this example a cathode ray tube is used), and ADC is
AD converters, 3 to 5 (5a, 5b) are data buses, RFC is an RF converter, and TVS is a TV receiver.

The video signal generator VDP is connected to a video ram V.
It operates as an interface between the RAM and the central control unit CPU, and the image content is determined by various data stored in the video RAM VRAM. It is configured to be able to generate video signals. An example of such a video signal generator VDP is the video display manufactured by Texas Instruments, Inc., which was introduced in Nikkei McGraw-Hill's "Nikkei Electronics" March 30, 1981 issue (p.156 to p.164).・Processor (VDP)
You can use the video signal generator in the following description
Assume that a video display processor is used as the VDP.

FIG. 2 is a diagram showing an example of the memory map of the video RAM VRAM. As shown in this memory map, 1024 bytes from address 0 to address 1023 are used as a sprite, generator table, and SGT. , 1024 to 1791
768 bytes up to address are pattern name table
Used as PNT and also from 1792 to 1919
The 128 bytes up to the address are the sprite attribute table
Used as SAT and furthermore, from address 1920 to 1951
The 32 bytes up to the address are used as the color table CT, and the 2048 bytes from address 2048 to address 4095 are used as the pattern generator table PGT. Note that 96 bytes from address 1952 to address 2047 are unused.

The pattern generator table PGT is
For example, 8 by 8 pixels each use 8 bytes.
Since it remembers two specific patterns, 8x8
Can store 256 types of pixel patterns. The pattern information stored in this pattern generator table PGT is stored in the central controller CPU.
Due to the operation of the device, read-only (hereinafter referred to as “read-only”) memory
It is transferred from ROM, but the pattern
The generator table PGT may be used as a read-only memory.

Each of the above-mentioned 8×8 pixel specific patterns individually stored in the pattern generator table PGT is identified as a specific pattern by a pattern name given to each storage area in which each specific pattern is stored. be specified. In the example shown in the second figure, 256 types of patterns can be specified by pattern names #0 to #255.

Next, the pattern name table PNT is used to store information indicating which pattern name in the pattern generator table PGT each display section displayed on the display surface of the display CRT corresponds to. It has a storage capacity corresponding to the total number of display sections.

In the example shown in Figure 3, the total number of sections set on the display screen is (32 columns) x (24 rows) = 768, and since 1 byte is used as the amount of information indicating one section, the pattern name Table PNT has a storage capacity of 768 bytes as described above.

As mentioned above, the required number of patterns are stored in the pattern generator table PGT in the video RAM VRAM, and the required pattern name assigned to each pattern is When the name table PNT is stored in each section of the display surface, the video display processor VDP combines the information stored in the pattern name table PNT in the video RAM VRAM and the pattern generator table PGT. generates a composite video signal in accordance with a specific standard format whose image content is determined by the information stored in the color table CT and, if necessary, the information stored in the color table CT, and supplies it to the display CRT; A specific pattern is displayed on the display surface of a display CRT.

In the above explanation, a display mode (so-called graphics mode) in which a specific pattern stored in the pattern generator table PGT is displayed in a specific section within 768 sections on the display screen is used. When displaying a pattern in this graphic mode, the position of the pattern is specified by the pattern name table PNT, so when moving any one pattern on the display screen,
The pitch of pattern movement is one section (distance of 8 pixels) on the display screen.

Therefore, in order to reduce the pitch of movement of the pattern on the display surface and make the pattern move smoothly, the sprite generator table
The pattern is stored in the SGT and can be moved within the display screen at a pitch of one pixel by changing the coordinates.

The pattern stored in the sprite generator table SGT is 8x8 pixel or 16x16 pixel sprite data. For each pattern stored in this sprite generator table SGT, #0, #1,
..., #N, and the sprite surfaces corresponding to the patterns with each sprite name have a higher priority as the numerical value indicated by the sprite name is smaller.

In the memory map of the video RAM VRAM shown in Figure 2, as mentioned above, the sprite generator table SGT starts from address 0.
Since 1024 bytes up to address 1023 are used, in this example, if the pattern is 8 x 8 pixels, 128 patterns (sprite names #0 to
#127) can be memorized, and if the pattern is 16 x 16 pixels, 32 patterns (sprite name #0 ~
#31) can be memorized. In video RAM V RAM, sprite generator table
If 2048 bytes are allocated to SGT, the number of patterns that can be stored in sprite generator table SGT is doubled.

The sprite attribute table SAT uses 4 bytes for each sprite to specify the sprite's position {1 byte each for specifying vertical and horizontal positions},
Name of display sprite (1 byte), color code and end code of display sprite (1 byte)
etc. are set, so the sprite attribute table
If 128 bytes are used for SAT, information for 32 sprites is stored in this sprite attribute table SAT.

The position of the sprite is in the horizontal (X) direction on the display surface.
The coordinates of 49152 pixels determined by 256 pixels (8 pixels x 32 sections) and 192 pixels in the vertical (Y) direction (8 pixels x 24 sections) are determined by the vertical position {what number of pixels in the vertical direction? } and horizontal position {number indicating which pixel it is in the horizontal direction} are written to the sprite attribute table SAT {the base point of the sprite is the upper left edge), and the sprite is moved. is 1
It can be done at pixel pitch.

In the display device of the present invention, a plurality of types of patterns are stored in a pattern generator table PGT, a sprite generator table SGT, etc., and patterns to be displayed on the display surface are selected and patterns are moved. The sprite attribute table specifies the VU level, peak level hold value, and maximum VU (and peak) level of the audio signal.
By configuring the display to be performed using the data written in the SAT, a specific pattern can be displayed on the display surface in a movable manner.
In addition, the data written in the pattern name table PNT corresponding to the peak level of the audio signal, the time elapsed information on the timer, etc., is used to select the pattern and specify the movement mode of the pattern. It is possible to display a specific pattern on the display surface.

FIG. 4 shows an example of how various information is displayed on the display surface of the display device of the present invention, and the letters L and R in this figure are respectively
This is a display pattern for displaying the distinction between Lch and Rch on the display surface, and is displayed approximately at the center of the display surface.
Numbers such as ∞, -30, -20, . . . , 6, 8, 10, etc. are display patterns for displaying decibel values of signal levels. Furthermore, the vertical lines drawn above and below these numbers mean scales, and furthermore, the circle and numbers in the upper left part of the display surface are the display pattern of the timer.

In addition, in Figure 4, the white triangles pointing downward and upward are the display patterns to show the maximum value of the VU level within a certain period of time (for example, 3 seconds), and similarly, the black triangles pointing downward and upward are the display patterns to show the peak value of the VU level up to the present time (for example, 3 seconds). This is a display pattern for indicating the maximum level value. Furthermore, the English text shown in the lower part of the display surface is a display pattern for informing the observer of the displayed content (summary).

Various display patterns as shown in the fourth diagram are as follows:
The various display patterns mentioned above are stored in the read-only memory ROM and prepared in advance.
From the ROM, the pattern generator table PGT and sprite generator table of the video RAM VRAM are processed through the central controller CPU and video display processor VDP.
The data is transferred to the SGT, stored, and used for display operations on the display screen, as will be described in detail later.

The audio signals of each channel supplied to input terminals 1 and 2 are sent to the respective band wavers.
When supplied to the double-wave rectifiers FRl and FRr via BPFl and BPFr, the double-wave rectified output of the left channel audio signal is multiplexed from the double-wave rectifier FRl.
MPX and similarly from the double wave rectifier FRr.
The double-wave rectified output of the channel audio signal is supplied to the multiplexer MPX.

In the configuration example shown in Figure 1, the multiplexer
In addition to the outputs from the double-wave rectifiers FRl and FRr, the MPX is configured to be supplied with the output from the timer TER, and the multiplexer MPX performs switching operations based on a switching control signal from the central controller CPU. , sequentially AD the three types of input signals from the above double-wave rectifiers FRl, FRr and timer TER.
Supply to converter ADC.

The timer TER can be configured as a sawtooth generator, for example, and the variable resistor VR
By adjusting , the period of the sawtooth wave can be variably set to be long or short. The sawtooth generator can be of the known type, generating pulses in a stepped manner.

The timer TER is of a type that generates an analog signal whose size gradually increases linearly on the time axis as described above, and its output is converted into a digital signal by the AD converter ADC via the multiplexer MPX. Instead of using the configuration shown in Figure 1 which converts the time information and supplies it to the central controller CPU as time information, a timer built in the central controller CPU may be used; in that case, the configuration shown in Figure 1 The timer is set by operating a timer input button (for example, an input button provided corresponding to a time value such as 30 minutes, 45 minutes, 120 minutes, etc.) indicated by a broken line frame TER SW.

The central control unit CPU performs operations as shown in the flowchart in Figure 5, creates data necessary for displaying various levels of audio signals and displaying timers, and displays the data on the video display.
The signal is supplied to the processor VDP and the video RAM VRAM, and functions to produce a display as shown in FIG. 4 on the display screen.

As shown in the flowchart in Figure 5, when the power switch (not shown) on the main body of the device is closed, the display device starts (step (1)) and initialization (system initialization) is performed. (Step (2)), AD converter ADC, main memory
RAM, video RAM VRAM, etc. are cleared, and the video display processor
The registers in the VDP are set, the areas to be used in the video RAM VRAM are set (determining which storage area is used for which table), the operating mode, etc. are set.

In addition, predetermined types of pattern information {for example, pattern information such as letters, numbers, vertical lines, and timers shown in FIG. 4} are transferred from the read-only memory ROM to the pattern generator table PGT to the video display processor VDP. Transfer sprites from read-only memory ROM through
A predetermined type of pattern information {for example, pattern information such as white or black triangles or vertical bars as shown in Figure 4} is transferred to the generator table SGT, and furthermore, it is transferred from this read-only memory ROM to the sprite attribute table SAT. Transfer sprite name, Y coordinate, color data, etc.

Then, the central control unit CPU repeatedly executes the operations from step (3) to step (10), and further executes each step from step (11) to step (16) at predetermined intervals using a built-in counter. Multiplexers MPX and AD
It controls the operation of the converter ADC and stores various input data in the main memory RAM.

First, the interrupt operation consisting of steps (11) to (16) will be explained. Interruptions are performed at regular intervals by a counter built into the central control unit CPU, and are used to control switching of the multiplexer MPX, start conversion operations for the AD converter ADC, and store data. That is, in step (11), the sample value of the Lch signal is AD converted, and in step (12), it is stored in the main memory RAM. Further, in step (13), the sample value of the Rch signal is AD converted, and in step (14), it is stored in the main memory RAM. Further, in step (15), the sample value of the timer value is AD converted, and in step (16), it is stored in the main memory RAM, and the interrupt operation is completed. The central control unit CPU returns to the previous control operation at the time the interrupt was made.

Now, in step (3), the VU level is calculated, and this requires data on the level of the audio signal in a predetermined time width T (for example, 300 msec). The reason is that the VU level of the audio signal is 300msec.
This is because it can be obtained by rising with a time constant of 300 msec and falling with a time constant of 300 msec.

If the time length of the audio signal used to calculate the VU level is T, and there are N signal level sample values during that time length T, then the VU
The level calculation begins by calculating the arithmetic mean of N sample values existing during the time length T. For example, T = 300msec, sampling period = 10m
sec, the number of samples N=30, so in this case, the arithmetic mean of 30 sample values is calculated.

The calculation performed using the N sample values existing during the time length T is performed on the Lch and Rch audio signals respectively stored in the main memory RAM in step (12) and step (14). , are performed sequentially and individually, but if the sample value data for each channel is stored in the main memory RAM as shown in Figure 6 for each channel, the calculation becomes easier and simpler. is valid above.

In this FIG _. 6, M ₁ , M _{2 , .}
Sample value data different from each other is stored in each of a total of n sections indicated by #1, #2, . . . , #n in the figure. Note that FIG. 6 shows only the storage area of one channel, and two sets of the ones shown in the figure may be prepared to store the audio signals of L and R2 channels.

In the explanation of each operation below, each channel of L and R
Since there is no difference in principle between the audio signals, only one channel will be explained. Also,
To simplify the explanation, we will first explain the VU level calculation in detail, assuming that the sample value data of the audio signal is stored in the main memory RAM one after another after the main memory RAM has been cleared. Explain.

AD the sample value of the audio signal at time t ₁
Let the converted sample value data be S ₁ , and similarly, the time
If the sample value data obtained at t ₂ , t ₃ , ..., t _o are respectively expressed as S ₂ , S ₃ , ..., _So , then these sample value data S ₁ to _{S o} are stored in the main memory RAM. Each section of the n storage areas M ₁ to _{M o} is stored in the following manner.

That is, the sample value data S ₁ is stored in section #1 in the storage area M ₁ , and the sample value data S ₂ is stored in the storage area M 1.
The sample value data _S3 is stored in section #2 in M1 and section # ₁ in storage area _M2 .
Sequential sample value data is stored in the main memory RAM in a storage manner such that it is stored in partition #3 in _M1 , partition #2 in storage area _{M2 ,} and partition #1 in storage area M3. The storage state shown in FIG. 6 is reached.

When the main memory RAM is cleared, in a state where N sample value data of the audio signal is sequentially supplied to the main memory RAM, all sections # ₁ to #n of the storage area M1 are
When sample value data S ₁ to S _o are stored in , and then the (N+1)th sample value data of the audio signal is sent to the main memory RAM, the storage area M ₂ is divided into all sections #1 to #n. Sample value data S ₁ to S _o are stored in . In the same manner, the sample value data is sent to the main memory RAM one after another, so that the sample value data is sequentially stored in all the sections #1 to #n in each of the storage areas M ₃ , M ₄ , ..., _Mo. It will be stored.

In this way, when the storage area M ₁ has finished storing sample value data in all sections #1 to #n, all the sample value data stored in the storage area M ₁ are retrieved. Then, following the above state, the next sample value data is sent to the main memory RAM and stored in the storage area _M2.
When the sample value data has been stored in all the sections #1 to #n, all the sample value data stored in the storage area _M2 is retrieved and the arithmetic mean value thereof is obtained, and the same goes on. If the arithmetic mean value of each sample value data is obtained in this manner, the arithmetic mean value of the signal level over a fixed time length T can be successively obtained for each sampling period.

Note that all sections #1 to 1 of one storage area
After the sample value data has been stored in #n, when sample value data is sent one after another to the main memory RAM, those sample value data are stored in sections #1, #2, and #n in the storage area. By sequentially storing to..., each of the above storage areas M ₁ to _{M o}
It is clear that can be used cyclically for the successive operations, and after the sample value data has been stored in all sections of the entire storage area M ₁ to M _o ,
The storage data in each of the storage areas M ₁ to Mn is
It changes every sampling period Ts (Ts=T/n), and N sample value data in each time width T are stored in all the storage areas M ₁ to _{M o} .

Now, the main memory RAM when cleared
Then, the sample value data output one after another from the AD converter ADC is sequentially stored in the above-mentioned memory areas _M1 to M _o , and the sample value data _S1 is stored in all sections # ₁ to #n of the memory area M1. ~When S _o is memorized, the central controller
The CPU extracts these sample value data S ₁ -Sn and performs an operation to obtain the arithmetic mean thereof, and then compares the result of the operation with the result of the previous VU level operation stored in the main memory RAM.

Here, _the arithmetic mean value ₍ S ₁
When +S ₂ +...+)/n is S _b1 and the previous VU level calculation result is Svuo, the comparison result between S _b1 and Svuo will generally be in one of the following three cases.

Svuo＜S _b1 …(1) Svuo＝S _b1 …(2) Svuo＞S _b1 …(3) If the comparison result is (1) or (2), use the value of S _b1 as the new VU level value. Rewrites the VU level stored in main memory RAM as Svu ₁ . Also, if the comparison result is (3), the previous VU level Svuo
After obtaining KSvuo by multiplying it by a coefficient K determined corresponding to the falling time constant (for example, 300 msec) of the VU meter, this KSvuo and S _b1 are compared.

KSvuo＜S _b1 ……(4) KSvuo＝S _b1 ……(5) KSvuo＞S _b1 ……(6) As a result of the comparison, three cases shown in (4) to (6) occur, but the comparison If the result is (4) or (5), set the value of S _b1 to the new (current) VU level value.
Stored in main memory RAM as Svu ₁
Rewrite VU level. Furthermore, if the comparison result is (6), the VU level stored in the main memory RAM is rewritten using the value of KSvuo as a new VU level value.

In addition, in the example, the operation performed on the sample value data S ₁ to _{S o} stored in the storage area M ₁ is the first operation {the first operation performed after clearing the main memory RAM}. Needless to say, in the case of , the arithmetic mean value S _b1 is stored in the main memory RAM as the VU level Svu ₁ .

Next, after one sampling period Ts has elapsed, the storage area
When _M2 has finished storing sample value data in all sections #1 to #n, the central controller CPU
Next, we will calculate the arithmetic mean value S _b2 of the sample value data S ₂ to _{S o+1} stored in the storage area M ₂ , and compare this S _b2 with the previously calculated VU level Svu ₁ . Calculate the new VU level. In the same way, new VU levels are calculated one after another every time one sampling period passes, and the new VU levels calculated in this way are stored in a predetermined storage area of the main memory RAM. It is rewritten and stored.

The VU level calculation explained in detail above is the fifth
In step (3) in the flowchart shown, Lch
The VU levels of the Lch and Rch signals are respectively stored in predetermined storage areas in the main memory RAM.

Next, the calculation of the peak level in step (4) of the flowchart of FIG. 5 will be explained in detail. The peak level calculation is performed by taking out the two newest sample value data and the previous peak level value from among the sample value data used in the VU level calculation described above. That is, taking the sample value data S ₁ to _{S o} as an example, the peak level is determined by first comparing the two sample value data S _o-1 and S _o , and then performing a predetermined calculation according to the comparison result. The comparison result is determined by the following three cases.

S _o-1 ＞S _o ……(7) S _o-1 ＝S _o ……(8) S _o-1 ＜S _o ……(9) First, the comparison result is (8) (sample data S _{o -1} = S _o )
If the current peak level value is 1dB below S _o
A temporary peak level value S _op is determined as a low value, and then this S _op is compared with the previous peak level value S _pl stored in the main memory RAM.

S _pl ＜S _op ……(10) S _pl ＝S _op ……(11) S _pl ＞S _op ……(12) When the former is in the relationship (10) and (11), as above, The determined temporary peak level value S _op is determined as the current peak level value S _op1 and is rewritten and stored.

In addition, when the two have the relationship shown in (12), the previous peak level value S _pl is multiplied by a coefficient _{K p} determined in correspondence with the falling time constant (for example, 1.5 sec) of the VU meter. After calculating S _pl , this K _p ·S _pl is compared with the above provisional peak level value S _op .

K _p・S _pl ＜S _op ……(13) K _p・S _pl ＝S _op ……(14) K _p・S _pl ＞S _op ……(15) In this way, as a result of the comparison, the above three However, if the comparison result is (13) or (14),
S _op is set as a new peak level value S _op1 , and this is rewritten and stored in the main memory RAM as the current peak level value.

Next, in the case where the two sample value data S _o-1 and S _o are not equal ((7), (9)), and one of the sample value data of S _o-1 and S _o is 0. When it is close to the peak level indicated by the larger sample value data,
Change the level value 15dB lower to the current temporary peak level S _op
and then this S _op and main memory RAM
and the previous peak level value S _pl stored in Determine the new (current) peak level value S _op1 in the same way as described with reference and store it in the main memory RAM
Rewrite and store.

In addition, the two sample value data S _o-1 and S _o are not equal, and the two described cases, namely, the case where the two sample value data S _o-1 and S _o are equal, and the case where one sample value data is close to 0, and the difference between the two sample values corresponds to a predetermined size level, for example, to the larger peak level. -10dB, -
A predetermined level value such as 5 dB, -3 dB, etc. is determined as a temporary peak level value S _op , and this S _op is compared with the previous peak level value S _pl . Based on the comparison result, (10) ~ ( A new peak level value S _op1 is determined according to the peak level determination method as described with reference to the relationship 15).
is determined and rewritten and stored in the main memory RAM as the current peak level value.

The peak level calculation performed in the flowchart of FIG. 5 is also performed sequentially for each storage area M ₁ to _{M o} , and is performed individually and successively for Lch and Rch, etc.
This is similar to the case of level calculation.

Next, the peak level hold calculation performed in step (5) of the flowchart in FIG.
The process is carried out according to the flowchart shown in the figure.
That is, at step (5A) the main memory
Read and compare both the previous peak level hold value stored in RAM and the current peak level value determined in step (4) in Figure 5 and stored in main memory RAM. If the peak level is large (YES), step (5B)
Set the timer for peak value hold in step (5E), and store the current peak level in the main memory RAM as the new peak level hold value.
Store it in and finish. Also, step (5A)
If the comparison result is NO, that is, the previous peak level hold value is greater than the current peak level, the timer for peak value hold is counted down at step (5C), and the peak value is set at step (5D). Check whether the time set in the hold timer (for example, 3 seconds) has expired,
If NO, the process ends. If YES, the process proceeds to step (5E), changes the current peak hold value, stores the new peak level hold value in the main memory RAM, and ends the process.

Furthermore, in step (6) of Fig. 5, the highest VU level and peak level after the power is turned on and the display device starts operating are determined, and the values are stored in the main memory RAM respectively.
Store in. Next, in step (7), the time value after the power is turned on and the display device starts operating is determined by the scheduled operating time of the device body (for example, if the device body is a tape recorder, it is determined by the magnetic tape being used). time value} is calculated from the output of the timer TER, and the result is stored in the main memory RAM.

Next, in step (8), steps (3), (4), (5),
The VU level value, peak level value, peak level hold value, and maximum
It is determined to which position on the display surface, which is graduated in decibel values, the display of the VU level value, peak level value, etc. corresponds to. Also, step
Determine which position on the display surface the time rate obtained in (7) occupies, and in step (9),
The pattern name table PNT creates data to be written in the sprite attribute table SAT in correspondence with the data values determined in step (8) above. Then, in step (10), this data is converted into a video file.
Transfer to video RAM VRAM via display processor VDP.

The video display processor VDP creates a composite video signal from the data written to the video RAM VRAM as described above, and supplies this to the display CRT and RF converter RFC. This allows the display surface of the display CRT,
Various signal levels, time ratios (elapsed time relative to the set time shown in Figure 4), etc. are displayed in predetermined patterns on the display screen of the TV receiver TVS, which is used as a monitor to receive the output signal of the RF converter RFC. Ru.

The manner in which the various signal levels displayed on the display screen in this way are displayed at a time rate Tm (timer) will be described below.

First, even if the power is turned on and the display device is ready for operation, if no signals are supplied to input terminals 1 and 2, the display screen of the display CRT will be
The image will look like the one shown in the figure. Here, when signals of L and R channels are supplied to input terminals 1 and 2, respectively,
For Lch and Rch, the instantaneous signal level is shown on the left side of the letters L and R displayed on the display screen as a pattern with multiple vertical bars arranged between -∞ and the signal peak level. The level is displayed on the assumption that the length of the vertical bars expands and contracts as the peak level of the signal changes.

This type of display is achieved by writing the vertical bar pattern in the pattern generator table PGT, determining the area in which the vertical bar pattern will be arranged based on signal peak level data, and then setting the area corresponding to that area. This can be easily done by writing the pattern name in the pattern name table PNT.
In that case, for example, it is easy to display the vertical bar to the left of the 0 dB position in green or light blue, and the bar to the right of the 0 dB position to be displayed in orange or light red. It's even more convenient.

As mentioned above, the peak position value of each L and R channel signal changes instantaneously.
This is useful when processing audio signals, and this can be done by displaying the hold value of the peak level in a specific pattern, such as a vertical bar, as shown in Figure 4. The vertical bar pattern indicated by PH indicates the peak level hold value.

As described above, when the peak level of a new signal exceeds this vertical bar pattern PH, the peak level hold value pattern PH is rewritten by the peak level value that exceeds it. If a peak level value exceeding 100% does not appear for a certain period of time (for example, 3 seconds), it disappears after being displayed for a certain period of time.

Such peak level hold values can also be displayed using the pattern generator table PGT and pattern name table PNT, or the sprite generator table SGT.
It can also be displayed using the sprite attribute table SAT.

On the other hand, the VU level is displayed, for example, as a thin white vertical line on the display screen, as indicated by the symbol VU in FIG.
This VU level display consists of the sprite generator table SGT and the sprite attribute table
This can be easily done using the SAT.

Furthermore, patterns VUm and Pm shown by white triangles and black triangles in FIG. 4, respectively, are patterns showing the maximum values of the VU level and the peak level, respectively.
These patterns VUm, Pm, etc. can also be easily displayed using the sprite generator table SGT and the sprite attribute table SAT.

Furthermore, the time rate pattern indicated by the symbol Tm in Fig. 4 is based on the pattern generator table.
It can also be displayed using PGT and pattern name table PNT.

〔effect〕

As described above, according to the display device of the present invention, a video signal generator (video display processor) selects and outputs a predetermined pattern of images from a video RAM storing various image patterns.
etc., the various measurement and calculation data such as VU level, peak level, etc. can be used to calculate the time rate, etc.
They can be displayed simultaneously on the same display surface, so
It is possible to properly adjust and monitor the signal level during audio signal transmission, recording and playback,
In addition, since it is easy to enlarge the display surface (using a large display device), it is easy to allow many people to view the screen at the same time, and for example, it is possible to display a video image and monitor an audio signal at the same time. We can respond well to requests such as
Furthermore, it has an excellent feature that it can be used in various fields and modes of use, such as the ability to easily display the signal level in a stereo playback device using a home TV receiver.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the display device of the present invention, FIG. 2 is a diagram showing an example of a memory map of a video ram, FIG. 4 and 8 are diagrams showing examples of display patterns on the display surface of the device of the present invention, FIGS. 5 and 7 are flowcharts for explaining the operation, and FIG. 6 is a flowchart for explaining the operation. FIG. 3 is a schematic diagram for explaining a storage mode. 1, 2...Input terminal, BPFl, BPFr...bandwidth wave generator, MPX...multiplexer, ADC...AD
Converter, TER...Timer, CPU...Central control unit, RAM...Main memory, VDP...Video signal generator (video display processor), VRAM...Video RAM, CRT...Display device , RFC...RF converter, TVS
...TV receiver.

Claims (1)

[Claims] 1. Analog-to-digital conversion means for converting an audio signal into a digital signal, and a VU level and a VU level based on digital data within a predetermined time width obtained by the analog-to-digital conversion means. Calculate the peak level and/or its hold level, or the maximum value of the values obtained from the VU level and peak level, and use the calculation result to create predetermined pattern information corresponding to the type and magnitude of the level. a video signal generator (video display processor) that supplies a predetermined pattern of images to the central controller from a video ram storing various image contents;
and a display device that displays output data from the video signal generator, and the VU level, peak level, or hold level of the audio signal, or the maximum value of the above-mentioned VU level or peak level. A display device capable of displaying information on the display surface of the display device in real time.