JPH06100948B2 - Reset signal control circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset signal control circuit in a device incorporating a microprocessor or the like.

2. Description of the Related Art Conventionally, in various devices including a computer system and a microprocessor, a backup battery is built in, and important data is erased even if a power failure or a power line disconnection occurs during operation. Some are configured to prevent this. That is,
For example, the CPU (central processing unit) shifts from the normal operation mode to the data retention mode as the external power supply is cut off, and retains the data in the memory device without accepting external commands until the external power supply is restored. It kept the data retention mode.

By the way, in general, when this kind of device is turned on,
It was necessary to set it to the initial setting state where all unnecessary data in the CPU was erased. Therefore, when an external power source is applied
The configuration is such that a reset signal is always sent to the CPU to enter the initial setting state, that is, a power-on reset configuration.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention In such a device, when it is desired to perform an operation in the data holding mode, for example, a multifunction telephone having an automatic dial function, a data terminal, and a document creation function for creating document data to be sent out, etc. If you want to operate only the telephone function and the automatic dial function for that purpose with the external power supply not applied, or with the power switch turned off because the document creation function is unnecessary in the device, a backup It is possible if the CPU is operated using a battery.

However, in such a configuration, since the power-on / reset configuration is performed as described above, while searching for the data of the target dial number and while transmitting the dial pulse to the telephone line according to the data. When external power is applied due to restoration of power failure, etc., the CPU may be set and the operation may be interrupted halfway, which is very inconvenient.

The present invention has been made in view of the above problems, and prevents the CUP from being reset even when an external power supply is applied during the operation when the operation is in the data retention mode. The present invention provides a reset signal control circuit that can be used.

Means for Solving the Problems In order to solve the above problems, the present invention provides a storage means for storing power supply drop information by a data holding mode (hereinafter referred to as standby mode) transition command signal that occurs when an external power supply is cut off. , The input of the reset signal to the microprocessor is blocked while the power-down information is stored in the storage means, and the reset signal to the microprocessor is passed while the power-down information is not stored in the storage means. A gate means is provided for erasing the power-down information of the storage means according to the output signal of the gate means.

Operation With this configuration, when the power is turned off, the power-down information is stored in the storage means, the gate means is in the passing state, and the MPU can be reset to operate the telephone etc. even in the standby mode. , When the operation is started, the reset signal is once applied to the MPU, at that time the power supply drop information of the storage means is erased, the gate means is turned off, and the reset signal is applied during the operation. You can choose not to accept it.

Embodiments Embodiments in which the reset signal control circuit according to the present invention is used in a multifunction telephone device will be described below with reference to the drawings. FIG. 1 shows a reset signal control circuit and peripheral devices in this embodiment.

Reference numeral 1 is a NAND gate inserted in the reset signal line.

2 is a microprocessor (hereinafter referred to as MPU). M
The PU2 is provided with a reset signal (hereinafter referred to as RESET) input terminal, and the reset signal line from the NAND gate 1 is connected thereto. The MPU2 also has input terminals such as the standby mode transition command signal (STBY) input terminal and non-maskable interrupt signal (NMI) input terminal. The MPU2 also has an internal I / O port.
One of the pins of the / O port is the output pin for the signal that directs the transition to the standby mode (hereinafter referred to as STBYOUT).

Reference numeral 3 is a flip-flop circuit for storing the standby mode. The set input terminal S is connected to the STBYOUT output terminal of MPU2, and the reset input terminal R is connected to the reset signal line leading to the RESET input terminal of MPU2. The output terminal Q of the flip-flop circuit 3 is connected to the control circuit 1, and its inverting output terminal is connected to the STBY input terminal of MPU2.

A battery 4 holds data and operates during a power failure, and supplies power to each circuit. Reference numeral 5 denotes a voltage drop detection circuit (hereinafter referred to as a detection circuit) that detects a voltage drop of the external power supply, and when the voltage drop is detected, an interrupt signal is transmitted to the NMI terminal of MPU2. An OR circuit 6 receives a power-on reset signal from the power supply circuit and an operation request signal input by the user in the standby state. And
The output signal line is connected to the input side of the NAND gate 1.
However, the input side of the OR circuit 6 is illogical.

Next, based on FIG. 2, a multi-function telephone device having a reset signal control circuit according to this embodiment will be described. In addition to the function as a telephone device, the multifunctional telephone device has a function as a data terminal device, a document creating device for creating a document to be sent to the other party, and the like.

Reference numeral 7 is a reset signal control circuit including the NAND gate 1, the flip-flop circuit 3, and the OR circuit 6 as described above. Reference numeral 8 is provided with the above-mentioned detection circuit 5, and power supply lines PW1 and PW
2 is a power supply circuit for supplying a power supply voltage to each part of the device via 2. The power supply line PW1 supplies a power supply voltage to the MPU 2, reset control circuit 7, telephone circuit 10, RAM 17, and keyboard 25. The backup battery 4 is connected to the power line PW1. On the other hand, power line PW
2 supplies the power supply voltage to other devices. Reference numeral 9 denotes a power switch of this apparatus, which turns on / off the external power supplied to the power circuit 8.

Reference numeral 10 is a telephone circuit to which a telephone line is connected and which performs operations such as sending a dial signal, amplifying a voice signal, and generating a ringing tone according to control of the MPU 2. Reference numeral 11 is a MODEM circuit which operates in the data communication mode and modulates the carrier signal with the data sent from the MPU2. The input / output signal line of the MODEM circuit 11 is connected to the telephone circuit 10.

Reference numeral 12 is an I / O port that is provided in the MPU 2 as described above and is used exclusively for controlling the telephone circuit. Also, 13 is MPU2
CPU (central processing unit) provided in, 14 is also RAM (random access memory) also provided in MPU2, 15 is a ROM (read only memory) also provided in MPU2.

Reference numerals 16 and 17 are a ROM and a RAM for storing a program relating to each function, document data created in the document creation mode, document data sent via a telephone line, and the like.

Reference numeral 18 is an I / O port for outputting print data to an external printer, and 19 is an I / O port provided for inputting / outputting data to / from another device via an RS232C terminal.

Reference numeral 20 is a disk drive control circuit for controlling the floppy disk drive device 21, and for writing and reading data to and from the device. Reference numeral 22 is a CRT control circuit for displaying a document created on the CRT display device 23, a list of stored telephone numbers, and the like.

Reference numeral 24 is a keyboard used for inputting operation data to this apparatus or inputting document data when creating a document. Reference numeral 25 is a keyboard provided with a numeric keypad exclusively for inputting numerical data and function keys for operation commands. 26 is a telephone line
It is a handset connected to 10.

The operation of the multifunction telephone device having the reset signal control circuit as described above will be described below with reference to the timing chart of FIG.

Now, it is assumed that the power switch 9 is turned on, external power is supplied, and normal power supply voltage is applied to MPU2 and other devices. Then, it is assumed that the present apparatus is performing a normal operation in an operation mode such as document creation.

If a power failure occurs at this time, the detection circuit 5 detects that the power supply voltage has dropped, and as shown in FIG. 1, sets the signal a input to the NMI terminal of the MPU2 to 0 and instructs the MPU2 to perform interrupt processing. . The MPU2 sets the STBYOUT output b to 1 in order to enter the standby mode after performing the necessary processing by this interrupt signal. The flip-flop circuit 3 is set by the rise of the output b, and the output of the inverting output terminal becomes 0, whereby the MPU 2 enters the standby mode. In standby mode, the MPU2 waits for power restoration while backing up document data and so on. Also, along with that, output terminal Q
Output d becomes 1, the NAND gate 1 is closed, and the MPU 2 becomes resettable. In this state, the MPU2 cannot output a control signal to the outside and holds the memory internally.

Here, when the user feels the necessity of talking with the other party of data communication and picks up the handset 26, the operation request signal e from the telephone circuit 10 becomes 0 and the output f of the OR circuit 1 becomes 1.
Becomes Since the NAND gate 1 is closed, its output h is the inversion of f, that is, 0.

When h becomes 0, MPU2 is reset. Also,
At the same time, the flip-flop circuit 3 is reset, the output c becomes 1 and the standby mode of the MPU 2 is released. Then, the MPU2 starts operation and performs each operation in the telephone mode according to the program.

Also, when the flip-flop circuit 3 is reset, Q
Output d becomes 0, and the NAND gate 1 is released, that is, in the reset prohibited state.

Even during such a power failure operation, for example, even when the telephone function is working as in this example, when the external power supply is restored, the power-on / reset function normally works, the signal g becomes 0, and the output of the OR circuit 6 is output. The signal f becomes 1. However, the NAND gate 1 is in the reset prohibition state due to the output of the flip-flop circuit 3, the reset signal is not output to the MPU 2, and the signal h remains at 1. Therefore, the operation during execution of MPU2 is not canceled and the operation is continued. However, the output a of the detection circuit 5 becomes 1 to indicate the return of the external power supply, and the normal operation is continued without performing the interrupt operation.

If the call ends before the external power is restored, the MPU2 sets the STBYOUT signal b to 1 again and sets the flip-flop circuit 3 according to information such as the handle set 26 being placed. Becomes

EFFECTS OF THE INVENTION As described above, according to the present invention, storage means for storing power down information by a data holding mode transition command signal generated when an external power supply is cut off, and a state in which the power down information is stored in the storage means. Gate means is provided for blocking the input of the reset signal to the microprocessor, and for passing the reset signal to the microprocessor in a state in which the power-down information is not stored in the storage means, and the storage means is provided in accordance with the output signal of the gate means. By configuring to delete the power supply drop information of the means, when the external power supply is cut off, the gate means is in a passing state, and the MPU can be reset to operate even when the external power supply is cut off. In addition to this, once the reset signal is applied to the MPU in this state, the gate means becomes the cutoff state. It is possible to prevent the subsequent reset signal from being accepted.Therefore, when an operation such as a power outage in which the external power source is not applied is being performed, the external power Even if is applied, since the reset signal is printed when the operation is performed, it is possible to prevent the CPU from being reset again during the operation.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a reset signal control circuit according to an embodiment of the present invention, FIG. 2 is a block diagram of a multifunctional telephone device including the reset signal control circuit, and FIG. 3 is a diagram of the reset signal control circuit. It is a timing diagram which shows operation. 1 ... NAND gate 2 ... Microprocessor (shown as MPU in the figure) 3 ... Flip-flop circuit 4 ... Battery 5 ... Voltage drop detection circuit 6 ... OR circuit

Claims (1)

[Claims] 1. A storage unit that operates with a backup battery and stores power supply drop information by a data holding mode transition command signal generated when an external power supply is cut off.
According to the information stored in the storage means, the input of the reset signal to the microprocessor is blocked while the power down information is stored in the storage means, and the power down information is not stored in the storage means. 3. A reset signal control circuit, characterized in that gate means for passing a reset signal to the microprocessor is provided, and the power supply drop information of the storage means is erased according to the output signal of the gate means.