JPH06100974B2 - Single-chip microcomputer - Google Patents

Description

The present invention relates to a single-chip microcomputer, and more particularly to a single-chip microcomputer incorporating an analog / digital converter (hereinafter abbreviated as ADC).

[Conventional technology]

In recent years, single-chip microcomputers with built-in ADC have become popular. This single-chip microcomputer uses a PROM to test the built-in ADC.
, Etc., an instruction was input from outside the single-chip microcomputer, the CPU was made to execute the instruction, the digital value of the ADC was compared with the expected value, or the digital value was derived to the output terminal.

[Problems to be Solved by the Invention]

The conventional single-chip microcomputer described above has a drawback that the test method is complicated because the CPU in the single-chip microcomputer is operated to test and characterize the built-in ADC.

[Means for Solving the Problems] A single-chip microcomputer according to the present invention uses a test input terminal and a signal from the test input terminal.
It has means for outputting the digital value of the ADC to the internal data bus and outputting the synchronizing signal of the ADC to the outside of the single chip microcomputer, and means for deriving the internal data bus to the output terminal.

[Action]

By inputting the test signal from the test input terminal, the digital value of the ADC can be derived to the output terminal without operating the CPU.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a single chip microcomputer of the present invention.

Single-chip microcomputer 1, CPU2, AD
C3, peripheral device 4, output port 5, AD conversion result holding register (ADCR) 6, data bus 7, output buffers B101 to B10
n, B201 to B20N, B301 to B30N (n is the resolution of ADC3, N is the bus width of data bus 7), AND gates 8,11 and OR gates
It has 9,10,12 and input gates G101 to G10N. The output of the AND gate 8 is "1" when the test signal TEST is "0" and the output enable signal OUT1 from the CPU2 to the data bus 7 is "1".
Then, the data of the CPU 2 is output to the data bus 7. The output of the OR gate 9 becomes "1" when the test signal TEST is "1" or the AD conversion result read signal ADRD is "1".
Is output to the data bus 7. The OR gate 10 has a test signal TEST of “1” or an AD conversion start request signal ADSTART.
When is “1”, the output becomes “1” and ADC3 starts conversion. As for the output of the AND gate 11, the test signal TEST is "0".
And an output enable signal from the peripheral device 4 to the data bus 7.
When OUT2 is "1", it becomes "1", and the data of the peripheral device 4 is output to the data bus 7. OR gate 12 is the test signal
When TEST is "1" or the input buffer ON signal RORTON of the output port 5 is "1", it becomes "1", and the data on the data bus 7 is output from the output port 5.

When the test signal TEST becomes "1", the values of AND gates 8 and 11 become "0", the values of OR gates 9, 10 and 12 become "1", and the CPU
2, the peripheral device 4 is prohibited from outputting to the data bus 7, and AD
C3 starts the conversion, and when the conversion ends, outputs a conversion end synchronization signal and writes the conversion result to ADCR6. The ADCR6 outputs the written conversion result to the data bus 7, and the output port 5
Outputs the conversion result on the data bus 7 to the output terminal.

FIG. 2 is a block diagram showing a second embodiment of the single-chip microcomputer of the present invention.

Single-chip microcomputer 1A of this embodiment
Is a D-type latch 201, 202, rising edge detection circuit 20
3, the falling detection circuit 204, the latch circuits 207, 208, the output ports 209, 210, the OR gates 211, 213, 215, 217, and the AND gates 205, 206, 212, 214, 216, 218, and the others are the same as the first embodiment.

In the first embodiment, the relationship between the resolution n of the ADC 3 and the bus width N of the data bus 7 is n ≦ N, but in the second embodiment, n
≦ 2 × N.

The OR gate 211 outputs the lower bit read signal ADL of the conversion result.
When RD is "1" or the test signal TEST is "1" and the conversion end synchronization signal is "0", it becomes "1" and the lower N bits of ADCR6 are output to the data bus 7. The OR gate 213 becomes "1" when the conversion result high-order bit read signal ADHRD is "1" or the test signal TEST is "1" and the conversion end synchronization signal is "1", and N + 1 to n bits of ADCR6 are converted. It is output to the data bus 7. OR gate 215 has output port 2
Data write signal P1WR to 09 data latch 207 is “1”
Alternatively, when the test signal TEST is “1” and the AND gate 205 is “1”, it becomes “1”, the data on the data bus 7 is written to the data latch 207 of the output port 209, and the output port 20
It is output from 9. The OR gate 217 is configured such that the data write signal P2WR to the data latch 208 of the output port 210 is “1” or the test signal TEST is “1”, and the AND gate 206 is “1”.
At this time, it becomes "1", and the data on the data bus 7 is written in the data latch 208 of the output port 210 and output from the output port 210.

FIG. 3 is a time chart showing the operation of the single-chip microcomputer shown in FIG. 2 when the test signal TEST is "1". The operations of the CPU 2, the ADC 3, and the peripheral device 4 are the same as those in the first embodiment, and will be omitted. The synchronizing signal output from ADC3 for two clocks from time t ₁ to t ₃ is the D-type latch 201, 20.
A delay of 1 clock is applied by ₂ and becomes a signal from time t ₂ to t ₄ . The rising edge detection circuit 203 is a D type latch 2
It detects that the output of 02 rises at time t ₂ and outputs “1”, the AND gate 205 becomes “1” while the clock signal φ is “1”, and the output of the OR gate 215 becomes “1”, The data on the data bus 7 is latched in the data latch 207 of the output port 209 at time t ₂ . In this case, the OR gate 213 is on the data bus 7 because it is made from time t ₁ to the period "1" of t ₃ are riding high-order data of ADCR6. Therefore, the upper data of ADCR6 is output from the output port 209. Next, at time t ₄ , when the output of the D-type latch 202 falls, the output of the falling edge detection circuit 204 becomes “1”, and the AND gate 206 sets it to “1” while the clock signal φ is “1”. OR gate 217 becomes “1” and output port 210
The data on the data bus 7 is stored in the data latch 208 of the time t ₄
Is latched by. At this time, the OR gate 211 because it has become a time t ₃ after the "1", on the data bus 7 is riding backward data of ADCR6. Therefore, the lower data of ADCR6 is output from the output port 210.

With the above operation, the upper and lower data of ADCR6 will be output.

〔The invention's effect〕

As described above, the present invention is a single-chip microcomputer with a built-in ADC, by deriving the ADC digital value and the synchronizing signal to the output terminal without operating the CPU by the test input terminal signal, and -It has the effect of facilitating testing and evaluation of the ADC built into the microcomputer.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a single-chip microcomputer of the present invention, FIG. 2 is a block diagram showing a second embodiment of the single-chip microcomputer of the present invention, and FIG. 3 is a time chart explaining the operation of FIG. 2. 1,1A ... Single chip microcomputer, 2 ... CP
U, 3 ... ADC, 4 ... Peripheral device, 5,209, 210 ... Output port,
6 ... ADCR, 7 ... data bus, 8,11,205,206,212,214,21
6,218 ... AND gate, 9,10,12,211,213,215,217 ... OR gate, 201,202 ... D type latch, 203 ... Rising edge detection circuit, 204 ... Falling edge detection circuit, 207, 2
08 ... Data latch, B101 to B10n, B201 to B20N, B301 to B30N
… Output buffers, G101 to G10N… Input gates.

Claims (1)

[Claims] 1. A single-chip microcomputer incorporating an analog-digital converter, wherein a digital value of the analog-digital converter is transferred to an internal data bus by a test input terminal and a test signal from the test input terminal. A single-chip microcomputer having means for outputting and outputting the synchronizing signal of the analog-digital converter to the outside of the single-chip microcomputer, and means for deriving the internal data bus to an output terminal.