JPH06101228B2 - Dynamic RAM - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a dynamic RAM (random access memory), which is effective when used for a dynamic RAM including a Mayamplifier activated by a pulse signal, for example. It is about technology.

[Background technology]

The column system selection circuit is composed of a static type circuit,
The column address signal is changed while the word line is in the selected state to switch the selection of the data line one after another so that the continuous read / write operation of the memory cells coupled to the word line is performed. Dynamic RAM in static column mode has been developed. In such a continuous access mode by the static column mode, since the address of the column system is switched by the address signal supplied from the external terminal, the address can be switched at any timing, but the external terminal can be switched. The operation speed is relatively slowed due to the skew of the address signal supplied from the device (difference in change timing of the address signal). The reason for this is that the column selection operation is performed with the address signal that changes most slowly among the address signals composed of multiple bits.

On the other hand, in the page mode in which the column address signal is fetched in synchronization with the column address strobe signal ▲ ▼, and the selection of the data line is switched one after another as described above, it is not necessary to consider the skew of the address signal, and therefore the higher speed Continuous access operation can be realized.

The inventor of the present application has studied to selectively realize both the continuous access modes by a common circuit in order to rationalize the design of a dynamic RAM and improve mass production. If a static type circuit is used as the main amplifier that amplifies the signal of the selected data line in order to be able to deal with either of the above two continuous access modes according to the specifications, the current consumption is relatively low. There is a problem that it becomes large.

For the dynamic RAM, see, for example, Nikkei McGraw-Hill Co., July 18, 1983, "Nikkei Electronics", pages 169 to 193.

[Object of the Invention]

An object of the present invention is to provide a dynamic RAM equipped with a main amplifier that realizes low power consumption.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, the column address strobe signal is received, and the one-shot pulse signal almost synchronized with the column selection operation causes the main amplifier to be operated for a certain period. Further, the main amplifier is operated only in the read operation mode.

〔Example〕

FIG. 1 shows a dynamic RAM to which the present invention is applied.
A block diagram of is shown. The circuit elements constituting each circuit block in the same figure are formed on a semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique, although not particularly limited thereto. The main blocks in this figure are drawn according to the actual geometrical arrangement.

In this embodiment, although not particularly limited, the memory arrays are arranged in two groups, left and right and top and bottom, like M0 to M3. In each of the memory arrays M0 to M3, the column system signal line (data line) is composed of a pair of complementary data lines arranged in parallel. Bit line or digit line system). Further, a pair of common complementary data lines running in the vertical direction in the figure are arranged on the left and right centering on the column decoders YDCR0 and YDCR1.
Although not particularly limited, each memory array M0 to M3 has a storage capacity of, for example, about 256 Kbits,
The total storage capacity is about 1 Mbit.

The column switch circuits CW0 to CW3 are connected to the column decoder YDCR0.
And a decode output signal (selection signal) formed by YDCR1 and YDCR1 to receive complementary output lines and common data lines of the memory arrays M0 to M3 corresponding to the respective addresses. The column decoder YDCR is provided with a complementary address signal a y0 to a column address buffer YADB to be described later.
It decodes ayn and forms a selection signal to be supplied to the column switch circuits CW0 to CW3 in synchronization with the data line selection timing signal. Here, complementary address signals a y0 to a yn
Represents the internal address signals ay0 to ayn in phase with the address signals AY0 to AYn supplied from the external terminals and the internal address signals y0 to yn whose phases are inverted. The same applies to the row address signals described later.

In each of the memory arrays M0 to M3, row-related address selection lines (word lines, dummy word lines) are arranged so as to extend in the vertical direction in FIG.

The row decoders XDCR0 and XDCR1 have complementary address signals a x0 to a xm supplied from a row address buffer XADB, which will be described later.
Is decoded to form a selection signal for one word line in the memory arrays M0, M2 and M1, M3 and the dummy word line corresponding thereto. Word line drive circuit WDRV0, WRV2 and WDRV1, WD
The RV3 receives the selection signal and the word line selection timing signal and puts the one word line and the dummy word line in the corresponding memory arrays M0, M2 and M1, M3 into the selected state.

The sense amplifiers SA0 to SA3 start the amplification operation by the sense amplifier timing signal during the write / read operation, and particularly limit the minute read voltage from the memory cell coupled to one data line by the word line selection operation. Although not performed, the complementary data line is amplified to the high level / low level by referring to the reference voltage from the dummy cell coupled to the other data line by the selection operation of the dummy word line.

The row address buffer XADB is an external address signal supplied in synchronization with the row address strobe signal ▲ ▼.
Captures AX0～AXm, the complementary address signal a x0~ a xm
To form. Column address buffer YADB takes in the external address signal AY0~AYn supplied in synchronism with a column address strobe signal ▲ ▼, forming the complementary address signal a y0~ a yn.

The common complementary data line is coupled to the input terminals of the main amplifiers MA0 and MA1 and the output terminal of the data input circuit DIB. The main amplifiers MA0 and MA1 start an amplifying operation according to a main amplifier timing signal, which will be described later, and amplify the signal read to the common complementary data line to output the data output circuit.
Tell DOB. The data output circuit DOB, if the read operation in which the write enable signal ▲ ▼ is set to high level,
The main amplifier is activated at a specified timing.
The output of MA0 or MA1 is amplified and sent to the external terminal D. In the write operation in which the write enable signal ▲ ▼ is set to the low level, the data input circuit DIB is activated at a predetermined timing and the data Di supplied from the external terminal is input.
n is transmitted to one of the addressed common complementary data lines.

The internal control signal generation circuit TG receives three external control signals ▲ ▼ (row address strobe signal), ▲ ▼ (column address strobe signal), and ▲ ▼ (write enable signal), but its operation mode is not particularly limited. , And various timing signals required for its operation mode are formed and sent to each circuit.

FIG. 2 shows a circuit diagram of an embodiment of the data input and output circuit. Each circuit element in the figure is a well-known CMOS.
(Complementary MOS) It is formed on a semiconductor substrate such as single crystal silicon by a manufacturing technique of an integrated circuit. In the figure, the MOSFET in which a straight line is added between the source and drain is a channel type.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single crystal P-type silicon. N-channel MOSFET
Is a gate electrode made of polysilicon formed through a thin gate insulating film on the surface of the semiconductor substrate between the source region and the drain region and between the source region and the drain region. Composed of. The P-channel MOSFET is formed in the N-type well region formed on the surface of the semiconductor substrate. As a result, the semiconductor substrate has a plurality of N channel MOs formed thereon.
Configure the common substrate gate of the SFET. The N-type well region constitutes the substrate gate of the P-channel MOSFET formed thereon. The substrate gate of the P-channel MOSFET, that is, the N-type well region, is coupled to the power supply terminal Vcc. Although not particularly limited, the built-in substrate back bias voltage generation circuit (not shown) responds to a positive power supply voltage such as + 5V applied between the power supply terminal Vcc that constitutes the external terminal of the integrated circuit and the reference potential terminal or the ground terminal. Then, a negative back bias voltage to be supplied to the semiconductor substrate is generated.
This applies a back bias voltage to the substrate gate of the N-channel MOSFET. As a result, the junction capacitance (parasitic capacitance) between the source and drain of the N-channel MOSFET and the semiconductor substrate is reduced to speed up the operation, and minority carriers generated in the substrate are absorbed. Therefore, the information retention time of the memory cell is lengthened.

Common complementary data line CD0, ▲ ▼ 0 shown as a representative
Is coupled to the input terminal of main amplifier MA0. The main amplifier MA0 is composed of the following pair of first stage differential amplifier circuit, second stage differential amplifier circuit 2nd, and output selection circuit.

One of the pair of first stage differential amplifier circuits is N
Channel differential amplification MOSFETs Q7 and Q8, and P-channel load MOSFET Q provided between the drain and the power supply voltage Vcc
5, Q6 and the differential amplification MOSFETs Q7 and Q8, and an N-channel type power switch MOSFET Q13 provided between the common source and the ground potential point of the circuit. Load MOS above
The FETs Q5 and Q6 form an active load circuit by forming a current mirror form. The other one of the first-stage differential amplifier circuit has the same N-channel differential amplifier MOSFET Q11, Q1
2 and P-channel load MOSFETs Q9, Q10, the common source of the differential amplification MOSFETs Q11, Q12 is shared with the common source of the one differential amplification MOSFETs Q7, Q8, and the operation is controlled by the power switch MOSFET Q13. Is done. The gate of the MOSFET Q13 is supplied with an operation timing signal φma of the main amplifier, which will be described later.

The gate of the N-channel MOSFET Q7 as an inverting input terminal in the one differential amplifier circuit and the N-channel MOSFET Q1 as a non-inverting input terminal in the other differential amplifier circuit.
The gate of 1 is coupled to the common complementary data line {circle around (0)}. The gate of the N-channel MOSFET Q8 as the non-inverting input terminal in the one differential amplifier circuit and the gate of the N-channel MOSFET Q12 as the inverting input terminal in the other differential amplifier circuit are the common complementary data line CD0.
Be combined with.

The pair of output signals amplified by the pair of first-stage differential amplifier circuits is not particularly limited, but is configured by a circuit similar to the first-stage differential amplifier circuit as a circuit surrounded by a dotted line in FIG. It is supplied to a pair of input terminals of the second stage differential amplifier circuit 2nd. Since each circuit element in the second stage differential amplifier circuit is the same as that in the first stage amplifier circuit, the circuit symbol and its description are omitted.

The pair of output signals of the second stage differential amplifier circuit 2nd is transmitted to the input of the common data output circuit DOB through the next output selection circuit. One output selection circuit for receiving one output signal of the differential amplifier circuit path 2nd is a P-channel MOSFET Q17.
Is supplied to the input of the CMOS inverter circuit constituted by the N-channel MOSFET Q18. This CMOS inverter circuit is put into operation by the power supply voltage Vcc and the ground potential of the circuit being supplied by the P-channel MOSFET Q16 and the N-channel MOSFET Q19. Therefore, the above MOSF
When ETQ16 and Q19 are turned off, the output of the CMOS inverter circuit is set to a high impedance state. The other output selection circuit that receives the other output signal of the differential amplifier circuit 2nd is a P-channel MOSFET Q21, N-channel MOSFET Q22 and a P-channel MOSFET Q20, N-channel MOSFET Q23 that supplies an operating voltage, which constitutes a CMOS inverter circuit similar to the above.
When the MOSFETs Q20 and Q23 are turned off, the output of the CMOS inverter circuit is brought to a high impedance state.

The other main amplifier MA1 shown in FIG. 1 is also composed of a circuit similar to the above. These two main amplifiers MA0 and MA1
Output signal is selectively transmitted to the data output circuit DOB by, for example, a 1-bit address signal an, n of a column system. That is, the NOR circuit G6 constitutes a decoder circuit. The input of the NOR gate circuit G6 is supplied with a pulse read signal ▲ ▼ and an address signal an which are generated in synchronization with the column selection operation during the read operation as described later. The NOR gate circuit G6, for example, when the address signal an is at low level and the control signal ▲ ▼ is at low level, the output thereof becomes high level in synchronization with this. The output of the NOR gate circuit G6 is inverted by the CMOS inverter circuit IV3 and supplied to the gates of the P-channel MOSFETs Q16 and Q20 of the output selection circuit. The output of the NOR gate circuit G6 is the N channel of the output selection circuit.
It is supplied to the gates of MOSFETs Q19 and Q23. by this,
The main amplifier is synchronized with the control signal ▲ ▼.
The output signal of MA0 is sent to the input terminal of the next data output circuit DOB. If the inverted address signal n is low level, the output signal of the main amplifier MA1 not shown is transmitted to the data output circuit DOB.

The data output circuit DOB is a NAND gate circuit G1, G2.
A latch circuit configured by is provided. P-channel MOSFETs Q24 and Q25 controlled by the control signal RYP are provided between the pair of input terminals and the power supply voltage Vcc.

The output signals of this latch circuit are the NAND gate circuit G3, the CMOS inverter circuit IV1 and the NAND gate circuit G4, respectively.
And N-channel output MOSFET Q26 of push-pull type and N-channel output MOSFE via CMOS inverter circuit IV2
It is transmitted to the gate of TQ27. The above NAND gate circuit G3, G
The operation timing signal DOB is supplied to the other input of 4. When this signal DOB is at high level (logic "1"), the NAND gate circuits G3 and G4 open the gates accordingly and the CMOS
The selected main amplifier MA0 (or MA1) output signal is amplified and sent to the external terminal Dout via the inverter circuits IV1 and IV2 and the output MOSFETs Q26 and Q27. If the timing signal DOB is at a low level such as the ground potential of the circuit, the output signals of the NOR gate circuits G3 and G4 are both set to the high level, and the output signals of the inverter circuits IV1 and IV2 are set to the low level. As a result, both output MOSFETs Q26 and Q27 are turned off, and their outputs are put in a high impedance state.

The external input terminal Din is connected to the input terminal of the data input circuit DIB. This data input circuit DIB is activated by a timing signal φin, which will be described later, and the external input terminal Din
To form a write signal having the same phase as the write data signal supplied to the write signal and the opposite write signal. The complementary write data signals are N-channel transmission gate MOSFETs Q1 and Q2.
Is supplied to the common complementary data line ▲ ▼ 0, CD0 via the. Common complementary data line ▲ ▼ 0, CD0 and power supply voltage V
N-channel load MOSFETs Q3 and Q4 having a relatively small conductance are provided between them and cc.

The gates of the transmission gate MOSFETs Q1 and Q2 that selectively transmit the output signal of the data input circuit DIB are supplied with the output selection signal of the decoder circuit constituted by the following NOR gate circuit G7. Input to the NOR gate circuit G7 is the same address signal an and pulse write signal ▲ ▼ as in the above output selection circuit.
Is supplied. This allows the common complementary data line ▲ ▼
When the address signal an for instructing 0 or CD0 is at low level, the control signal
The output signal of the NOR gate circuit G7 is set to the high level in synchronization with the low level of ▼. Accordingly, the transmission gate MO
SFETQ1 and Q2 are turned on, and the write signal supplied from the external input terminal Din is the common complementary data line ▲ ▼ 0, CD0
Be transmitted to. As a result, in FIG. 1, writing is performed to the memory cell in the selective state in the memory array M0 or M1 on the left side. The above data input circuit
The output of the DIB is fed through a similar transmission gate MOSFET to the first
It is selectively transmitted to another common complementary data line CD1, not shown, corresponding to the memory arrays M1 and M3 on the right side shown in the figure. In the read operation, the control signal ▲ ▼ is set to the high level, so the NOR gate circuit
The output of G7 goes low. In response to this, the transmission gate MOSFETs Q1 and Q2 are turned off. The output of the NOR gate circuit G7 is inverted by the CMOS inverter circuit IV6 and transmitted to the gates of the N-channel MOSFETs Q3 and Q4. Therefore, at times other than the above write operation, these MOSFETs Q3 and Q4 are turned on to give a substantially constant bias level to the common complementary data lines {circle around (0)}, CD0. Depending on the ON state of MOSFETs Q3 and Q4, common complementary data line ▲ ▼
Since the signal amplitudes of 0 and CD0 are substantially limited, the read signal from the memory cell can be responded at high speed.

In this embodiment, in order to reduce the current consumption of the main amplifier MA0 (MA1), its operation timing signal φ
ma is formed by the following timing generation circuit.

In this embodiment, although not particularly limited, two timing generation circuits are prepared in order to cause the operation of the main amplifier for a fixed period in the page mode or the static column mode. One of them is an address signal change detection circuit ATD which receives a column address signal ay and detects its change, and the other is a timing generation circuit PG which receives an internal column address strobe signal ▲ ▼. . For example, when realizing the static column mode, the timing signal formed by the address signal change detection circuit ATD is supplied to the pulse generation circuit RWPG as shown by the solid line in the figure. When realizing the page mode, the output timing signal of the timing generation circuit PG is supplied to the pulse generation circuit RWPG as indicated by the dotted line instead of the solid line. Although not particularly limited, such a change in connection is performed by the master slice method.

The pulse generation circuit RWPG is set to 1 during the read operation.
A pulse read signal ▲ ▼ for a shot is generated, and a pulse write signal ▲ ▼ for one shot is similarly generated during a write operation. Pulse read signal above ▲
▼ is a circuit (not shown) that forms the operation timing signal φma of the May amp through the inverter circuit IV4
Be transmitted to. For example, the timing signal φma supplied to the main amplifier MA0 is set to a high level in synchronization with the pulse read signal ▲ ▼ when the address signal an is a low level. When the address signal an is high level, the timing signal φma of the other main amplifier MA1 is generated in synchronization with the pulse read signal ▲ ▼. On the other hand, the pulse write signal {circle around (5)} is transmitted via the inverter circuit IV5 to a circuit (not shown) which forms the operation timing signal φin of the data input circuit DIB. The timing signal φin is set to the high level in synchronization with the low level of the pulse write signal ▲ ▼.

Further, the pulse read signal ▲ ▼ and the pulse write signal ▲ ▼ are transmitted to the NAND gate circuit G5 which constitutes a substantial logical sum circuit. That is, when one of the signals is set to the low level (logic "0"), its output is set to the high level (logic "1"). The output signal of the NAND gate circuit G5 is the data line selection timing signal φy.
Is transmitted to the input of the timing generation circuit φy-G. The signal φy is one shot pulse ▲ ▼ or ▲
Y-decoder YDCR
The complementary data line selected by is connected to the common complementary data line. As a result, in synchronization with the data line selection operation, the main amplifier MA0 or MA1 for a read operation is
In the case of a write operation, the DIBs of the data input circuit are activated.

FIG. 3 shows a timing chart for explaining the read operation in the static column mode.

In the static column mode, the signal ▲ ▼ and Dout control signal ▲ ▼ remain low level even after the first word line W0 selection operation is performed by row addressing synchronized with the row address strobe signal ▲ ▼, and the column By switching the system address signal AY, the memory cells connected to the selected word line W0 are read one after another. In the above continuous read operation, in synchronization with the change of the column address signal, in other words, the switching of the data line, 1 is set for a certain period.
Timing signal φ synchronized with shot pulse ▲ ▼
Since the ma-amplifier is activated by ma, the power consumption can be reduced. Even when the main amplifier is deactivated, the data output circuit DOB outputs the output signal of the main amplifier held by the latch circuit to the external terminal Do
It can be continuously sent to ut.

FIG. 4 shows a timing chart for explaining the read operation in the page mode.

In page mode, row address strobe signal ▲
After the first 1-bit read operation is performed by row system and column system addressing synchronized with ▼ and the column address strobe signal ▲ ▼, the column address strobe signal ▲ ▼ is temporarily changed to capture the column address signal. High level. Then, at the timing when the column address strobe signal ▲ ▼ changes from the high level to the low level, the address signal AY for switching the column is fetched. Even in this case, the connection shown by the dotted line in FIG. 2 is performed to synchronize the pulse for a certain period in synchronization with the low level of the column address strobe signal ▲ ▼, in other words, in synchronization with the switching of the data line. Since the main amplifier is activated by the signal φma synchronized with ▲ ▼, its power consumption can be reduced. Note that the data output circuit DOB can continue to send the output signal of the main amplifier held by the latch circuit to the external terminal Dout even when the main amplifier is in the inactive state while the column address strobe signal ▲ ▼ is at the low level. .

Further, in the write operation, in both the above operation modes, only the operation timing signal φin of the data input circuit DIB is formed by the pulse ▲ ▼, and the operation timing signal of the main amplifier is not formed, so that the power consumption can be reduced. .

〔effect〕

(1) The one-shot pulse formed on the basis of the column address strobe signal causes the main amplifier to operate only temporarily, so that the power consumption can be reduced.

(2) To reduce the power consumption of the main amplifier in the static column mode or the page mode by temporarily operating the main amplifier according to either the change timing of the address signal or the column address strobe signal by the master slice method. The effect of being able to do is obtained.

(3) The power consumption can be reduced by temporarily operating the main amplifier in the read operation and the data input circuit in the write operation in synchronization with the column selection operation. can get.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. Nor. For example, one shot pulse for pulse read and pulse write may be formed from the data line selection timing signal. In this case, the data line selection timing signal is formed from the column address strobe signal or the address signal change detection signal. Further, the main amplifier may have any circuit configuration as long as its operating current flows according to the timing signal. Further, the dynamic RAM may adopt a half precharge method (dummy cellless method) in which the complementary data line is precharged to Vcc / 2 and this precharge signal is used as a read reference potential.

[Field of application]

The present invention can be widely applied to dynamic RAM.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an embodiment of a data output circuit and an input circuit, and FIG. 3 is an example of a read operation in a static column mode. 4 is a timing chart showing an example of the read operation in the page mode. M0 to M3 …… Memory array, SA0 to SA3 …… Sense amplifier,
XADB …… Row address buffer, CW0 to CW3 …… Column switch, YADB …… Column address buffer, XDCR0, XDCR
1 ... Row decoder, WDRV0 to WDRV3 ... Word line drive circuit, YDCR0, YDCR1 ... Column decoder, MA1, MA2 ... Main amplifier, TG ... Internal control signal generation circuit, DOB ... Data output circuit, DIB ... ... Data input circuit

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Kazumasa Yanagisawa 2326 Imai, Ome City, Tokyo Hitachi, Ltd. Device Development Center

Claims (4)

[Claims] 1. A column address strobe signal is received,
A timing generation circuit that generates a one-shot pulse signal that is substantially synchronized with the column selection operation, a main amplifier that is operated for a certain period of time by the pulse signal formed by this timing generation circuit, and an output signal of the main amplifier A dynamic RAM, including a data output circuit having a latch function. 2. The main amplifier is selectively supplied with a 1-shot pulse signal formed by an address signal change detection circuit which receives a pulse signal formed by the timing generation circuit and a column address signal by a master slice method. A dynamic RAM according to claim 1, characterized in that 3. A main amplifier that receives only one shot pulse generated almost in synchronization with a column selection operation only in a read operation mode and is operated only for a certain period, and an output signal of the main amplifier. A data output circuit having a latch function and a data input circuit which is operated only for a certain period of time in response to a one-shot pulse generated almost in synchronization with a column selection operation only in a write operation mode A dynamic RAM that is characterized by: 4. The column selection operation is synchronized with a data line selection timing signal formed by a logical sum output of a pulse signal for turning on the main amplifier and a pulse signal for turning on the data input circuit. The dynamic RAM according to claim 3, which is performed.