JPH06101237B2 - Sample and hold circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention adds, for example, an input signal to be sampled and held to a holding capacitor installed between the input and output terminals of a differential amplifier, and the sample and hold thereof is performed. And a sample and hold circuit for

[Conventional technology]

Conventionally, as shown in FIG. 5, a sample-and-hold circuit has a holding capacitor 4 between a negative input terminal of a differential amplifier 2 and its output terminal as a amplifying means, and a negative input of the differential amplifier 2. There is one in which a switch 6 controlled by a sampling signal SH is installed on the terminal side, and a feedback circuit is constituted by resistors 8 and 10. In this case, a bias voltage V _{B of a} specific positive voltage is applied to the positive input terminal side of the differential amplifier 2 from the bias circuit.

In such a sample and hold circuit, the input signal V _IN to be sampled and held is applied to the input terminal 12, and the switch 6 is controlled to be conductive at a constant time interval by the sampling signal SH. Therefore, at the time of sampling, the hold voltage of the capacitor 4 is compared with the input signal V _IN to perform level comparison, and the capacitor 4 is in a charged state or a discharged state depending on the magnitude relationship. As a result, the input signal V _IN at the time of sampling is sampled and is held in the holding capacitor 4 as a hold voltage until the next sampling. As a result, the hold voltage is output from the output terminal 14 to the sample and hold output voltage.
It is taken out as V _OUT .

[Problems to be solved by the invention]

By the way, in the sample and hold circuit, conventionally, when the switch 6 is composed of a bipolar transistor, the circuit structure is complicated and the response speed is slow.

Further, in the case of using the C-MOS switch as the switch 6, since the response speed of the sample and hold circuit is determined by the resistors 8 and 10 and the holding capacitor 4,
Since the resistance values of the resistors 8 and 10 and the capacitance value of the holding capacitor 4 cannot be increased, the precision of the sample and hold is low, and the resistors 8 and 10 are used to improve the precision.
When the resistance value of 1 and the capacitance value of the holding capacitor 4 are increased, there is a drawback that the response speed becomes slow.

Therefore, the present invention is intended to realize the simplification of the structure of the bipolar transistor, and to increase the response speed of the sample and hold and the accuracy thereof.

[Means for solving problems]

As illustrated in FIG. 1, the sample-and-hold circuit of the present invention includes a first constant current source 22 for supplying a constant current, a second constant current source 26 for drawing a constant current, and the first constant current source 26. A first switch 20 connected in series with the current source and opened / closed by a sampling signal; a second switch 24 connected in series with the second constant current source and opened / closed by the sampling signal; and the first switch 20. A first constant current source connected in series through a switch, conducting at the base by receiving an input signal to be sampled and held, and forming a constant current path from the first constant current source; Is connected in series to the second constant current source via the second switch and the second constant current source, and the base receives the input signal to be sampled and held to conduct, so that the second constant current source is constant. The second, which forms a current path for drawing current The transistor 18 and the base are connected to the first constant current source via the first switch, and a constant bias voltage is set to the first constant current source.
A third transistor 30 to which a base current is supplied from the first constant current source when the first transistor is non-conductive, and a first and a second resistor connected to the third transistor. Are connected in series via a series circuit including 34 and 36, the second constant current source is connected to the base via the second switch, and a constant bias voltage V _B is set. When the second switch is turned on, the reverse of the connection point between the fourth transistor 32, to which the base current is supplied by the second constant current source when the second transistor is not turned on, and the first and second resistors. Between a differential amplifier 2 to which a phase input is applied, a constant bias voltage is set on the positive phase input side, and the input signal is applied to the output side, and a negative phase input side and an output side of the differential amplifier. Before being connected to A charging circuit is formed through the third transistor, and a discharging circuit is formed through the fourth transistor. The charging circuit is placed in the charging state or the discharging state according to the magnitude relationship between the hold voltage and the level of the input signal, and is input in synchronization with the sampling pulse. And a holding capacitor 4 for holding the signal level as the hold voltage.

[Action]

The input signal V _IN to be sampled and held is matched with the hold voltage V _H held in the holding capacitor 4, and the difference voltage between the first and second transistors.
Added to 16,18. In addition, the switches 20 and 24 are turned on (sampling time) by the sampling signal SH.
T _SH ) is controlled.

At the sampling time T _SH , when the level of the input signal V _IN is higher than the hold voltage V _H (positive difference voltage + ΔV),
The first transistor 16 becomes non-conductive, and the constant current I flows from the constant current source 22 to the third transistor 30. The transistor 30 becomes conductive in response to the constant current I to form a charging circuit for the holding capacitor 4, and the holding capacitor 4 is charged through the transistor 30. Due to this charging, the hold voltage V _H becomes equal to the level of the input signal V _IN .

When the level of the input signal V _IN is smaller than the hold voltage V _{H at} the sampling time T _SH (negative difference voltage −Δ
V), the second transistor 18 becomes non-conductive, and the constant current I flows from the constant current source 26 to the fourth transistor 32. The transistor 32 becomes conductive in response to the constant current I to form a discharging circuit for the holding capacitor 4, and the holding capacitor 4 is discharged through the transistor 32. Due to this discharge, the hold voltage V _H becomes equal to the level of the input signal V _IN .

Transistor 3 according to such sampling signal SH
In accordance with the conduction of 0 and 32, the holding capacitor 4 is charged and discharged based on the magnitude relationship between the holding voltage V _H and the input signal V _IN.
The input signal V _{IN at SH} is retained.

〔Example〕

FIG. 1 shows an embodiment of the sample and hold circuit of the present invention.

An input signal V _IN to be held by a holding capacitor 4 connected between the negative input of the differential amplifier 2 and the output terminals as an amplifying means is applied to the first input terminal 12, and the first and second input terminals 12 are applied. The input signal V _IN is applied to the bases of the transistors 16 and 18 through the resistor 8 and the hold voltage V _H held in the hold capacitor 4 is applied through the resistor 10. That is, the transistor 16,
The input signal V _IN and the hold voltage V _H are matched with each other at the base of 18, and a difference voltage ± ΔV (= V _IN −V _H ) between them is added according to the ratio of the resistors 8 and 10. In this case, the transistor 16 is a PNP type transistor and the transistor 18 is an NPN type transistor. When the level of the input signal V _IN is higher than the hold voltage V _H (+ ΔV),
When the transistor 16 is non-conductive and the level of the input signal V _IN is lower than the hold voltage V _H (-ΔV), the transistor 16
18 becomes non-conductive.

A first constant current source 22 is installed on the emitter side of the transistor 16 via a first switch 20, and a second constant current source 22 is installed on the emitter side of the transistor 18 via a second switch 24.
A constant current source 26 is installed. Each switch 20, 24 is
At the sampling time T _SH of the sampling signal SH applied to the second input terminal 28, the contacts are closed to the contacts a ₂ and b ₂ .

The base of the third transistor 30 is connected to the emitter of the transistor 16 and the base of the fourth transistor 32 is connected to the emitter of the transistor 18, and the transistors 30 and 32 have resistors 34 and 36 on the emitter side, respectively. They are connected in series with each other. Also, the transistor 30
The collector of is connected to the positive power supply V _cc, and the collector of transistor 32 is grounded.
A constant bias voltage V _B is applied from the voltage source to the bases of 0 and 32 through the connection point of the resistors 38 and 40. In this case, the transistor 30 is an NPN type transistor and the transistor 32 is a PNP type transistor.

The negative input terminal of the differential amplifier 2 and the hold capacitor 4 are connected to the intermediate connection point between the resistors 34 and 36, and the hold voltage V _H of the hold capacitor 4 is taken out from the output terminal 14 as a sample hold output.

In such a sample and hold circuit, input terminals
When the input signal V _IN is applied to 12 and the sampling signal SH is applied to the input terminal 28, the switches 20 and 24 switch to the sampling signal SH.
Opening and closing are controlled by the contact point, and at the sampling time T _SH , the contacts a ₁ and b ₁ are closed to the contacts a ₂ and b ₂ .

At the sampling time T _SH , when the level of the input signal V _IN is higher than the hold voltage V _H (positive difference voltage + ΔV),
The transistor 16 becomes non-conductive, and the constant current I flows from the constant current source 22 to the base of the transistor 30. The transistor 30 becomes conductive in accordance with the constant current I to form a charging circuit for the holding capacitor 4, and the holding capacitor 4 is charged through the transistor 30. Due to this charging, the hold voltage V _H becomes equal to the level of the input signal V _IN .

When the level of the input signal V _IN is smaller than the hold voltage V _{H at} the sampling time T _SH (negative difference voltage −Δ
V), the transistor 32 becomes non-conductive instead of the transistor 30, and the constant current I is drawn from the transistor 32 to the constant current source 26. The transistor 32 becomes conductive in response to the constant current I to form a discharging circuit for the holding capacitor 4, and the holding capacitor 4 is discharged through the transistor 32. This discharge causes the hold voltage V _H to change to the input signal V
_The value will be equal to the _IN level.

Transistor 30 by such a sampling signal SH,
In accordance with the conduction of 32, the holding capacitor 4 is charged and discharged based on the magnitude relationship between the hold voltage V _H and the input signal V _IN , so that the sampling time T
The input signal V _{IN at SH} is retained.

Next, the operation of this sample and hold circuit will be described with reference to the operation waveforms shown in FIG.

The input signal V _IN shown in A of FIG.
When the sampling signal SH shown in B of FIG. 2 is added to 8, the pulse width of the sampling signal SH becomes the sampling time T _SH .

Because of the feedback circuit composed of the resistors 8 and 10, the bases of the transistors 16 and 18 have a bias voltage V _B at the sampling time T _SH corresponding to the input signal V _IN as shown in C of FIG. A difference voltage ± ΔV of The value of this difference voltage ± ΔV is the input signal V _IN , the hold voltage V _H and the resistors 8 and 10.
It is determined by the resistance ratio of.

In addition, the switch 20 makes contact with the sampling signal SH.
closed contact a ₂ side from a ₁ side, at the same time, the switch 24 contacts a ₁
Side to contact a ₂ side. In response to such a sampling operation, the base (point D) of the transistor 30 has a second
As shown in FIG. 2D, a voltage that rises in the positive direction with respect to the bias voltage V _B is generated, and as shown in E of FIG.
A voltage that drops in the negative direction with respect to V _B is generated. Also, an intermediate connection point (point F) between the first and second resistors 34, 36.
, A bias voltage V _B shown by F in FIG. 2 is generated.

Then, at the sampling time T _SH , a transistor is generated according to the difference voltage ± ΔV between the input signal V _IN and the hold voltage V _H.
As a result of controlling the conduction of 16 and 18, the charge state or the discharge state is maintained through the transistors 30 and 32 until the hold voltage V _H reaches the input signal V _IN .

As a result, at the output terminal 14, as shown in G of FIG.
The input signal V _IN is sampled and held in response to the sampling signal SH, and is in anti-phase relationship with the input signal V _IN. The sample-and-hold output voltage V _{OUT at}

Therefore, in such a sample and hold circuit,
Unlike the switch 6 of the conventional sample and hold circuit shown in FIG. 5, the circuit including the transistors 30 and 32 and the transistors 16 and 18 forms a buffer circuit to control the charging or discharging of the holding capacitor 4. Current source 22,
Since the constant current I of 26 is used as a reference through the transistors 16 and 18, the charging / discharging time of the holding capacitor 4 can be shortened.

The transistors 30 and 32 can be configured by bipolar transistors. In that case, the transistors 30 and 32 can be simply configured by two transistors, so that the circuit configuration is simple and the sample and hold operation can be performed with high accuracy.

In the sample and hold circuit of the present invention, as another embodiment, for example, as shown in FIG.
If a resistance 41, for example, is inserted on the negative input terminal side as a vibration prevention impedance, the loop gain of the circuit can be adjusted and ringing can be prevented.

Further, in the sample and hold circuit of the present invention, as shown in FIG. 4, the differential amplifier 2 includes transistors 42, 44, 4
When configured with 6, 48, the constant current source 50 and the resistors 52, 54, the base charge absorption prevention circuit 3 may be installed on the transistor 42 side of the negative input terminal side. When the constant current I flows through the constant current source 50 of the differential amplifier 2, the transistor 42
A half of the constant current I / 2 flows, and its base current is
The value is I / 2β divided by the current amplification factor β.

Therefore, in the base charge absorption prevention circuit 3,
A transistor 420 equivalent to 42 is installed, and a constant current I / 2 is caused to flow by a constant current source 56, a base current I / 2β at that time is detected, and this current I / 2β is formed by transistors 58, 60.
The base current I / 2β flowing through the transistor 42 is compensated by flowing the current to the base of the transistor 42 through the second current mirror circuit 65 including the current mirror circuit 61 and the transistors 62 and 64. As a result, it is possible to prevent the charge absorbed from the holding capacitor 4 to the base of the transistor 42 as a base current, and to obtain a more accurate sample
Hold can be realized.

The same effect can be expected even if the differential amplifier 2 of each embodiment is replaced with another amplification means such as an operational amplifier.

〔The invention's effect〕

According to the present invention, a switching circuit having a buffer configuration is used instead of the conventional switch, so that the input signal and the hold voltage are compared, and the holding capacitor is charged and discharged based on the comparison. ,
With a bipolar transistor, the circuit configuration can be simplified and highly accurate sample and hold can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the sample and hold circuit of the present invention, FIG. 2 is a diagram showing operation waveforms of respective parts of the sample and hold circuit shown in FIG. 1, and FIG. 3 is shown in FIG. FIG. 5 is a circuit diagram showing a modified example of the sample-hold circuit shown in FIG. 4, and FIG. 4 is a circuit diagram showing a specific example of a sample-hold circuit in which a transistor base charge absorption preventing circuit in a differential amplifier is added. FIG. 6 is a circuit diagram showing a conventional sample and hold circuit. 2 ... differential amplifier 4 ... holding capacitor 16 ... first transistor 18 ... second transistor 20 ... first switch 22 ... first constant current source 24 ... second switch 26 ...... Second constant current source 30 ...... Third transistor 32 ...... Fourth transistor 34 ...... First resistance 36 ...... Second resistance

Claims (1)

[Claims] 1. A first constant current source for supplying a constant current, a second constant current source for drawing a constant current, and a first constant current source connected in series to the first constant current source for opening and closing by a sampling signal. A switch, a second switch connected in series to the second constant current source and opened and closed by the sampling signal, and a second switch connected in series to the first constant current source via the first switch, A first transistor, which is made conductive by receiving an input signal to be sampled and held by the base and forms a current path of a constant current from the first constant current source, and the second constant through the second switch. A second transistor which is connected in series to a current source and which conducts upon receipt of an input signal to be sampled and held by the base and which forms a current path for the second constant current source to draw in a constant current; and the first transistor at the base. Via the switch Note that when the first constant current source is connected, a constant bias voltage is set, and the first switch is turned on, the base current from the first constant current source is turned off when the first transistor is turned off. Is connected in series to the third transistor via a series circuit including first and second resistors, and the second transistor is connected to the base via the second switch. A fourth constant current source is connected and a constant bias voltage is set, and when the second switch is conductive, a base current is supplied by the second constant current source when the second transistor is non-conductive. A reverse phase input is applied from the connection point between the transistor and the first and second resistors, a constant bias voltage is set on the positive phase input side, and the input signal is applied on the output side. A dynamic amplifier and a charging circuit connected between the negative phase input side and the output side of the differential amplifier and passing through the third transistor;
A discharge circuit is formed through the transistor, and the hold circuit holds the input signal level as the hold voltage in synchronization with the sampling pulse by being placed in a charge state or a discharge state according to the magnitude relationship between the hold voltage and the level of the input signal. And a capacitor for use in a sample and hold circuit.