JPH06101450B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device using a III-V group compound semiconductor such as GaAs, and more particularly to an improvement in a step of forming a high concentration n-type layer.

[Technical background of the invention and its problems]

Since III-V group compound semiconductors such as GaAs have high electron mobility, their application to electronic devices operating at high speed is being promoted. In manufacturing devices such as MESFETs and heterojunction bipolar transistors (HBTs) that use a heterojunction of AlGaAs and GaAs, a technique for selectively forming a high-concentration n-type layer is required to lower the contact resistance of ohmic electrodes. ing. Since these elements require particularly high controllability, the ion implantation method is exclusively used, and as the ion species of the n-type impurities, the implantation loss is relatively small and the diffusion constant is small. (Si)
Is often used.

By the way, as a problem of this type of conventional technique, it is difficult to form a high-concentration n-type layer by the ion implantation method.
Has become clear. This will be described below with reference to the drawings.

Figure 4 shows an n-type layer obtained by heat treatment by halogen lamp irradiation while implanting Si ⁺ into a semi-insulating GaAs substrate at an acceleration energy of 130 KeV and covering the surface with a CVDSiO ₂ film to prevent dissociation of As. 2 shows the relationship between the sheet carrier concentration and the amount of ion implantation. When the injection amount was 5 × 10 ¹³ / cm ² , the sheet carrier concentration was 65% of the injection amount, but the activation rate decreased as the injection amount was increased, and the injection amount was 1 × 10 ¹⁵ / cm ²
In, only 8% of the implanted ion amount acted as a donor.

The reason why the activation rate of Si is small is that Si is a group IV element and acts as an amphoteric dopant in GaAs. In order for Si to act as a donor, Si must be Ga
It is necessary to enter the lattice position, but as the Si implantation amount increases, As
The proportion of Si entering the lattice position increases, and the effective donor density does not increase.

In view of these points, attempts have recently been made to intentionally shift the atomic ratio of Ga and As from 1 in order to promote the substitution of Si for the Ga lattice position. For example, there is a method in which SiON is used for the surface protection film and Ga vacancies are generated in GaAs by utilizing the diffusion of Ga into the film, thereby increasing the activation rate of Si. However, this method lacks controllability and the activation rate of Si does not increase so much. In order to change the ratio of Ga and As more directly, As may be ion-implanted, but As is a heavy element and implantation damage increases, which rather lowers the activation rate of Si.

Thus, obtaining a high-concentration n-type layer by ion-implanting Si into a GaAs crystal has been an unsolved technical problem.

[Object of the Invention]

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above technical problems and provide a method for manufacturing a semiconductor device in which a high concentration n-type layer is formed in a III-V compound semiconductor layer by ion implantation of Si. .

[Outline of Invention]

In the present invention, phosphorus (P), which is not contained as a constituent element of the semiconductor layer, is ion-implanted before and after the step of ion-implanting Si into the III-V compound semiconductor layer, and after these ion-implanting steps. Heat treatment is performed to form a high concentration n-type layer.

〔The invention's effect〕

As described above, the reason why a high-concentration n-type GaAs layer cannot be obtained by ion implantation of Si is that part of the implanted Si replaces the As lattice point. In the present invention, in order to promote the substitution of Si for the Ga lattice point and to supplement the lack of the amount of As at that time, P, which is the same V group element as As, is implanted by ion implantation to serve as a Si donor. Improve the activation rate of. Since P has an atomic number of 15 and is only one larger than Si, it is possible to obtain the same projective range as Si with almost the same implantation energy as Si. Furthermore, the introduction of P does not induce new crystal defects in the GaAs crystal, as expected from GaP and GaAs forming a solid solution.

According to the present invention, n having a high carrier concentration of 5 × 10 ¹⁹ / cm ³ which could not be realized by the conventional Si ion implantation.
It became possible to obtain a mold layer. Ti is added to this high-concentration n-type layer.
A good non-alloyed ohmic electrode could be formed using the / Al film. As a result, the conventionally used alloy ohmic electrode made of AuGe alloy becomes unnecessary, and the reliability of the device can be improved and the cost can be reduced.

Example of Invention

Prior to the description of the embodiment applied to the production of a specific device, the experimental result of forming a high concentration n-type layer on a semi-insulating GaAs substrate by ion implantation of Si and P will be described.

Fig. 1 shows a semi-insulating GaAs substrate with Si and P of 130 KeV each.
And the same amount of ion implantation with the implantation energy of 140 KeV
It shows the relationship (solid line) between the Si implantation amount and the obtained sheet carrier concentration of the n-type layer. The figure also shows a conventional example (broken line) in which P ion implantation is not performed. The heat treatment after these ion implantations was performed by covering the surface with a CVDSiO ₂ film and heating to 1050 ° C. with a halogen lamp. In the conventional method, the carrier activation rate was 8% when the Si implantation amount was 1 × 10 ¹⁵ / cm ² , but it was 65% in the method of the present invention.
It showed a large value.

The carrier concentration distribution at this time is shown by the solid line in FIG. P
The peak carrier concentration is 5 × 10 ¹³ due to the combined use of ion implantation.
reached / cm ⁹ . Figure 2 shows Si at 130 KeV and 140 KeV.
The LSS theoretical curves of P in FIG. P
It is understood that the concentration distribution of is almost the same as that of Si.

FIG. 3 shows a sectional structure of an HBT to which the present invention is applied. In the figure, 1 is an n ⁺ type GaAs substrate, and 2 is an n type Ga serving as a collector.
As layer, 3 is a p-type GaAs layer serving as a base, 4 is an n-type AlGaAs layer serving as an emitter, and 5 is a high-concentration n-type emitter cap layer. The high-concentration n-type emitter cap layer 5 was formed by the method of the present invention using both Si and P ion implantation.

Thus, after forming an npn wafer using an AlGaAs-GaAs heterojunction for the emitter junction by using the epitaxial growth method or the ion implantation method, Mg is ion-implanted and the high concentration p ⁺
The mold external base layer 6 is formed. 7 is a base electrode, 8 is Si
An O ₂ film, 9 is an emitter electrode, and 10 is a high resistance layer formed by ion implantation of boron (B).

In the HBT according to this embodiment, the high-concentration n-type emitter cap layer 5 has a sufficiently low resistance, and Ti / Al is vapor-deposited on the emitter cap layer 5 having an implantation amount of 1 × 10 ¹⁵ / cm ² to provide a contact resistance. When measured, it was non-alloy and showed ohmic contact, and the specific contact resistivity was a small value of 4 × 0 ⁻⁷ · cm ² .

In the present invention, it is not always necessary to make the implantation amount of P and the acceleration voltage of implantation equal to that of Si.
For example, the implantation amount of P is selected in the range of about 1/10 to 10 times the implantation amount of Si, and the improvement of the impurity activation rate is recognized. The present invention can also be applied to the case of forming an n-type layer on other III-V group semiconductors such as InAs and AlGaAs in addition to GaAs. The present invention is naturally effective when a high-concentration n-type layer is formed in the source and drain regions of MESFET.

[Brief description of drawings]

FIG. 1 is a diagram showing the relationship between the amount of Si ions implanted into a semi-insulating GaAs substrate according to the present invention and the sheet carrier concentration, FIG. 2 is a diagram showing the same carrier concentration distribution, and FIG. 3 is an HBT to which the present invention is applied. Fig. 4 shows the semi-insulating GaAs by the conventional method.
It is a figure which shows the relationship of Si implantation amount with respect to a board | substrate, and sheet carrier concentration. 1 ... n ⁺ type GaAs substrate, 2 ... n type GaAs layer (collector),
3 ... p-type GaAs layer (base), 4 ... n-type AlGaAs layer (emitter), 5 ... n ⁺ -type emitter cap layer, 6 ... p ⁺
External base layer for mold, 7 ... Base electrode, 8 ... SiO ₂ film, 9
...... Emitter electrode, 10 …… High resistance layer.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location H01L 29/205 29/812

Claims (4)

[Claims] 1. A step of ion-implanting silicon into a III-V compound semiconductor layer, and a step of ion-implanting phosphorus which is not included as a constituent element of the semiconductor layer into the same region of the semiconductor layer before and after this step. And a step of performing a heat treatment after these ion implantation steps to form a high-concentration n-type layer, a method of manufacturing a semiconductor device. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the III-V group compound semiconductor is GaAs. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the high-concentration n-type layer is an emitter cap layer of a heterojunction bipolar transistor. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the high-concentration n-type layer is a source or drain region of a MOSFET.