JPH06101466B2 - Method for forming an insulating dielectric layer of silicon dioxide on a silicon layer - Google Patents
Method for forming an insulating dielectric layer of silicon dioxide on a silicon layerInfo
- Publication number
- JPH06101466B2 JPH06101466B2 JP58213177A JP21317783A JPH06101466B2 JP H06101466 B2 JPH06101466 B2 JP H06101466B2 JP 58213177 A JP58213177 A JP 58213177A JP 21317783 A JP21317783 A JP 21317783A JP H06101466 B2 JPH06101466 B2 JP H06101466B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- silicon
- silicon layer
- silicon dioxide
- amorphous silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6302—Non-deposition formation processes
- H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
- H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
- H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
Landscapes
- Formation Of Insulating Films (AREA)
- Semiconductor Memories (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】 この発明は高耐圧低漏洩電流の２酸化シリコンを被着シ
リコン上に形成する方法に関する。The present invention relates to a method of forming silicon dioxide having a high breakdown voltage and a low leakage current on an adhered silicon.
絶縁性誘電体で分離された多結晶シリコン層から成る多
レベル多結晶シリコン構体は、電荷結合装置のようなシ
リコン装置や、コンデンサ、EEPROM装置、CMOS装置のよ
うな集積回路構体に長年用いられている。この多結晶シ
リコン層は抵抗を下げるために燐ドーピングされること
もあるが、一般に基板温度約620℃で低圧化学蒸着によ
り形成される。絶縁性誘電体は一般に２酸化シリコン
で、下層の多結晶シリコン層の熱酸化または多結晶シリ
コン層上への化学蒸着により形成されるが、熱的に生成
した２酸化シリコンの方が処理が簡単で酸化物の純度が
よいため好ましい。Multi-level polycrystalline silicon structures, which consist of polycrystalline silicon layers separated by insulating dielectrics, have been used for many years in silicon devices such as charge-coupled devices and integrated circuit structures such as capacitors, EEPROM devices, and CMOS devices. There is. This polycrystalline silicon layer, which may be phosphorus-doped to reduce resistance, is generally formed by low pressure chemical vapor deposition at a substrate temperature of about 620 ° C. The insulating dielectric is generally silicon dioxide and is formed by thermal oxidation of the underlying polycrystalline silicon layer or chemical vapor deposition onto the polycrystalline silicon layer, but thermally generated silicon dioxide is easier to process. Is preferable because the oxide has good purity.
しかし下層の多結晶シリコン層上に熱成長させた２酸化
シリコンの絶縁性が単結晶シリコン上に熱成長させた２
酸化シリコンのそれより悪いことも公知である。すなわ
ちこれらの酸化物は絶縁耐力（破壊的降伏を生ずる電界
強度）が低く、与えられた印加電界で大きな漏洩電流を
示す。このような欠点は多結晶シリコンの粒子性とそれ
によるその表面の組織から来る２酸化シリコンとの界面
の粗さに原因する。すなわち表面の粗さによつてその界
面に局部電界の変化を生じ、これが酸化物内への電子注
入を増大するのである。However, the insulating property of the silicon dioxide that is thermally grown on the lower polycrystalline silicon layer is 2 that is thermally grown on the single crystal silicon.
It is also known to be worse than that of silicon oxide. That is, these oxides have low dielectric strength (electric field strength that causes destructive breakdown) and show a large leakage current in a given applied electric field. Such defects are due to the graininess of polycrystalline silicon and the resulting roughness of the interface with the silicon dioxide resulting from the texture of its surface. That is, the surface roughness causes a change in the local electric field at the interface, which increases electron injection into the oxide.
シリコンを含む雰囲気から温度580℃未満の基板上に蒸
着されたシリコンは、極めて表面の滑らかな無定形（ア
モルフアス）シリコン層を形成する。この被膜を温度90
0〜1000℃で焼ならしすると、その無定形シリコンが無
定形状態から平均粒径約0.08μの多結晶状態に転換す
る。この処理による驚くべき効果は、最初無定形状態で
蒸着された多結晶シリコン層の方が多結晶状態で蒸着さ
れた層より結晶粒径が著しく大きいにも拘らず、その多
結晶シリコンが極めて滑らかな表面を維持することであ
る。Silicon deposited from a silicon-containing atmosphere onto a substrate at a temperature below 580 ° C. forms an amorphous silicon layer with a very smooth surface. This coating has a temperature of 90
Normalizing at 0 to 1000 ℃ transforms the amorphous silicon from the amorphous state to the polycrystalline state with an average grain size of about 0.08μ. The surprising effect of this treatment is that even though the polycrystalline silicon layer initially deposited in the amorphous state has a significantly larger grain size than the layer deposited in the polycrystalline state, the polycrystalline silicon is extremely smooth. To maintain a smooth surface.
この発明は温度約580℃未満の基板上に無定形シリコン
の層を蒸着する段階と、その層を酸化する段階とを含む
２酸化シリコン層の製造法である。The present invention is a method of making a silicon dioxide layer that includes depositing a layer of amorphous silicon on a substrate at a temperature below about 580 ° C. and oxidizing the layer.
この発明はまた多結晶シリコン層上に２酸化シリコン層
を有し、その２酸化シリコン層が温度580℃未満で蒸着
された無定形シリコンの熱酸化により形成された半導体
装置も含んでいる。The present invention also includes a semiconductor device having a silicon dioxide layer on a polycrystalline silicon layer, the silicon dioxide layer being formed by thermal oxidation of amorphous silicon deposited at a temperature of less than 580 ° C.
第１図は一般に電荷結合装置に見られるゲート構体を表
面に持つ半導体装置の一部10を示す。この部分10は主表
面14を持つ単結晶シリコン基体12を含み、その基体12の
酸化によつて普通形成されるゲート酸化物16がその表面
を被つている。このゲート酸化物16上には普通２酸化シ
リコンの誘電体24により互いに絶縁されたそれぞれ３種
のゲート18、20、22を複数組多レベル構体中に含むゲー
ト構体がある。FIG. 1 shows a portion 10 of a semiconductor device having on its surface a gate structure commonly found in charge coupled devices. This portion 10 includes a single crystal silicon substrate 12 having a major surface 14 overlaid by a gate oxide 16 which is commonly formed by oxidation of the substrate 12. On top of this gate oxide 16 is a gate structure that includes three gates 18, 20, 22 each of which are insulated from each other by a dielectric 24, typically silicon dioxide, in a multilevel structure.
従来法では、ゲート18、20、22は一般に温度620℃以上
でシリコンとドープ剤、好ましくは燐を含む雰囲気から
低温化学蒸着により多結晶状態で被着した多結晶シリコ
ンから構成され、ゲート間の誘電体絶縁層はその多結晶
シリコン層を乾燥酸素雰囲気中において約900〜1100℃
で、または水蒸気中において約800〜900℃で加熱するこ
とにより形成し、その雰囲気にはまた一般に約３容積％
の気状HClを含ませる。In the conventional method, the gates 18, 20, 22 are generally composed of polycrystalline silicon deposited in a polycrystalline state by low temperature chemical vapor deposition from an atmosphere containing silicon and a dopant, preferably phosphorus at a temperature of 620 ° C. or higher, and The dielectric insulating layer has a polycrystalline silicon layer of about 900 to 1100 ° C in a dry oxygen atmosphere.
Formed by heating at about 800-900 ° C., or in steam, the atmosphere also generally containing about 3% by volume.
Gaseous HCl.
この発明の方法では、他の被着法を用いてもよいが、一
般に窒素で稀釈されたシランの形でシリコンを含む雰囲
気から低温化学蒸着法により無定形シリコンを被着し、
そのとき基板温度を580℃未満、一般に約550〜575℃、
好ましくは約560℃に保つ。次にこの無定形シリコン層
を約600℃以上、好ましくは約900〜1000℃の温度で焼な
らしすることにより多結晶状態に変換する。無定形シリ
コンを被着される基板は一般に表面にゲート酸化物層を
有する単結晶シリコンの基体である。Although other deposition methods may be used in the method of this invention, amorphous silicon is generally deposited by low temperature chemical vapor deposition from an atmosphere containing silicon in the form of silane diluted with nitrogen,
At that time, the substrate temperature is less than 580 ° C, generally about 550-575 ° C,
It is preferably maintained at about 560 ° C. This amorphous silicon layer is then converted to the polycrystalline state by normalizing at a temperature of about 600 ° C or higher, preferably about 900-1000 ° C. The substrate on which the amorphous silicon is deposited is generally a single crystal silicon substrate having a gate oxide layer on its surface.
無定形シリコン層は導電度変更剤、一般に燐を被着中の
雰囲気に燐を含む化合物を加えることによりドーピング
することもあるが、この無定形シリコン層のドーピング
はその層の被着と同時に行うよりドープ剤シリコン層の
表面が滑らかなため、後の段階で行うのが望ましいこと
が判つた。The amorphous silicon layer may be doped by adding a conductivity modifier, typically phosphorus, to the atmosphere during deposition by adding a compound containing phosphorus, but this amorphous silicon layer is doped at the same time as the deposition of the layer. It has been found that it is desirable to do it at a later stage because the surface of the dopant silicon layer is smoother.
無定形シリコン層は次の段階で当業者に公知の技法を用
いたドープ剤を含む雰囲気からのイオン注入または拡散
によつてドーピングを行うこともできる。拡散ドーピン
グではPOCl3を含む雰囲気を用い、無定形シリコン層を
約800〜1100℃の温度に加熱すればよく、イオン注入で
は次の酸化段階でドープ剤の活性化を行う。The amorphous silicon layer can also be doped in the next step by ion implantation or diffusion from an atmosphere containing a dopant using techniques known to those skilled in the art. In the diffusion doping, an atmosphere containing POCl 3 is used, and the amorphous silicon layer may be heated to a temperature of about 800 to 1100 ° C. In the ion implantation, the dopant is activated in the next oxidation step.
燐でドープした無定形シリコン層は約0.5％の酸素を含
む窒素雰囲気中において約850〜1000℃の温度で焼なら
しすることにより多結晶シリコンに変換することができ
る。酸素含有量が少ないと表面に薄いガラス層ができ
て、燐の逸出を防ぐと共に表面に窒化物が形成するのを
防止する。POCl3雰囲気中における無定形シリコン層の
拡散ドーピングもまたその層の表面に薄いガラス層の形
成をもたらす。何れの場合もそのガラスは一般に厚さ２
〜10nmで、燐で強くドープされている。このガラスは有
用な絶縁性誘電体ではなく、２酸化シリコンの絶縁性誘
電体の形成前にエツチングで除去される。The phosphorus-doped amorphous silicon layer can be converted into polycrystalline silicon by normalizing at a temperature of about 850 to 1000 ° C. in a nitrogen atmosphere containing about 0.5% oxygen. A low oxygen content creates a thin glass layer on the surface that prevents the escape of phosphorus and prevents the formation of nitrides on the surface. Diffusion doping of an amorphous silicon layer in a POCl 3 atmosphere also results in the formation of a thin glass layer on the surface of that layer. In both cases the glass is generally 2
At ~ 10 nm, heavily doped with phosphorus. This glass is not a useful insulating dielectric and is etched away prior to the formation of the silicon dioxide insulating dielectric.
工程のこの点では、シリコン層はそのドーピングを被着
中またはイオン注入によつて行つたとき無定形状態であ
る。層のドーピングを被着後拡散によつて行うと、その
ドーピング時の加熱により層はドーピング段階の始めに
充分多結晶状態に変る。下述の熱酸化段階でも被着され
た層は充分無定形状態から多結晶状態に変る。At this point in the process, the silicon layer is amorphous when its doping is done during deposition or by ion implantation. If the layer is doped by diffusion after deposition, the heating during the doping causes the layer to become fully polycrystalline at the beginning of the doping step. Even in the thermal oxidation step described below, the deposited layer changes from a sufficiently amorphous state to a polycrystalline state.
無定形シリコン層はドーピング段階でも酸化段階でもそ
の極めて早期に多結晶状態に変るにも拘らず、その上に
被着した２酸化シリコン層は、最初から多結晶状態で被
着された多結晶シリコン上に被着されたものより驚異的
に大きい絶縁耐力と低い漏洩電流を示すことが判つてい
る。Although the amorphous silicon layer changes into the polycrystalline state very early in the doping stage and the oxidation stage, the silicon dioxide layer deposited on the amorphous silicon layer is the polycrystalline silicon deposited in the polycrystalline state from the beginning. It has been found to exhibit surprisingly greater dielectric strength and lower leakage current than those deposited above.
シリコン層は一般に被着後酸化前に標準的写真食刻法を
用いてその一部を除去することにより１個またはそれ以
上の電極のような所要形状にパタン形成される。The silicon layer is generally patterned after deposition by removing a portion thereof using standard photolithographic techniques prior to oxidation to the desired shape, such as one or more electrodes.
シリコン層は無定形状態と多結晶状態の何れで被着され
ても上述のように水蒸気または乾燥酸素を含む雰囲気中
で加熱することにより酸化されるが、乾燥酸素雰囲気を
用いる方が好ましい。The silicon layer is oxidized by heating in an atmosphere containing water vapor or dry oxygen as described above regardless of whether it is deposited in an amorphous state or a polycrystalline state, but it is preferable to use a dry oxygen atmosphere.
２酸化シリコン層の厚さは少なくとも約10nmであるが一
般に約15nm以上であつて、約25nm以上が好ましい。The thickness of the silicon dioxide layer is at least about 10 nm, but generally about 15 nm or more, preferably about 25 nm or more.
この発明の方法により形成された２酸化シリコンは第２
図に示す試験装置を用いて試験した。The silicon dioxide formed by the method of the present invention has a second
It tested using the test apparatus shown in the figure.
試験試料はその表面42の一部を厚さ0.3μのゲート酸化
物44が被う単結晶シリコンの基体40を含み、そのゲート
酸化物44と基体40の表面42の一部をこの発明の方法によ
り被着された燐ドープ剤シリコン層から成るゲート電極
46が被つている。便宜上ゲート電極46はパタン形成され
ていない。このゲート電極46上にはこの発明の方法によ
り形成された２酸化シリコン層48があり、その層48の上
にはそれぞれ直径1mmのｎ型多結晶シリコン層とこれに
対するアルミニウム接触部から成る複数個の試験電極50
があつてその試験試料上に複数個の試験コンデンサを形
成している。The test sample includes a single crystal silicon substrate 40 overlying a portion of its surface 42 with a gate oxide 44 having a thickness of 0.3μ, the gate oxide 44 and a portion of the surface 42 of the substrate 40 being covered by the method of this invention. Electrode consisting of a phosphorus-doped silicon layer deposited by
46 is covered. For convenience, the gate electrode 46 is not patterned. A silicon dioxide layer 48 formed by the method of the present invention is formed on the gate electrode 46, and a plurality of n-type polycrystalline silicon layers each having a diameter of 1 mm and an aluminum contact portion thereto are formed on the layer 48. Test electrode 50
Then, a plurality of test capacitors are formed on the test sample.
測定装置は電圧源60、限流直列抵抗62および複数個の試
験電極50の１つに電気接触を与える探針64を備え、電流
が電圧源60から限流抵抗62、探針64、試料および電流計
66を通つて接地電位点に流れる。試料の両面間にはこれ
による電圧降下を測定する電圧計68が接続されている。The measuring device comprises a voltage source 60, a current limiting series resistance 62 and a probe 64 for making electrical contact with one of the plurality of test electrodes 50, and a current from the voltage source 60 to the current limiting resistor 62, the probe 64, the sample and Ammeter
It flows through 66 to the ground potential point. A voltmeter 68 for measuring the voltage drop caused by the voltmeter 68 is connected between both surfaces of the sample.
電圧源60は試験電極50に正または負の電圧を印加するこ
とができる。各試験コンデンサの降伏電圧と漏洩電流は
試験電極に正負の電圧を印加して各別に測定する。試験
コンデンサに流れる電流は本来ゲートまたは試験電極か
ら２酸化シリコンへの電子注入によるものであるから、
電圧の極性を変えて結果を比較することにより、ゲート
電極とその上の２酸化シリコン層との間の界面の品質を
評価することができる。The voltage source 60 can apply a positive or negative voltage to the test electrode 50. The breakdown voltage and leakage current of each test capacitor are measured separately by applying positive and negative voltages to the test electrodes. The current flowing through the test capacitor is originally due to electron injection from the gate or test electrode into silicon dioxide,
By changing the polarity of the voltage and comparing the results, the quality of the interface between the gate electrode and the silicon dioxide layer above it can be evaluated.
次の例はこの発明の説明に供するものであつて、何等こ
の発明の範囲を限定するものではない。The following examples serve to explain the present invention and do not limit the scope of the present invention in any way.
例 １ 上述のように共通のゲート電極と複数個の試験電極をそ
れぞれ有する３つの試験試料を乾燥酸素中の熱酸化によ
り作つた。試料１は温度560℃でゲート酸化物上にシラ
ン雰囲気中において低温化学蒸着により被着された無定
形シリコン層で、この層を次にPOCl3雰囲気から950℃15
分間拡散することにより燐でドープした。この処理によ
りシリコン層は面抵抗16Ω／□の多結晶シリコン状態に
変換された。次にこの層を乾燥酸素プラス３％HCl雰囲
気中において１時間1000℃に加熱し、そのシリコン層の
表面に厚さ108nmの２酸化シリコンを形成した。Example 1 Three test samples each having a common gate electrode and a plurality of test electrodes as described above were prepared by thermal oxidation in dry oxygen. Sample 1 is an amorphous silicon layer deposited by low temperature chemical vapor deposition in a silane atmosphere on a gate oxide at a temperature of 560 ° C, which is then exposed to a POCl 3 atmosphere at 950 ° C.
Doped with phosphorus by diffusion for minutes. By this treatment, the silicon layer was converted into a polycrystalline silicon state with a surface resistance of 16Ω / □. Next, this layer was heated to 1000 ° C. for 1 hour in an atmosphere of dry oxygen plus 3% HCl to form silicon dioxide having a thickness of 108 nm on the surface of the silicon layer.
この２酸化シリコン層上に次の手順で複数個の試験電極
を形成した。A plurality of test electrodes were formed on this silicon dioxide layer by the following procedure.
（ａ）酸化物層上に厚さ約700nmの多結晶シリコン層を
被着する。(A) Deposit a polycrystalline silicon layer about 700 nm thick on the oxide layer.
（ｂ）この多結晶シリコン層をPOCl3源からの燐の拡散
によりドーピングする。(B) Doping this polycrystalline silicon layer by diffusion of phosphorus from a POCl 3 source.
（ｃ）標準の写真食刻法を用いて多結晶シリコンドツト
を画定する。(C) Define polycrystalline silicon dots using standard photolithographic techniques.
（ｄ）この多結晶シリコンドツトを露出した２酸化シリ
コンの双方を含む全表面にアルミニウム被覆をする。(D) An aluminum coating is applied to the entire surface including both of the silicon dioxide which has exposed this polycrystalline silicon dot.
（ｅ）標準の写真食刻法を用いて多結晶シリコンドツト
上にそれより直径の小さいアルミニウムドツトを画定す
る。(E) Define smaller diameter aluminum dots on the polycrystalline silicon dots using standard photolithographic techniques.
試料２は試料１と同じ方法で形成したが、無定形シリコ
ン層をシランとホスフインを含む雰囲気から560℃で被
着して、被着と同時にドーピングを行つた。この無定形
シリコン層の面抵抗は10Ω／□であつた。試料１と同様
にして厚さ130nmの２酸化シリコン層を形成し、この上
に上述のようにして試験電極を形成した。Sample 2 was formed by the same method as Sample 1, except that an amorphous silicon layer was deposited at 560 ° C. from an atmosphere containing silane and phosphine, and doping was performed simultaneously with the deposition. The sheet resistance of this amorphous silicon layer was 10Ω / □. A 130 nm-thick silicon dioxide layer was formed in the same manner as in Sample 1, and a test electrode was formed thereon as described above.
試料３は比較試料で、シランを含む雰囲気から620℃で
被着した後POCl3雰囲気から950℃で15分ドーピングして
通常の多結晶シリコン層を形成し、この多結晶シリコン
層の上に試料１のようにして厚さ95nm、面抵抗18Ω／□
の２酸化シリコン層を形成し、さらに試料１のようにし
て試験電極を形成したものである。Sample 3 is a comparative sample, which is deposited at 620 ° C. from an atmosphere containing silane and then doped at 950 ° C. for 15 minutes in a POCl 3 atmosphere to form a normal polycrystalline silicon layer. The thickness is 95nm and the surface resistance is 18Ω / □
The silicon dioxide layer is formed, and the test electrode is formed as in Sample 1.
第３図ａ、ｂ、ｃはそれぞれ試験電極の正負の電圧を印
加したとき与えられた範囲に絶縁破壊電界強のある装置
の百分率のヒストグラムを試験試料１、２、３について
描いたものである。FIGS. 3a, 3b and 3c respectively show, for test samples 1, 2 and 3, histograms of percentages of devices having a breakdown electric field strength within a given range when positive and negative voltages are applied to the test electrodes. .
この図から、無定形状態で被着したシリコン層から形成
された２酸化シリコンは、それの酸化開始時に無定形で
も結晶質でも、平均として多結晶状態で被着されたシリ
コン上に形成された２酸化シリコンより絶縁破壊強度が
約２倍大きいことが明らかである。From this figure, the silicon dioxide formed from the silicon layer deposited in the amorphous state was formed on the silicon deposited in the polycrystalline state on average, whether amorphous or crystalline at the beginning of its oxidation. It is clear that the dielectric breakdown strength is about twice as high as that of silicon dioxide.
電圧極性を反転すると試験電極から電子注入が起る。酸
化物の生長中にゲートと２酸化シリコンの界面の粗さが
一部除かれるため、試験電極と酸化物の界面はゲートと
２酸化シリコンの界面より滑らかになる。この場合は無
定形状態で被着された層と多結晶状態で被着された層の
差は余り大きくなく、絶縁破壊電圧の上昇も少ない。When the voltage polarity is reversed, electron injection occurs from the test electrode. The roughness of the interface between the gate and silicon dioxide is partially removed during the growth of the oxide, so that the interface between the test electrode and the oxide is smoother than the interface between the gate and silicon dioxide. In this case, the difference between the layer deposited in the amorphous state and the layer deposited in the polycrystalline state is not so large, and the increase in the dielectric breakdown voltage is small.
試料１はどちらの電圧極性についても試料２より平均破
壊電圧が高い。この結果は無定形シリコン層のドーピン
グを被着と同時に行うより被着後に行う方がよいことを
示し、この結果は無定形シリコンから多結晶シリコンへ
の転換がドーピング段階の始めに起るという点で驚くべ
きことである。このときドープ剤の原子は結晶粒界に選
択的に入り、ここがドープ剤過剰になるため、次の酸化
がこの結晶粒界で優先的に起る。このためシリコン表面
の粗さが増大する。Sample 1 has a higher average breakdown voltage than Sample 2 for both voltage polarities. This result indicates that it is better to do the doping of the amorphous silicon layer after deposition than at the same time as deposition, the result being that the conversion of amorphous silicon to polycrystalline silicon occurs at the beginning of the doping step. Is amazing. At this time, atoms of the doping agent selectively enter the crystal grain boundary, and the doping agent is excessively present there, so that the next oxidation preferentially occurs at this crystal grain boundary. Therefore, the roughness of the silicon surface increases.
例 ２ 上述のように共通のゲート電極と複数個の試験電極をそ
れぞれ有する３つの試験試料を、水蒸気雰囲気中でゲー
ト電極の一部を熱酸化して作つた。試料４は例１の試料
１の場合のように被着されドーピングされた無定形シリ
コンのゲート電極を有し、約19Ω／□の面抵抗を示し
た。水蒸気雰囲気中で形成された２酸化シリコン層の厚
さは175nmであつた。試料５は試料４と同じ方法で形成
したが、例１の試料２の場合のように無定形シリコン層
の被着とドーピングを同時に行つた。このシリコン層の
面抵抗は10Ω／□であり、水蒸気雰囲気中で形成した２
酸化シリコン層の厚さは161nmであつた。試料６は比較
用試料で、例１の試料３に対応し、620℃において多結
晶状態でシリコン層を被着した後、POCl3雰囲気中にお
いて950℃で15分間ドーピングを行つた。この多結晶層
の面抵抗は15Ω／□、水蒸気雰囲気中において850℃で
形成した２酸化シリコン層の厚さは200nmであつた。Example 2 Three test samples each having a common gate electrode and a plurality of test electrodes as described above were prepared by thermally oxidizing a part of the gate electrode in a water vapor atmosphere. Sample 4 had a gate electrode of amorphous silicon deposited and doped as in Sample 1 of Example 1 and exhibited a sheet resistance of about 19 Ω / □. The thickness of the silicon dioxide layer formed in the water vapor atmosphere was 175 nm. Sample 5 was formed in the same manner as Sample 4, but the amorphous silicon layer was deposited and doped at the same time as in Sample 2 of Example 1. The sheet resistance of this silicon layer is 10Ω / □, and it was formed in a water vapor atmosphere.
The thickness of the silicon oxide layer was 161 nm. Sample 6 is a comparative sample, corresponding to sample 3 of Example 1, after depositing a silicon layer in a polycrystalline state at 620 ° C. and then doping in a POCl 3 atmosphere at 950 ° C. for 15 minutes. The sheet resistance of this polycrystalline layer was 15Ω / □, and the thickness of the silicon dioxide layer formed at 850 ° C. in a water vapor atmosphere was 200 nm.
第４図ａ、ｂ、ｃはそれぞれ試験電極に正負の電圧を印
加したとき絶縁破壊電界強度が与えられた範囲にある装
置の百分率のヒストグラムを試料４、５、６について描
いたものである。試験電極の正の試験電圧を印加したと
きは、25〜50％程度の僅かな破壊電界強度の上昇が認め
られ、また試験電極に負の試験電圧を印加したときも破
壊電界強度に同様の上昇が認められる。FIGS. 4a, 4b and 4c are the histograms of the percentages of the devices in the range where the breakdown electric field strength is applied when positive and negative voltages are applied to the test electrodes, for samples 4, 5 and 6, respectively. When a positive test voltage is applied to the test electrode, a slight increase in the breakdown field strength of about 25 to 50% is observed, and when a negative test voltage is applied to the test electrode, the breakdown field strength similarly rises. Is recognized.
これらの破壊電界強度を各形式の試料について試料１、
２、３に対するそれと比較すると、熱酸化を水蒸気雰囲
気中で行つたものより乾燥酸素雰囲気中で行つたものの
方が常に破壊電界強度が高いことが判る。These breakdown electric field strengths were measured for each type of sample, Sample 1,
Comparing with those for 2 and 3, it can be seen that the breakdown electric field strength is always higher in the case where the thermal oxidation is performed in the dry oxygen atmosphere than in the case where the steam oxidation is performed.
例 ３ ４種の試料に3MV/cmの一定電界を印加して漏洩電流密度
を測定した。この結果は下表に示す。試料Ａを試料１の
場合のように無定形状態で被着し、ドーピング後乾燥酸
素中で酸化して形成した。酸化物層の厚さは160nmであ
つた。Example 3 Leakage current density was measured by applying a constant electric field of 3 MV / cm to four kinds of samples. The results are shown in the table below. Sample A was deposited in the amorphous state as in Sample 1, and was formed by doping and oxidizing in dry oxygen. The thickness of the oxide layer was 160 nm.
試料Ｂを試料３の場合のように多結晶状態で被着し、ド
ーピング後乾燥酸素中で酸化して形成した。酸化物層の
厚さは130nmであつた。Sample B was deposited in the polycrystalline state as in sample 3, and after doping was oxidized in dry oxygen. The thickness of the oxide layer was 130 nm.
試料Ｃを試料４の場合のように無定形状態で被着し、ド
ーピング後水蒸気中で酸化して形成した。酸化物層の厚
さは116nmであつた。Sample C was deposited in an amorphous state as in sample 4, and was formed by doping and oxidizing it in water vapor. The thickness of the oxide layer was 116 nm.
試料Ｄを試料６の場合のように多結晶状態で被着し、ド
ーピング後水蒸気中で酸化して形成した。酸化物層の厚
さは80nmであつた。Sample D was deposited in the polycrystalline state as in Sample 6, and was formed by doping and oxidizing in water vapor. The thickness of the oxide layer was 80 nm.
このようにこの発明の方法によつて、すなわち無定形状
態で被着されたシリコン上に乾燥酸素中における酸化に
より形成された２酸化シリコン層は、通常の方法で形成
された２酸化シリコン層より３倍以上も漏洩電流が小さ
い。 Thus, a silicon dioxide layer formed by the method of the present invention, i.e., by oxidation in dry oxygen on silicon deposited in an amorphous state, is more than a silicon dioxide layer formed by conventional methods. The leakage current is three times or more smaller.
第１図はこの発明の一例半導体装置の断面図、第２図は
この発明の方法により形成された２酸化シリコンの性質
の測定に用いる試験装置の略図、第３図および第４図は
無定形シリコン層と多結晶シリコン層の上に形成された
２酸化シリコン層の破壊電圧を示すヒストグラムであ
る。 18、20、22、46……シリコン層、24、48……絶縁誘電体
層、50……追加の層。FIG. 1 is a cross-sectional view of a semiconductor device as an example of the present invention, FIG. 2 is a schematic view of a test apparatus used for measuring the properties of silicon dioxide formed by the method of the present invention, and FIGS. 3 and 4 are amorphous. 6 is a histogram showing a breakdown voltage of a silicon dioxide layer formed on a silicon layer and a polycrystalline silicon layer. 18, 20, 22, 46 ... Silicon layer, 24, 48 ... Insulating dielectric layer, 50 ... Additional layers.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭56−76537（ＪＰ，Ａ) 特開 昭55−44793（ＪＰ，Ａ) 特開 昭52−104870（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-56-76537 (JP, A) JP-A-55-44793 (JP, A) JP-A-52-104870 (JP, A)
Claims (6)
面を有する無定形シリコン層を蒸着し、この無定形シリ
コン層を乾燥酸素雰囲気中で900〜1100℃の温度に加熱
することにより、上記無定形シリコン層の表面層を酸化
して多結晶状態の２酸化シリコン層よりなる絶縁誘電体
層を形成するとともに上記無定形シリコン層の上記表面
層以外の部分を多結晶状態のシリコンに変換する段階を
含むことを特徴とする、シリコン層上に２酸化シリコン
の絶縁誘電体層を作る方法。1. Deposition of an amorphous silicon layer having a smooth surface on a substrate at a temperature of about 550 to 580 ° C. and heating the amorphous silicon layer to a temperature of 900 to 1100 ° C. in a dry oxygen atmosphere. To oxidize the surface layer of the amorphous silicon layer to form an insulating dielectric layer made of a polycrystalline silicon dioxide layer, and to form a portion of the amorphous silicon layer other than the surface layer in the polycrystalline silicon layer. A method of forming an insulating dielectric layer of silicon dioxide on a silicon layer, the method including the step of converting to.
層をドーピングする段階を含む特許請求の範囲第１項記
載の方法。2. The method of claim 1 including the step of doping the amorphous silicon layer prior to said oxidizing step.
ドーピングする段階が同時に行われる特許請求の範囲第
２項記載の方法。3. A method according to claim 2 wherein the step of depositing and the step of doping the amorphous silicon layer are performed simultaneously.
ある特許請求の範囲第２項記載の方法。4. The method according to claim 2, wherein the doping agent for doping is phosphorus.
約560℃の温度で行われる特許請求の範囲第４項記載の
方法。5. The method of claim 4 wherein the step of depositing the amorphous silicon layer is performed at a temperature of about 560.degree.
950〜1050℃の温度で行われる特許請求の範囲第５項記
載の方法。6. A step of oxidizing said amorphous silicon layer
The method according to claim 5, which is carried out at a temperature of 950 to 1050 ° C.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US44137282A | 1982-11-12 | 1982-11-12 | |
| US441372 | 1982-11-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59103347A JPS59103347A (en) | 1984-06-14 |
| JPH06101466B2 true JPH06101466B2 (en) | 1994-12-12 |
Family
ID=23752622
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58213177A Expired - Lifetime JPH06101466B2 (en) | 1982-11-12 | 1983-11-11 | Method for forming an insulating dielectric layer of silicon dioxide on a silicon layer |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPH06101466B2 (en) |
| DE (1) | DE3340583A1 (en) |
| FR (1) | FR2536208B1 (en) |
| GB (1) | GB2131407B (en) |
| IT (1) | IT1171798B (en) |
| SE (1) | SE500975C2 (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4814291A (en) * | 1986-02-25 | 1989-03-21 | American Telephone And Telegraph Company, At&T Bell Laboratories | Method of making devices having thin dielectric layers |
| US4874716A (en) * | 1986-04-01 | 1989-10-17 | Texas Instrument Incorporated | Process for fabricating integrated circuit structure with extremely smooth polysilicone dielectric interface |
| EP0281233A1 (en) * | 1987-01-30 | 1988-09-07 | AT&T Corp. | Improved formation of dielectric on deposited silicon |
| US5851871A (en) * | 1987-12-23 | 1998-12-22 | Sgs-Thomson Microelectronics, S.R.L. | Process for manufacturing integrated capacitors in MOS technology |
| EP0598409B1 (en) * | 1989-02-14 | 1998-11-18 | Seiko Epson Corporation | A method of manufacturing a semiconductor device |
| EP0545585A3 (en) * | 1991-12-03 | 1996-11-06 | American Telephone & Telegraph | Integrated circuit fabrication comprising a locos process |
| US5712177A (en) * | 1994-08-01 | 1998-01-27 | Motorola, Inc. | Method for forming a reverse dielectric stack |
| US5665620A (en) * | 1994-08-01 | 1997-09-09 | Motorola, Inc. | Method for forming concurrent top oxides using reoxidized silicon in an EPROM |
| EP1192647B1 (en) * | 1999-06-25 | 2010-10-20 | Massachusetts Institute Of Technology | Oxidation of silicon on germanium |
| CN112992672B (en) * | 2019-12-16 | 2022-10-14 | 山东有研半导体材料有限公司 | Preparation method of silicon-based silicon dioxide back sealing film |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3900345A (en) * | 1973-08-02 | 1975-08-19 | Motorola Inc | Thin low temperature epi regions by conversion of an amorphous layer |
| JPS5910060B2 (en) * | 1976-03-01 | 1984-03-06 | 株式会社日立製作所 | Manufacturing method of semiconductor device |
| IT1089298B (en) * | 1977-01-17 | 1985-06-18 | Mostek Corp | PROCEDURE FOR MANUFACTURING A SEMICONDUCTIVE DEVICE |
| US4166919A (en) * | 1978-09-25 | 1979-09-04 | Rca Corporation | Amorphous silicon solar cell allowing infrared transmission |
| JPS55115341A (en) * | 1979-02-28 | 1980-09-05 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor device |
| JPS5676537A (en) * | 1979-11-27 | 1981-06-24 | Fujitsu Ltd | Manufacture of semiconductor device |
| US4479831A (en) * | 1980-09-15 | 1984-10-30 | Burroughs Corporation | Method of making low resistance polysilicon gate transistors and low resistance interconnections therefor via gas deposited in-situ doped amorphous layer and heat-treatment |
| US4358326A (en) * | 1980-11-03 | 1982-11-09 | International Business Machines Corporation | Epitaxially extended polycrystalline structures utilizing a predeposit of amorphous silicon with subsequent annealing |
| US4441249A (en) * | 1982-05-26 | 1984-04-10 | Bell Telephone Laboratories, Incorporated | Semiconductor integrated circuit capacitor |
-
1983
- 1983-11-03 GB GB08329380A patent/GB2131407B/en not_active Expired
- 1983-11-04 SE SE8306071A patent/SE500975C2/en unknown
- 1983-11-10 FR FR8317930A patent/FR2536208B1/en not_active Expired
- 1983-11-10 DE DE19833340583 patent/DE3340583A1/en active Granted
- 1983-11-11 JP JP58213177A patent/JPH06101466B2/en not_active Expired - Lifetime
- 1983-11-11 IT IT23691/83A patent/IT1171798B/en active
Also Published As
| Publication number | Publication date |
|---|---|
| IT1171798B (en) | 1987-06-10 |
| IT8323691A0 (en) | 1983-11-11 |
| GB2131407B (en) | 1987-02-04 |
| FR2536208B1 (en) | 1987-03-20 |
| JPS59103347A (en) | 1984-06-14 |
| DE3340583A1 (en) | 1984-05-17 |
| SE8306071L (en) | 1984-05-13 |
| DE3340583C2 (en) | 1993-04-29 |
| FR2536208A1 (en) | 1984-05-18 |
| GB8329380D0 (en) | 1983-12-07 |
| GB2131407A (en) | 1984-06-20 |
| SE500975C2 (en) | 1994-10-10 |
| SE8306071D0 (en) | 1983-11-04 |
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