JPH06101509B2 - Semiconductor process abnormality diagnosis method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor process abnormality diagnosis method, and more particularly to a diagnosis method of collecting knowledge of wafer process abnormality diagnosis and setting a test pattern on a semiconductor wafer. Is.

[Background of the Invention]

With the miniaturization of semiconductor products, it is becoming more and more difficult to develop new processes or perform process diagnosis for the purpose of improving yield quickly and accurately. One method for solving this problem is to create a test pattern for each analysis purpose on a product wafer and analyze this test pattern. However, in order to analyze such a test pattern, diagnostic knowledge obtained from actual diagnostic experience is indispensable, and in order to effectively utilize the analysis of the test pattern, it is necessary to collect the above-mentioned diagnostic knowledge.

Conventionally, a method of creating a special test pattern for analysis on a product wafer and analyzing this test pattern has been described, for example, in "Automatic Parameter Tester for Integrated Circuit Process Monitor" (Kaempf, Solid State Tec).
hnology (Japanese version) Nov, 1981.pp.62-69) or "Statistical modeling approach.
For Similation of MOS VLSI Circuit Design "(A Statistical Modeling Approach for
Simulation of MOS VLSI Circuit Design: Herr, IEEE IE
DM82, pp290-293 (1982)). However, in the conventional techniques including the above-mentioned documents, only to statistically analyze the inspection data, and to investigate the cause of the abnormality from the abnormal occurrence state of the inspection data,
Nothing said. That is, in the past, in order to investigate the cause, the analyst himself used the interpretation of the data analysis result. Recently, applying knowledge engineering technology,
A method of incorporating diagnostic knowledge for investigating the cause into a computer and causing the computer to perform the investigating of the cause has been considered, but how to collect diagnostic knowledge in this case is a big problem. Further, since the test pattern used conventionally is for measuring the electrical characteristics, the three-dimensional processing accuracy, stability, etc. including the state of the processed surface or the state of the cut surface by etching is tested. It was unsuitable for this.

[Object of the Invention]

The object of the present invention is to improve such conventional problems and to easily collect abnormality diagnosis knowledge, and by utilizing this, detect structural abnormality of a semiconductor product without spending a great deal of time and labor. It is therefore an object of the present invention to provide a semiconductor process abnormality diagnosis method capable of diagnosing an abnormality in a manufacturing process and forming a test pattern on a product wafer without changing the wafer manufacturing process.

[Outline of Invention]

In order to achieve the above object, a semiconductor process abnormality diagnosis method of the present invention includes a test pattern on a semiconductor wafer that is a semiconductor product, collects inspection data of the test pattern, and based on the inspection data, the semiconductor After estimating the element parameter value of the wafer, it is determined whether or not the element parameter is abnormal by comparing with the standard range,
It is characterized in that a known abnormality cause of the wafer is accepted, the abnormality cause and the above-mentioned abnormality occurrence state are paired, and this is stored as diagnostic knowledge.

Example of Invention

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram of an abnormality diagnosing apparatus for a semiconductor manufacturing process showing an embodiment of the present invention. As shown here, the semiconductor manufacturing process includes a manufacturing process 1-1 and an inspection process 1-2. The manufacturing process 1-1 includes, for example, an oxidation / diffusion process, an implantation process, a photoetching process, etc. The manufacturing process itself is a conventional manufacturing process, and semiconductor wafers are sequentially processed. Then we make product pellets. Inspection process 1
The step -2 is a step of measuring the electrical characteristic data of the test pattern specially provided on the wafer by the measuring device. After the above measurement data is transferred to the storage device 3 through the data collection device 2, the element parameter value is estimated by the processing device 4, and the estimation result is compared with a predetermined reference range. The presence or absence of abnormality is determined. In addition,
In the configuration of FIG. 1, the data collection device 2, the storage device 3, the processing device 4, and the display device 5 can be realized by one computer system including an external memory, an input / output device, and the like.

In this embodiment, a test pattern is provided on a semiconductor wafer to be a semiconductor product, and a wafer including a pellet whose cause of abnormality is known is prepared for such a wafer. The diagnostic knowledge for diagnosing these pellets can be easily collected as follows. That is, a step of collecting inspection data of the test pattern, and element parameter values (film thickness, dimensions, etc.) of the semiconductor pellet based on the inspection data.
And a step of determining whether or not there is an abnormality in the element parameter by comparing it with the standard range, and a step of combining the cause and the above-mentioned abnormality occurrence state and storing this as diagnostic knowledge. This simplifies the collection of diagnostic knowledge.

FIG. 2 is a diagram of a test pattern provided on a wafer in the present invention. The diagnostic test pattern on the wafer, which is the measured pattern for estimating the element parameter value, is similar to the conventional test pattern used for process technology development. 21,22 is the measured object, 23,23 ', 24,
24 'is a measuring terminal (pad).

Next, the estimation processing of the element parameter value performed by the processing device 4 of FIG. 1 will be described with a specific example. Element parameters of a field effect transistor (FET), which is one of the main elements constituting a semiconductor product, include dimensions, film thickness, impurity concentration, and the like. On the other hand, a special test pattern as shown in FIG. 2 is created on the same wafer as the product chip, and it can be empirically estimated from the measured values. As a basis of estimation, electric resistance is used as a parameter relating to dimensions, and electric capacity is used as a parameter relating to film thickness, impurity concentration and the like.

A specific method for estimating the element parameter will be described by taking the oxide film thickness as an example. For this estimation, for example, a test pattern as shown in FIG. 2 is created and used. In FIG. 2, reference numerals 21 and 22 denote electrodes, and a film (design value d) whose thickness is to be estimated is sandwiched between both electrodes. l ₁ and W ₁ are
The value is set to be larger than the dimensional variation in the manufacturing process, and the influence of the variation is relatively small. When the capacitance per unit area q [F / m ² ] is calculated from the capacitance C [F] obtained by measuring the test pattern of FIG. Becomes Here, since the dielectric constant ε [F / m] of the desired film thickness can be known from the composition of the film to be formed, the estimated value d [m] of the film thickness d can be calculated from the equation (1). Becomes Since this test pattern is formed on the product wafer at the same time as the product pellet, it can be considered that the value of d is the oxide film thickness of the product pellet. In addition,
In order to correctly estimate this test pattern,
It is indispensable that the test pattern is normally manufactured as designed, and it is necessary to check the preconditions in order to apply the equations (1) and (2). As an example, check K ₁ ≤ C ≤ K ₂ (3). Here, K ₁ and K ₂ are constants and indicate upper and lower limit values with respect to measured values when the test pattern is normally manufactured.

FIG. 3 is a flow chart of the oxide film thickness estimation processing according to the present invention. Further, element parameters relating to various dimensions and impurity concentrations other than the film thickness can be estimated by the same processing as the method shown in FIG. That is, first, the measured data of the test pattern is read out (step 3
1) Check the preconditions in the estimation formula (step 32). When the condition is satisfied, the capacitance per unit is estimated (step 33), and then the film thickness is estimated (step 32). In step 34), the estimated value is compared with a predetermined value to judge normality / abnormality (step 35). It is determined whether or not all the estimated parameters have ended, and if they have ended, the processing ends (step 36).

FIG. 4 is a device parameter value of the FET estimated by the method of FIG. The processing device 4 estimates various parameter values as shown in FIG. 4, determines normality and abnormality, and then accepts the cause of abnormality of the target pellet from the user via the input / output terminal device 5. Further, the apparatus 4 stores the determination result of the normality / abnormality of the element parameter value obtained as described above and the abnormality cause as one set as one horizontal row in the decision table format shown in FIG. . In FIG. 5, each row in the horizontal direction indicates that "when the cause of abnormality shown in the leftmost column occurs, abnormality is found in all the parameters marked with a circle." This is diagnostic knowledge. Every time a defective pellet is generated and its cause is known,
The diagnostic knowledge can be easily collected by collecting the diagnostic knowledge as described above.

The following method is used to investigate the cause of a new wafer abnormality using the diagnostic knowledge collected in this way. That is, the abnormality determination of the element parameter is performed in exactly the same manner as the above-mentioned knowledge collection. After the abnormality occurrence state of the element parameter is found out by this, the abnormality of the estimated parameter is utilized by utilizing the table of FIG. The abnormal process of the manufacturing process is investigated from the result of the judgment. Specifically, in each row in the horizontal direction of FIG. 5, if all the parameters marked with a circle have an abnormality, it is determined that an abnormality has occurred in the process shown on the left side. These results are displayed on the display device 5.

In this way, the test pattern provided on the wafer can be used to easily collect the knowledge for investigating the manufacturing process in which the abnormality has occurred. It can be carried out accurately, and the yield of ultrafine semiconductor products can be improved at an early stage and maintained at a high level.

FIG. 6 is a diagram of a test pattern on a wafer showing another embodiment of the present invention. In the present embodiment, the data collecting device 2 shown in FIG.
Types of equipment are used. That is, a measurement device generally called a semiconductor parameter tester is used for the conventionally used test pattern for electrical measurement. On the other hand, an electron microscope apparatus is used for the three-dimensional processing state measurement / intra-observation test pattern, which is a feature of this embodiment. Further, the storage device 3, the processing device 4, and the like are realized by one computer system including an external memory, an input / output device, and the like.

Conceptually, a semiconductor product can be understood as being manufactured by stacking various layers. Therefore, even if the manufacture of the wafer is completed and it is determined that the wafer is defective, it is not easy to check the quality of the three-dimensional processing state in the intermediate process. The three-dimensional processing state in the intermediate process can be realized by performing a sampling inspection in the intermediate process of the wafer process. However, in a mass production line, it is impossible to perform 100% inspection due to the large amount of production. Therefore, for a product that has been found to be defective, what is the state of the three-dimensional processing in each step during the wafer process? This is achieved by manufacturing a test pattern on the wafer at the same time as the product pellets, which enables measurement and observation of hot spots. Such a test pattern is
It can be created by the same method as the conventional test pattern for electrical measurement. That is, the mask pattern may be designed so that a new layer is not formed in the process subsequent to the process of interest with the test pattern.

The test pattern of this embodiment is different from the conventional one in that a pattern for an electron microscope is provided, and this point will be described in more detail.

As the test pattern, basically any test pattern suitable for the purpose of analysis may be adopted. In this embodiment, a test pattern for observing the three-dimensional processing state in the etching process is taken as an example, and a specific pattern and its utilization method will be described. To observe the three-dimensional processing state of the etching process, for example, the test pattern shown in FIG. 6 is created. FIG. 6 conceptually shows an example in which a test pattern on a wafer is observed obliquely from above with an electron microscope.
With this, it is possible to see the taper angle of the etching cut surface, the influence of the standing wave during exposure, and the like. Creating such a test pattern on a dedicated wafer has been conventionally utilized for process development of individual steps. However, this has not been carried out on the product wafer at the same time as the product pellet, and this point is the feature of this embodiment.

FIG. 7 is a layout of the test pattern on the wafer according to this embodiment, and FIG. 8 is a layout of the test pattern on the reticle.

The test pattern 7 is installed beside each pellet 6 as shown in FIG. Recently, with the miniaturization of mask patterns, there are many reduction exposure methods. Therefore, if the test pattern 7 is put on the reticle 8 as shown in FIG.
A test pattern can be automatically created on the entire surface of the wafer. FIG. 8 shows an example of test pattern arrangement in the case of the reticle 8 having two patterns.

As described above, in this embodiment, the test pattern can be formed on the product wafer without changing the wafer manufacturing process from the conventional one. Further, the process abnormality inspection can be easily performed by using the inspection data of these test patterns. This makes it possible to grasp and analyze (a) various parameter values for abnormality diagnosis and distributions within a wafer regarding three-dimensional processing states, inter-wafer variations, and their time-series changes. Therefore, not only the anomaly analysis at the time of analysis,
Prediction of abnormal occurrence is also possible. (B) It has advantages such as an early improvement in yield in semiconductor manufacturing and the ability to maintain a high level, which accelerates the development of ultrafine semiconductor products after the submicron process.

〔The invention's effect〕

As described above, according to the present invention, it is possible to easily collect the abnormality diagnosis knowledge based on the abnormality occurrence state of the device parameter value of the product pellet, and without using much time and labor by using this. It is possible to detect abnormalities in the structure of semiconductor products and diagnose abnormalities in the manufacturing process. Further, since the test pattern can be formed on the product wafer without changing the manufacturing process, the process can be easily diagnosed.

[Brief description of drawings]

FIG. 1 is a block diagram of an abnormality diagnosing apparatus for a semiconductor manufacturing process showing an embodiment of the present invention, FIG. 2 is a diagram showing a test pattern on a wafer in the present invention, and FIG. 3 is a diagram showing device parameter values from measured data. Processing flow chart for estimating, FIG. 4 is a diagram showing FET device parameters, FIG. 5 is a diagram showing a storage format of diagnostic knowledge according to the present invention, and FIG. 6 is a wafer showing another embodiment of the present invention. FIG. 7 is a perspective view of the above test pattern, FIG. 7 is a layout diagram of the test pattern on the wafer,
FIG. 8 is a layout diagram of the test pattern on the reticle. 1: semiconductor manufacturing process, 1-1: manufacturing process, 1-2: inspection process, 2: data acquisition device, 3: storage device, 4: processing device, 5: display device, 6: pellet, 7: test pattern, 8: Reticle, 21, 22: DUT, 23, 24, 23 ', 24': Measuring terminal (pad).

Claims (2)

[Claims] 1. A test pattern is provided on a semiconductor wafer to be a semiconductor product, inspection data of the test pattern is collected, and an element parameter value of the semiconductor wafer is estimated based on the inspection data. By comparing with the range, it is determined whether or not there is an abnormality in the element parameter,
A semiconductor process abnormality diagnosis method characterized in that a known abnormality cause of the wafer is accepted, the abnormality cause and the above-mentioned abnormality occurrence state are paired and stored as diagnosis knowledge. 2. A test pattern for electrical measurement and a test pattern for measurement / observation by an electron microscope when the test pattern is formed simultaneously with a product pellet on a semiconductor wafer. The semiconductor process abnormality diagnosis method according to the first section.