JPH06101560B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, and particularly to a semiconductor device suitable for high speed operation.
The present invention relates to an MIS type semiconductor integrated circuit device.

[Conventional technology]

In the MIS type semiconductor integrated circuit device, the recent technical trend of speeding up is remarkable, and it is largely due to the thinning of the gate insulating film. Nowadays, MOS transistors using a silicon dioxide film of about 300Å as a gate insulating film are not uncommon, and as a result, the withstand voltage decreases,
Input protection technology is essential against static electricity and noise voltage.

FIG. 2 shows an example of a typical input protection circuit. The MOS transistor Q ₃ is a protected transistor, 201 is an input pad, and 202 is an input protection circuit section. The input protection circuit 202 is
It is often composed of resistance elements R ₁ and R ₂ and a clamp circuit 203. An example of using a MOS transistor Q ₄ as a clamp circuit is shown in FIG. As the MOS transistor Q ₄ , a silicon dioxide film having a thickness of several thousand Å is used as a gate insulating film, and a transistor having a threshold voltage of about 20 v is often used. In an actual MOSIC, it is common to use the field insulating film as the gate insulating film.

Normally, there is a time delay before the clamp circuit 203 or the MOS transistor Q ₄ starts operating, and when an abnormal voltage is applied to the input pads 201 and 301, the abnormal voltage is generated before the clamp circuit operates. Protected transistor
A resistance element R ₂ is inserted in order to prevent the gate electrode of Q ₃ and Q _{5 from} reaching and being destroyed. In addition, abnormal voltage, especially static electricity, is often a high voltage of several thousand volts or more, and when the clamp circuit operates, a large current flows instantaneously, destroying the clamp circuit and the contact opening of the input pad. Therefore, the resistance element R ₁ for current limiting is inserted.

These input protection circuits are often placed around the input pads to save the occupied area, and are standardized in terms of layout patterns from the viewpoint of stability of protection characteristics, etc.
It is common knowledge to arrange the same standardized pattern around each pad for each input pad.

[Problems to be solved by the invention]

However, as described above, in the input protection circuit, the resistance element is a necessary and indispensable element, and the arrangement of the input protection circuit around the pad as in the conventional case may not be preferable in terms of characteristics.

FIG. 4 shows a conventional layout example. 401 MOSIC chip, P is the input pad, the input protection circuit 402, 403 is aluminum wire, Q _6, Q ₇ shows the protected transistor. In this case, the same external signal is laid out at positions where the MOS transistors (protected transistors) Q ₆ and Q ₇ to be connected are separated from each other on the chip 401, and the aluminum wiring 403 is routed around the chip. However, this aluminum wiring 403 is
Has a large stray capacitance C _S. For example, MOS transistor Q
_While the gate capacitance of ₈ and Q ₇ is about 0.2 pF, the stray capacitance of aluminum wiring of about 6 mm reaches 2 to 4 pF. In addition, the resistance element of the input protection circuit is usually 1.0 kΩ to 2.0 kΩ, so it has a time constant of up to 8 ns.

This delay of the input section is very hindrance when trying to realize a response speed of 20 ns or less than 10 ns. Furthermore MOSIC
Functions are becoming more diverse, and the more complex the functions become, the larger the chip becomes, the longer the wiring length becomes, and one input signal is required for many functional circuit blocks. The tendency is getting stronger.

[Means for solving problems]

The semiconductor device of the present invention has a plurality of MIS field effect transistors whose gate electrodes are connected to the same input pad, and the MIS field effect transistors are divided for each MIS field effect transistor or the plurality of MIS field effect transistors are divided. An input protection circuit is provided for each small group.

〔Example〕

Next, the present invention will be described with reference to the drawings. FIG. 1 shows an example in which the present invention is applied to the conventional example shown in FIG. 101 is a MOSIC chip, 102 is an input protection circuit, and 103 is
Aluminum wiring, P is an input pad, and Q ₁ and Q ₂ are protected transistors, respectively. It is characterized in that input protection is arranged in each of the protected transistors Q ₁ and Q ₂ , and both are arranged in positions as close to each other as possible.

〔The invention's effect〕

As described above, the present invention can reduce the stray capacitance existing between the resistance element and the protected transistor included in the input protection circuit, and contributes to the high speed operation of the MOSIC.

For example, the gate capacitance of the protected transistor is 0.2 pF, the aluminum wiring capacitance is 0.1 pF or less, and the input protection resistance of 2 kΩ is 0.6 ns.
The time constant is as follows.

[Brief description of drawings]

FIG. 1 is a layout diagram of an embodiment of the present invention, FIG.
FIG. 3 shows a typical example of the input protection circuit, and FIG. 4 shows
It is a figure which shows the conventional layout example. 101, 401 are MOSIC chips, 102, 202, 402 are input protection circuit parts, 103, 403 are aluminum wirings, P is an input pad, Q ₁ , Q ₂ , Q ₃ , Q ₅ , Q ₆ , Q ₇ are protected transistors, R ₁ , R ₂ the resistance element, 203 is a clamp circuit, Q ₄ is a MOS transistor for clamping, 201 and 301 denotes an input pad, C _S is the stray capacitance of the aluminum wiring portions, respectively.

Claims (1)

[Claims] 1. A plurality of signal lines extending from the same input pad and supplying signals to gate electrodes of a plurality of MIS type electric field transistors at positions different from the positions of the input pads on a chip, and the plurality of signal lines. 2. A semiconductor device having a plurality of input protection circuits provided in the vicinity of the MIS type field effect transistor and between the end portion of the signal wiring and the gate electrode of the MIS type field effect transistor.