JPH06101677B2 - Timer-circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a timer circuit capable of arbitrarily setting a timer time.

[Outline of Invention]

The present invention relates to a timer circuit in which a timer time can be arbitrarily set, a constant current circuit that is voltage-controlled by a phase synchronization circuit and outputs a constant current at all times, and a voltage control of the phase synchronization circuit that is charged by the constant current circuit. -Type oscillator that uses a capacitor formed by the same manufacturing method as that of the delay element to detect the charging time, so that fluctuations in the timer time due to manufacturing variations and temperature changes are sufficiently reduced. Is.

[Conventional technology]

As a conventional timer circuit, a configuration as shown in FIG. 4 is known. When the voltage level of the trigger input terminal 14 becomes 1/3 or less of the power supply voltage, the output of the comparator 10 becomes High.
Then, the RS flip-flop 11 is set and the output becomes Low level. Therefore, the discharging transistor 8 is turned off, and the capacitor Ce is charged according to the time constants of Re and Ce. When the charge level exceeds 2/3 of the power supply voltage, the output of the comparator 9 becomes High level, the flip-flop 11 is reset, its Q output becomes High level, and the discharging transistor 8 is turned on. As a result, the electric charge charged in the comparator Ce is rapidly discharged, and the state of waiting for the trigger input is again obtained.

The trigger input is applied as described above, and the capacitor Ce
The time until the charging voltage of exceeds 2/3 of the power supply voltage is the timer time, and this time can be set by the capacitor ce and the resistance Re.

[Problems to be solved by the invention]

However, the conventional timer circuit has a capacitor Ce and a resistor Re.
If there is a variation in the value, an error will occur in the timer time,
It is necessary to suppress variations in the values of Ce and Re sufficiently. However, when manufacturing Ce and Re on a semiconductor integrated circuit, it is very difficult to suppress this variation, and when high timer time accuracy is required, the timer circuit cannot be integrated using the conventional method. . Therefore, Ce and Re are externally attached to the integrated circuit to meet the demand for high accuracy, but in this case, there is a problem in that it is disadvantageous in terms of board mounting.

Therefore, the present invention solves such a problem, and an object thereof is to provide a timer circuit which is highly accurate and can be easily integrated into an integrated circuit.

[Means for solving problems]

The timer circuit of the present invention comprises, firstly, a first constant current circuit for controlling a current value by a control voltage and a plurality of stages of inverters, and oscillates based on the current value controlled by the first constant current circuit. A voltage-controlled oscillator equipped with a ring oscillator that compares the phase of a reference clock signal with the phase of a signal obtained based on the oscillation of the voltage-controlled oscillator, and a phase comparator that outputs an output signal based on the comparison result. A low-pass filter that outputs the control voltage based on the output signal of the phase comparator, and constitutes a phase locked loop circuit together with the voltage-controlled oscillator and the phase comparator, and has the same configuration as the first constant current circuit. And a second constant current circuit whose current value is controlled by the control voltage, and a capacitor which is a delay element in the ring oscillator are formed by the same manufacturing method. And a timer time setting capacitor charged by a current value controlled by the second constant current circuit, and the timer time setting capacitor by the second constant current circuit in response to the input of a trigger signal. A signal for starting the timer measurement and the timer measurement start signal is output, and when the charge level of the timer time setting capacitor reaches a predetermined value, the timer time setting capacitor starts discharging and the timer measurement end signal is output. Secondly, the measurement control circuit outputs a first detection signal when the trigger signal is detected, and the timer time. A second detection circuit that outputs a second detection signal when detecting that the charging level of the setting capacitor has reached a predetermined value; Charging of the timer time setting capacitor is started in response to the output of the first detection signal, and discharging of the timer time setting capacitor is started in response to the output of the second detection signal. And a charging / discharging control circuit for controlling the charging / discharging.

〔Example〕

FIG. 1 is a block diagram of a timer circuit according to the present invention, in which 2 is a phase comparator, 3 is a low pass filter (hereinafter referred to as LPF), 4 is a constant current circuit using a current mirror circuit, and 6 is a ring oscillator circuit. Yes, the circuits 4 and 6 constitute a voltage-controlled oscillator (hereinafter referred to as VCO), and each of the circuits described above constitutes a phase-locked circuit (hereinafter referred to as PLL) that receives a clock of frequency ₀ as an input. .

The above PLL always keeps the VCO output frequency _VCO at _VCO = ₀ after synchronizing with the input clock. At this time, in the current mirror circuit 4 composed of the transistors Q ₁ , Q ₂ , and Q ₃ , a current first flows through the transistor Q _{0 due} to the LPF output voltage V _CNT , and a current I ₀ flows through the transistors Q ₁ , Q _3.
And is converted into a current I ₁ flowing in the transistor Q ₂ . Naturally, I ₀ = I ₁ .

The ring oscillator circuit is composed of an odd number of stages of inverter circuits, and has exactly the same current source as the current source having the current outputs of I ₀ and I ₁ on the source side of each stage inverter circuit. The oscillation frequency of the load capacity is determined by the stability when the load capacity is charged and discharged by the current source, and the charge and discharge are repeated to cause oscillation. FIG. 1 shows an example of a three-stage ring oscillator circuit, in which transistors Q ₄ , Q ₅ , Q ₆ and Q ₇ , Q ₈ , Q ₉ form a current source.

FIG. 2 is a model of the basic components of each stage of the ring oscillator circuit. The capacitor C0 is a load capacity determined by the gate capacity of each stage inverter circuit, and is a delay element of the ring oscillator circuit that is charged by the current I ₁ and discharged by I ₀ . SW1 and SW2 are models of P-type transistors and N-type transistors of the inverter circuit, respectively. The charging time or discharging time t ₀ at this time is given by setting the circuit threshold of each stage inverter circuit to 1/2 of the power supply voltage V _DD , Is represented. Here, I = I ₀ = I ₁ .

On the other hand, the oscillation frequency _VCO when the ring oscillator circuit is configured in N stages is calculated by using the above t _0. Can be expressed as Frequency ₀ as shown in Fig. 1
In a PLL that uses the clock of as input, if ₀ is stable, the _VCO that follows it is also stable. Therefore, from equation (3,2), t ₀ is stable and I is the same. Even this variation in transistor characteristics caused by manufacturing variations and temperature changes etc., t ₀ as _long as ₀ is stabilized is stable, C
Regarding the current I that charges or discharges o, it means that the LPF output voltage V _CNT is corrected so that it is always constant.

When this V _CNT is used as an input and the current mirror circuit 5 that is exactly the same as the PLL section is configured, a constant current I ₂ having the same current value as I ₀ is output to the transistor 7. When a trigger input is applied to the comparator 10, the output level of the comparator 10 becomes High level when the input level falls below the reference voltage V _CP2 which allows the division ratio of the resistors R ₁ , R ₂ and R ₃ to become RS level. The Q output of pull-up 11 becomes low level. As a result, the discharge transistor 8, OFF next capacitor Co 'is charged with a constant current I _2. Charge level is R ₁ ,
When the reference voltage V _cp1 exceeding the division ratio of R ₂ and R ₃ is exceeded, the output of the comparator 9 becomes High level, the output of the flip-flop 11 is reset to High level, the discharge transistor 8 becomes ON, and Co ′ becomes The charged electric charge is discharged.

A timing diagram showing this state is shown in FIG. At this time, the timer time t ₀ ′ is from idt = Co′Vcp ₁ Is represented. here, Then the above formula becomes Therefore, if Co ′ = Co, then I ₂ = I, so (3,
Equation 4) is the same as equation (3,1). Therefore, to 'also has a stable timer time width that depends only on the input frequency ₀ of the PLL.

Further, here, the capacitor Co ′ is manufactured by the same manufacturing method as the gate capacitor Co of the ring oscillator circuit, and the gate area is
When m times Co, there is a relationship of Co ′ = mCo, and of course the timer time to ′ becomes to ′ = mto, which can be set to an arbitrary time. Further, since the capacitors Co ′ and Co are manufactured by the same manufacturing method, it is considered that the rate of change in the capacitance value due to variations in the gate film is the same on the integrated circuit. Therefore, for example, even if the capacitance value of the capacitor Co changes, the LPF output voltage V _CNT is corrected by the tracking operation of the PLL, and the current source output I ₀ (= I ₁ ) changes by the change rate of Co. It is considered that the changing rate of the capacitor Co ′ is the same as the changing rate of Co, and naturally the current flowing through the transistor 7
Since I ₂ always changes while maintaining the relationship of I ₂ = I ₀ , the change in Co ′ is also canceled out, and to ′ maintains a constant value.

〔The invention's effect〕

As described above, according to the present invention, the current source corrected by the PLL function so that the output current is always constant, and the V
The ring oscillator circuit forming the CO is provided with a timer time setting capacitor formed by the same manufacturing method as the capacitor which becomes the delay element, and the timer time is detected by detecting the time when the timer time setting capacitor is charged by the current source. By setting, it is always stable and highly accurate against variations such as manufacturing variations and temperature changes.
Moreover, there is an effect that a timer circuit suitable for integration into an integrated circuit can be obtained. In particular, when a highly accurate timer circuit is required like a data separation integrated circuit used for a floppy disk or the like and a PLL is included, the timer circuit according to the present invention is extremely effective due to its configuration.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a timer circuit for an integrated circuit of the present invention.
FIG. 2 is a model diagram of a ring oscillator circuit of a timer circuit for an integrated circuit according to the present invention. FIG. 3 is a timing chart of FIG. FIG. 4 is a block diagram of a conventional timer circuit. 1 …… Reference clock input terminal 2 …… Phase comparator 3 …… Low-pass filter 4,5 …… Current mirror circuit 6 …… Ring oscillator circuit 7 …… Constant current source transistor 8 …… Discharge transistor 9,10… … Voltage comparator circuit 11 …… RS flip-flop circuit 12 …… Inverter circuit 13 …… Timer output terminal 14 …… Trigger input terminal 15 …… Capacitor Co ′ terminal voltage

Claims (2)

[Claims] 1. A first constant current circuit for controlling a current value by a control voltage, comprising a plurality of stages of inverters,
The voltage-controlled oscillator equipped with a ring oscillator that oscillates based on the current value controlled by the constant-current circuit, and the phase of the reference clock signal and the phase of the signal obtained based on the oscillation of the voltage-controlled oscillator are compared. A phase comparator that outputs an output signal based on the comparison result, and a low-pass filter that outputs the control voltage based on the output signal of the phase comparator and configures a phase locked loop with the voltage controlled oscillator and the phase comparator. And a second constant current circuit having the same configuration as the first constant current circuit, the current value of which is controlled by the control voltage, and a method of manufacturing the same capacitor as the delay element in the ring oscillator. The timer time setting capacitor, which is charged by the current value controlled by the second constant current circuit, and the trigger signal are input. Then, a signal for starting charging of the timer time setting capacitor by the second constant current circuit and outputting a timer measurement is output, and when the charge level of the timer time setting capacitor reaches a predetermined value, the timer is set. And a measurement control circuit for starting the discharge of the time setting capacitor and outputting a signal for ending the timer measurement. 2. The measurement control circuit outputs a first detection signal when the trigger signal is detected, and a charge level of the timer time setting capacitor reaches a predetermined value. A second detection circuit that outputs a second detection signal when it is detected, and charging of the timer time setting capacitor is started in response to the output of the first detection signal, and the second detection circuit is started. 2. A timer circuit according to claim 1, further comprising: a charge / discharge control circuit for starting discharge of the timer time setting capacitor in response to the output of the detection signal.