JPH06101720B2 - Vehicle communication device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a vehicular communication device that improves reliability of data transmission.

(Prior Art) As a conventional multiplex communication device for a vehicle of this type, for example, there is one shown in FIG. 8 (see USP No. 4370561).

In FIG. 8, 10 is a vehicle power supply, 20 is a circuit protector, 30 is a power supply line, 40 is a multiplexing and synchronizing device, 50 is a communication line, 60 is a transmitting device, and 70 is a receiving device. The synchronizer 40 includes an oscillator 41 that constantly oscillates pulses as shown in FIG. 9A, a synchronous waveform generation circuit 42 including a counter and a logic gate, and a 3-state output based on the circuit 42. Driver 43
, And the waveform as shown in FIG. 9B is continuously transmitted to the communication line 50.

Here, 4000 shown in FIG. 9B is a master synchronization section (start marker), and the transmission / reception devices 60 and 70 detect the communication channel by counting the channel pulse 4001 (negative pulse) following this. (See FIG. 9D). Also, 4002 shown in FIG. 9B is a communication section following the above-mentioned channel pulse 4001, and in this section, the output of the synchronizer 40 is in a floating state. Further, when this communication section 4002 elapses, the "Hi" level is output again, and the channel interval 4003 is generated.

The transmitter 60 includes an oscillator 61, a filter 62, and a transmission controller 6
3, a channel counter 64, a channel decoder 65, an AND circuit 66, a data selector 67 and a driver 68. The transmission controller 63 composed of a counter and a logic gate constantly monitors the voltage level appearing on the transmission line 50 through the input filter 62 and causes the oscillator 61 to oscillate for a predetermined time at the same time when the channel pulse 4001 is detected (Fig. 9C). ,
reference). Further, the transmission control device 63 causes the channel counter 64 to count the number of these channel pulses, detects the communication channel (see FIG. 9D), and simultaneously
4002 is detected and output during the section. Channel decoder
65 outputs when a predetermined channel corresponding to each of the data inputs 69 appears, and this output is input to the AND circuit 66 together with the output of the communication section 4002. The data selector 67 selectively connects the data input 69 and the output driver 68 only when there is an output from the AND circuit 66 corresponding to each of the data inputs 69,
The data (see FIG. 9E) is transmitted to the communication line 50.

On the other hand, the receiving device 70 includes an oscillator 71, a filter 72, a reception control device 73, a channel counter 74, a channel decoder 75, an AND circuit 76 and a latch circuit 77, of which 71 to 75 are the transmitting device 60. (61-65) is basically the same. However, the reception control device 73 does not output the data in the communication section (Fig.
Figure F4004) is output. Latch circuit 77
Latches the transmission data (E4002 in FIG. 9) appearing on the communication line 50 by the read pulse (E4004 in FIG. 9) when a predetermined channel corresponding to each appears. The channel counters 64 and 74 are start markers (see FIG. 9B).
4000) is detected and reset by the transmission control device 63 and the reception control device 73.

As described above, communication data can be sent out via a plurality of communication channels configured on the same communication line 50.

(Problems to be solved by the present invention) However, in such a conventional multiplex communication device, since the communication channel section is sequentially counted and the received data is also sequentially latched and output, the communication line is connected to the communication line. If a momentary interruption or a short circuit (slight short) occurs, a channel pulse will occur during the start marker or during the channel interval, or the original negative pulse will be missing, so the channel counter will be erroneously counted and counted. The erroneous data remains latched until the next start marker and the subsequent channel section are restored to normal. Such erroneous transmission causes a problem in that the output (load) of the device malfunctions.

(Means for Solving Problems) The present invention has been made in view of such problems in the related art, and sets a secondary latch circuit for final output and sets the number of channel pulses between start markers. Is set to a predetermined number, and the data in the primary latch is written to the secondary latch circuit only when the number of channel pulses is a predetermined value to prevent erroneous transmission. It is an object of the present invention to provide a communication device capable of reliable and accurate data transmission.

In order to achieve this object, the present invention provides a communication line for performing data communication, a communication synchronization device for alternately generating a master synchronization section having a predetermined output waveform pattern and a channel section continuous thereto. A transmitter for supplying communication data corresponding to an external input to the signal line by designating the channel section by sequentially counting a predetermined number of synchronization clock pulses successively generated in the master synchronization section, In a vehicle communication device including a receiving device that receives and latches communication data when the channel section is designated from a signal line, in the receiving device, the number of synchronization clock pulses is counted and counted. A pulse number check circuit for determining whether or not the number of synchronous clock pulses matches the predetermined value, and when they match,
A latch circuit that outputs the communication data received in synchronization with the clock pulse, discards the communication data when they do not match, and holds and outputs the previous communication data is provided.

(Operation) In the present invention having such a configuration, when the number of synchronization clock pulses does not match the predetermined value, it is determined that the communication line is momentarily cut or short-circuited and an erroneous counting is performed, Since the erroneous data received in synchronization with the pulse is rejected, reliable and accurate data transmission can be performed. As a result, the reliability of the device can be further enhanced.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

1 and 2 are views showing a first embodiment of the present invention.

FIG. 1 shows a circuit block diagram of the receiving apparatus of the present invention, and the description of the same parts as those of the conventional example will be omitted.

First, the configuration will be described. In FIG. 1, reference numeral 78 is a pulse number check circuit, and a reset signal is directly input from the reception control circuit 73 to the pulse number check circuit 78.
The pulse number check circuit 78 is the channel counter at this time.
The output value n of 74 is read, and it is determined whether the value n at the time of reading is equal to a preset number N of channel pulses. The pulse number check circuit 78 outputs a reset signal to the channel counter 74 after the determination, and also outputs a latch pulse to the enable terminal E of the secondary latch circuit 79 according to the determination result. The secondary latch circuit 79 is connected to the next stage of the primary latch circuit 77, and the output from the Q terminal of the primary latch circuit 77 is input to the D input terminal of the secondary latch circuit 79.

Next, the operation will be described with reference to the flowchart of FIG.

First, when the value n of the channel counter 74 matches the predetermined value N set in advance in S1 (n = N), a latch pulse is output to the enable terminal E of the secondary latch circuit 78 in S2, and 1
The data of the next latch circuit 77 is latched. Next, in S3, the channel counter 74 is reset and returns to the standby state.

On the other hand, when the value n of the channel counter 74 does not match the predetermined value N in S1 (n = N), it is determined that the communication line 50 may be momentarily disconnected or short-circuited, and the primary latch circuit is determined. The data of 77 is not transferred to the secondary latch circuit 79 (secondary latch circuit 79
Holds the old data), resets the channel counter 74 in S3, and returns to the standby state.

In this way, if a momentary interruption or short circuit occurs, a channel pulse will occur during the start marker or channel interval, or the original negative pulse will be missing, causing the channel counter 74 to count incorrectly and erroneous data to be received. However, even in such a case, since the erroneous data can be rejected in this embodiment, reliable and accurate data transmission becomes possible. As a result, the reliability of the device can be further enhanced.

Next, FIGS. 3 and 4 are diagrams showing a second embodiment of the present invention.

This embodiment is an example in which the output of the secondary latch circuit 79 is reset to provide a fail-safe function when abnormal reception continues twice or more.

FIG. 3 shows a circuit block diagram of this embodiment. In this embodiment, the pulse number check circuit 78 also has a function as an abnormal reception number counter F that counts the number of times when the value n of the channel counter 74 does not match the predetermined N, and the count number F ≧ 2. At this time, a reset pulse is output to the reset terminal K of the second latch circuit 79. The other structure is the same as that of the above-mentioned embodiment, and the description thereof is omitted.

Next, the operation will be described.

When n = N in S11 (normal reception), the abnormal reception number counter F is cleared (S12), a latch pulse is output to the enable terminal E of the secondary latch circuit 79, and the primary latch circuit is output.
Latch 77 data (S13).

Next, the channel counter 74 is reset (S14) and returns to the standby state. When n ≠ N in S11 (abnormal reception), F is incremented (S15), and it is determined whether F is 2 or more (S16).

When F <2, the channel counter 74 is reset (S1
4) Return to the standby state.

On the other hand, when F ≧ 2, short breaks and short circuits frequently occur, it is determined that the communication state is bad, and a reset pulse is output to the reset terminal R of the secondary latch circuit 79 to reset the secondary latch circuit 79. (S17). Next, in step S14, the channel counter 74 is reset and returns to the standby state.

Needless to say, the number of counts F is not limited to F ≧ 2. Therefore, in this embodiment, when the reception abnormality is temporary (F <2), the previous data is held, and when the reception abnormality continues for a long time (F ≧ 2), for example, after the output reset, There is no problem that the load being driven is temporarily stopped or the output load is not stopped once being driven. As a result, the safety of the vehicle can be further enhanced.

Next, FIGS. 5 to 7 are views showing a third embodiment of the present invention.

This embodiment is an example in which an input signal input to a shift register is processed by using a chattering removal circuit, which enables reliable chattering removal and rapid data inversion.

In FIG. 5, 100 is an internal clock generator, 200 is an n-stage shift register, and 600 is a majority circuit. According to the internal clock generator 100, the shift register 200 sequentially reads the input signal IN, and the majority circuit 600 shifts the shift register 2
Compare the number of logic "0" and logic "1" values in each stage of 00,
The larger value is output as the fixed value.

Next, a method of forming the internal circuit of the majority circuit 600 will be specifically described.

For the input waveform as shown in Fig. 7 (a), set the circuit power supply to V _DD.
Then, in the case of the cmos circuit, the level determination is performed at 1 / 2V _DD , so the value input to the shift register 200 shows a change as shown in FIG. 7 (b).

On the other hand, when the internal clock generator 100 generates a clock as shown in FIG. 7 (c) and performs the input latch and shift at the rise from the "L" level to the "H" level, the shift register 200 The value of the first stage b1 changes as shown in FIG. 7 (d).

Here, describing the output of the majority circuit 600 over time,
It becomes like Table 1. Therefore, when t = t10, the output "φ" is inverted to "1" and becomes the definite value.

Next, the majority decision circuit 600 for n = 3 will be described. The truth table is as shown in Table 2, and the output is OUT = ▲ ▼ b2b3 + b1 ▲ ▼ + b1b2 ▲ ▼ + b1b2b.
It becomes 3.

Here, b1b2b3 + b1b2b3 = b1b2b3.

Therefore, the output OUT is as follows.

OUT = ▲ ▼ b2b3 + b1 ▲ ▼ b3 + b1b2 ▲ ▼ ＋ b1b
2b3 + b1b2b3 = b1b2 (b3 + ▲ ▼) + b3 (▲ ▼ b2 + b1 ▲ ▼
+ B1b2) = b1b2 + b3 (▲ ▼ b2 + b1b2 + b1 ▲ ▼ + b1b2) = b1b2 + b3 (b2 + b1) Therefore, the majority circuit 600 of n = 3 becomes like the internal circuit of FIG.

When this circuit 600 is compared with the conventional circuit (when n = 2), when n = 2, as shown in Table 3, the output O from t = t11
UT is inverted from "φ" to "1" to become a fixed value, and this circuit 60
When 0, the response is faster by one internal clock cycle (= T).

In general, chattering has a property that the appearance frequency of "1" gradually increases from "φ" while repeating "φ" and "1". Therefore, the majority circuit 600 is extremely effective in eliminating chattering. Is.

As described above, in this embodiment, the numbers of “φ” and “1” of the values input to the shift register 200 are compared, and the one with the larger number is set as the definite value. And, quick data inversion is possible.

(Effects of the Invention) As described above, according to the present invention, the secondary latch circuit for final output is set to another stage, and whether the number of channel pulses between start markers is a predetermined number or not. Since the circuit to be checked is set and the data of the primary latch is written to the secondary latch circuit only when the channel pulse has a predetermined value, the channel counter is erroneous when the communication line is momentarily disconnected or short-circuited. Count,
When erroneous data is received, these data can be reliably rejected, so that reliable and accurate data transfer can be performed.

Further, in another embodiment, when abnormal reception continues, the latch output is reset, so that the load being driven is not temporarily stopped or the output load is not stopped once it is driven. There are no problems and the safety of the vehicle can be sufficiently ensured.

Furthermore, since the chattering removal circuit is used in the other embodiments, reliable chattering removal and quick data inversion can be achieved.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a first embodiment of the present invention,
2 is a flow chart for explaining the operation, FIG. 3 is a circuit block diagram showing a second embodiment of the present invention, FIG. 4 is a flow chart for explaining the operation, and FIG.
6 and 6 are circuit block diagrams showing a third embodiment of the present invention, FIG. 7 is a timing chart thereof, FIG. 8 is a circuit block diagram showing a conventional example, and FIG. 9 is a timing chart thereof. 40 …… Synchronizer, 50 …… Communication line, 60 …… Transmitter, 70: Receiver, 78 …… Pulse number check circuit, 79 …… Second latch circuit.

Claims (2)

[Claims] Claim: What is claimed is: 1. A communication line for performing data communication, a communication synchronization device for alternately generating a master synchronization section having a predetermined output waveform pattern and a channel section continuous with the master synchronization section, and a communication synchronization apparatus continuous with the master synchronization section. By sequentially counting a predetermined number of synchronous clock pulses generated by the above, the transmitter for supplying the communication data corresponding to the external input to the signal line by sequentially counting the number of synchronization clock pulses, and the channel interval from the signal line. In a vehicular communication device comprising: a receiving device that receives communication data when specified and latches and outputs the same; in the receiving device, the number of synchronous clock pulses counted and counted is equal to the predetermined number. A pulse number check circuit that determines whether or not the values match,
When they match, the communication data received in synchronization with the pulse is output, and when they do not match, the communication data is rejected,
A vehicle communication device, comprising: a latch circuit that holds and outputs previous communication data. 2. The output according to claim 1, wherein the output of the latch circuit is reset when the number of the synchronous clock pulses does not continuously match a predetermined value. Vehicle communication device.