JPH06101725B2 - Signal multiplexing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention receives control information / address / data output from a microprocessor from a peripheral circuit of the microprocessor, converts the control information / address / data into a serial signal, and outputs the serial signal to a time division transmission line. The present invention relates to a signal multiplexing circuit for outputting.

[Conventional technology]

A conventional signal multiplexing circuit is a memory that stores each of control information, address, and data received and input from a microprocessor peripheral circuit, and takes out control information and data from these memories to form a serial signal for time-division transmission line. And a time-division transmission line control circuit for outputting. This will be described with reference to FIG.

FIG. 3 is a block diagram showing a conventional example. In FIG. 3, a control device 900 having a microprocessor 101 is connected and coupled to a controlled device 200 via a time division transmission line 300. The control device 900 has a microprocessor 101, a microprocessor peripheral circuit 102, a signal multiplexing circuit 903, and an external factor gate 104. The signal multiplexing circuit 903 has a control information memory 911, an address memory 912, a data memory 913, and a time division transmission line control circuit 914. When the microprocessor 101 controls the controlled device 200, control information is stored in the control information memory 911 via the microprocessor peripheral circuit 102.
At the same time, the address is written in the address memory 912 and the data is written in the data memory 913 at the same time. The time-division transmission line control circuit 914 is connected to each of the control information memory 911, the address memory 912, and the data memory 913 by a control lead for taking out control of the memory and an output lead for taking out information, and the predetermined information is stored in each memory. When is accumulated,
Control the control lead with each memory at the time allocated to each of the control information, address and data on the time division transmission line 300, take out the information sequentially from each output lead and convert it into a serial signal for time division transmission Output to path 300. Further, at a time not assigned to the control relationship on the time division transmission line 300, the time division transmission line control circuit 914 extracts the external factor information received and input by the external factor gate 104 from the output lead by controlling the control lead, and time division is performed. Output to the transmission path 300.

[Problems to be solved by the invention]

Since the conventional signal multiplexing circuit described above is configured to sequentially transmit the control information, address, and data received and input from the microprocessor from the individual memories, the transmission processing is performed three times for one data transmission. However, there is a problem that the processing time for controlling is increased.

Furthermore, the operation of the microprocessor and the operation of the time division transmission line are asynchronous, and when the microprocessor performs a write operation many times during one cycle of the time division transmission line,
Since the sending operation to the time-division transmission line and the writing operation of the microprocessor occur at the same time, the information is erroneous or the information is lost. Therefore, a conflict prevention circuit is required and the circuit becomes complicated. .

An object of the present invention is to provide a signal multiplexing circuit that solves the above problems.

[Means for solving problems]

The signal multiplexing circuit of the present invention comprises an input sequence output memory for sequentially storing control information, address and data input from a microprocessor through a peripheral circuit and outputting the storage sequence, and a control lead connected to the input sequence output memory. And a time-division transmission line control circuit for sequentially taking out the stored information from the control output lead and outputting it as a serial signal to the time-division transmission line.

〔Example〕

Next, the signal multiplexing circuit of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, the control device 100 is connected to the controlled device 200 by a time division transmission line 300, and the microprocessor 101 of the control device 100 controls the controlled device 200. The control device 100 includes a microprocessor 101, a microprocessor peripheral circuit 102, a signal multiplexing circuit 103, and an external factor gate 10.
4, the signal multiplexing circuit 103 has a write control circuit 111, a data selection circuit 112, an input sequence output memory 113, and a time division transmission line control circuit 114. The microprocessor 101 is connected to the write control circuit 111 via the microprocessor peripheral circuit 102, and is also connected to the data selection circuit 112 by reading addresses and data. Write control circuit 111
The respective outputs of the data selection circuit 112 and the data selection circuit 112 are connected to the control input and the data input of the input sequence output memory 113. The control output and data output of the input sequence output memory 113 are connected and coupled to the time division transmission line control circuit 114 by control leads and output leads, respectively.
Further, 4 is connected to the control lead and the output lead of the external factor gate 104 to receive the external factor information from the output lead by controlling the control lead at a predetermined allocation time. Further, the time division transmission line control circuit 114 exchanges the extracted information to a serial signal and outputs it to the time division transmission line 300.

Next, the operation function of the signal multiplexing circuit will be described with reference to FIG. 2 and FIG. FIG. 2 is a time chart showing an embodiment of the present invention. Microprocessor
Reference numeral 101 sends control information, address, and data via the microprocessor peripheral circuit 102 as if the controlled device 200 is directly connected to the microprocessor peripheral circuit 102.
Control information is sent to the write control circuit 111, and addresses and data are sent to the data selection circuit 112. As shown in FIG. 2, the write control circuit 111 generates an input forward output memory write pulse formed by two pulses, a second pulse and a fourth pulse, from a clock for a microprocessor and a control signal having a 4-pulse length of the clock. Output to the input order output memory 113. The first pulse is a pulse for writing the type and address contents of control information, and the second pulse is a pulse for writing data in the input sequence output memory 113, respectively. The data selection circuit 112 discriminates the type from the control information and discriminates the information and the address information into two types, that is, information and data information, which correspond to the control information address writing timing and the data writing timing. Send information. The two timings are obtained by dividing the control signal having a 4-pulse length into two, and correspond to the first pulse and the second pulse of the two pulses, respectively. In this way, the data is sequentially written in the input-order output memory together with the address / control information.

On the other hand, the time-division transmission line control circuit 114 uses the two-pulse length of the time-division transmission line clock as the output timing of the input sequence output memory and the output timing of the external factor gate to generate the input sequence output memory shift pulse for every two pulses. The time division transmission line control circuit 114 reads that the information is stored in the input sequence output memory 113 by the control read at the output timing of the input sequence output memory 113 on the time division transmission line 300, and takes out from the output lead. And transmits to the time division transmission line 300. Since the data transmission is divided into control information / address and data and sequentially transmitted, the aforementioned shift pulse is input to the control lead to sequentially replace the data in the input sequence output memory 113. The external factor gate 104 is the same as the conventional one.

In the above-mentioned embodiment, the write circuit for the input-order output memory is divided into the write control circuit and the data selection circuit and is shown and described. However, it may be a means for writing one data together with the address / control information into the input-order output memory. However, it is not limited to the above description.

〔The invention's effect〕

As described above, according to the present invention, by providing the input-order output memory between the microprocessor and the time-division transmission line, the microprocessor can transfer the control information, the address information, and the data information to the input-order output memory with one setting. Sequentially fetched from write input sequence output memory, so control processing time
There is an effect that it can be shortened to 1/3, and since the input-order output memory sequentially stores and sends at one place, synchronization between writing from the microprocessor and sending to the transmission line is not necessary and there is no conflict, therefore information There is an effect that the order is wrong and information is not lost.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the signal multiplexing circuit of the present invention, and FIG. 2 is a time chart of an embodiment of the present invention.
FIG. 3 is a block diagram showing a conventional example. 101 ... Microprocessor, 102 ... Microprocessor peripheral circuit, 103 ... Signal multiplexing circuit, 113 ... Input output memory, 114 ... Time division transmission line control circuit, 300 ... Time division transmission line.

Claims (1)

[Claims] 1. A signal multiplexing circuit for inputting control information / address / data from a microprocessor peripheral circuit, converting the control information / address / data into a serial signal, and outputting the serial signal to a time division transmission line, wherein the control information / address / data is stored in the order of input. An input-order output memory that outputs in storage order and a control lead that is coupled to the input-order output memory are controlled, and the information stored in the input-order output memory is sequentially taken out from the output lead and is output to the time division transmission line as a serial signal. A signal multiplexing circuit having a time division transmission line control circuit.