JPH06103335B2 - Circuit board inspection method - Google Patents
Circuit board inspection methodInfo
- Publication number
- JPH06103335B2 JPH06103335B2 JP63053365A JP5336588A JPH06103335B2 JP H06103335 B2 JPH06103335 B2 JP H06103335B2 JP 63053365 A JP63053365 A JP 63053365A JP 5336588 A JP5336588 A JP 5336588A JP H06103335 B2 JPH06103335 B2 JP H06103335B2
- Authority
- JP
- Japan
- Prior art keywords
- measurement
- circuit board
- signal
- board
- measured
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 13
- 238000007689 inspection Methods 0.000 title description 12
- 238000005259 measurement Methods 0.000 claims description 33
- 230000004044 response Effects 0.000 claims description 5
- 239000003990 capacitor Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000002950 deficient Effects 0.000 description 3
- 230000003252 repetitive effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002847 impedance measurement Methods 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、電子部品等が実装された回路基板の良否を
検査する回路基板検査方法に関するものである。Description: TECHNICAL FIELD The present invention relates to a circuit board inspection method for inspecting the quality of a circuit board on which electronic components and the like are mounted.
電子部品等が実装された回路基板の検査にインサーキッ
トテスタと称される回路基板検査装置が利用されるよう
になってきた。この種の装置は被検査回路基板個々の回
路内容によって種々の測定が実行できるように構成され
ており、その一般的な例が第5図に示されている。Circuit board inspection devices called in-circuit testers have come to be used for inspection of circuit boards on which electronic components and the like are mounted. This kind of device is constructed so that various measurements can be performed depending on the circuit contents of each circuit board to be inspected, and a general example thereof is shown in FIG.
すなわち、信号源1は例えば直流定電圧源(DC.V)2、
直流定電流源(DC.A)3、交流定電圧源(AC.V)4から
なり、スキャナ5を介して被検査回路基板(以下、「テ
スト基板」と言う。)6へ測定用信号を加え、その応答
信号がスキャナ7にて測定部8へ取り込むようになって
いる。測定部8は例えば直流電圧測定器(DC,Vメータ)
9、直流電流測定器(DC.Aメータ)10、LC測定器(L.C
メータ)11を備えており、基板上の部品種類によりソフ
トウェアでそれに適した測定ユニットを定め測定を行う
ようになっている。なお、測定系を切り換えるコントロ
ーラ12などが設けられている。That is, the signal source 1 is, for example, a DC constant voltage source (DC.V) 2,
It consists of a DC constant current source (DC.A) 3 and an AC constant voltage source (AC.V) 4, and sends a measurement signal to a circuit board under test (hereinafter referred to as “test board”) 6 via a scanner 5. In addition, the response signal is taken into the measuring unit 8 by the scanner 7. The measuring unit 8 is, for example, a DC voltage measuring device (DC, V meter)
9, DC current measuring device (DC.A meter) 10, LC measuring device (LC
It is equipped with a meter) 11, and a measuring unit suitable for it is determined by software according to the type of parts on the board to perform measurement. A controller 12 for switching the measurement system is provided.
この装置を利用した従来の測定方法についていくつかの
例を説明すると、第6図にはテスト基板6に装着された
IC素子とその電源回路が示されているが、一般には電圧
安定化用として図示のように比較的大容量の有極性コン
デンサCが接続されている。この場合、コンデンサの容
量を交流信号で測定しようとするとインピーダンスが低
く高速の測定ができないから例えば直流定電流源3を信
号源となし、定電流で一定時間充電したのちその端子間
電圧を測定する。更に所定時間充電して再び端子間電圧
を測定し、2つの電圧とその間の充電時間とから容量を
求めて良否判定を行う。なお、最初の充電開始直後定電
流源3の出力端子電圧を測定し、それがこの定電流源の
開放電圧に等しければコンデンサCは未実装、電圧測定
で2回目の電圧が上昇していなければ回路のブリッジと
判定する。Some examples of the conventional measuring method using this device will be described. In FIG.
Although an IC element and its power supply circuit are shown, a relatively large-capacity polar capacitor C is generally connected as shown for voltage stabilization. In this case, if an attempt is made to measure the capacitance of the capacitor with an AC signal, the impedance is low and high-speed measurement is not possible, so for example, the DC constant current source 3 is used as a signal source, and the terminal voltage is measured after charging with a constant current for a fixed time . Further, the battery is charged for a predetermined time, the terminal voltage is measured again, the capacity is obtained from the two voltages and the charging time between them, and the quality is judged. Note that the output terminal voltage of the constant current source 3 is measured immediately after the start of the first charge, and if it is equal to the open circuit voltage of this constant current source, the capacitor C is not mounted, and if the voltage measurement does not raise the voltage for the second time. Judge as a circuit bridge.
第7図に示されるような回路網においてコンデンサCの
容量を測定する場合には、例えば交流定電圧源4からダ
イオードD1,D2が動作しないような波高値約0.2V以下の
電圧を加え、L.Cメータ11にてその容量を測定する。抵
抗Rについても同様に波高値0.2V以下の電圧を加え、D
C.Aメータ10にて流れる電流を測定しその抵抗値を求め
る。ダイオードD1,D2については例えば直流定電流源3
から+方向と−方向の電流を流し、同定電流源3の出力
端子電圧をそれぞれDC.Vメータ9にて測定する。When measuring the capacitance of the capacitor C in the circuit network as shown in FIG. 7, for example, a voltage having a peak value of about 0.2 V or less is applied from the AC constant voltage source 4 so that the diodes D 1 and D 2 do not operate. , The capacity is measured by the LC meter 11. Similarly, apply a voltage with a peak value of 0.2 V or less to the resistor R
The current flowing through the CA meter 10 is measured and the resistance value is obtained. For the diodes D 1 and D 2 , for example, a DC constant current source 3
A current in the + direction and a current in the − direction is flown from and the output terminal voltage of the identification current source 3 is measured by the DC.V meter 9.
上記従来の検査方法によると、基板上の部品それぞれに
対応した測定方法が利用できるという利点がある。しか
しその反面、各種の信号源と測定器が必要となり装置が
大形化する。また、これらの機器は検査プログラムによ
り動作させるが、そのためには使用者側で部品個々の特
性等を熟知して検査プログラムを作成する必要があり、
プログラム作成者の技能によっては不良の検出力が異な
ることもある。なお、例えばガード処理(G)により他
の部品からの影響を減らす手法が併用されるが、この場
合スキャナ等がより大形化するとともにガード処理はい
わゆるカットアンドトライの要素が多く、検査プログラ
ムの作成に長時間かかるという欠点がある。According to the above-mentioned conventional inspection method, there is an advantage that a measurement method corresponding to each component on the board can be used. However, on the other hand, various types of signal sources and measuring instruments are required, and the size of the device becomes large. In addition, these devices are operated by an inspection program, but for that purpose, it is necessary for the user to create an inspection program by fully understanding the characteristics of each individual part.
Depending on the skill of the programmer, the defect detection power may differ. It should be noted that, for example, a method of reducing the influence from other parts is also used by the guard processing (G), but in this case, the scanner etc. becomes larger and the guard processing has many so-called cut-and-try elements. It has the drawback of taking a long time to create.
この発明は上記の事情に鑑みなされたもので、その目的
は、テスト基板上の測定対象とする部品、回路網等に例
えば信号源から周波数又はレベルの異なる複数の測定用
信号を加え、その応答信号に基づいてそれぞれ測定した
インピーダンスデータをあらかじめ同一条件で良品基板
を測定して得られた基準データと比較することにより、
判定のバラツキなどが無く、かつ簡単で、高度のプログ
ラム作成技能を特に必要としない回路基板検査方法を提
供することにある。The present invention has been made in view of the above circumstances, and an object thereof is to add a plurality of measurement signals having different frequencies or levels from, for example, a signal source to a measurement target component, a circuit network, etc. By comparing the impedance data measured on the basis of each signal with the reference data obtained by measuring the non-defective board under the same conditions in advance,
An object of the present invention is to provide a circuit board inspection method that does not have variations in judgment and is simple, and does not particularly require a high degree of programming skill.
この発明を実施するための装置が第1図に示されている
が、上記課題を解決するため例えば繰り返し同期が異な
る3種類のクロックパルスを送出可能とするクロック発
生器14cと、この送出パルスを所定数計数するカウンタ1
4bと、その計数データをそれぞれ所望レベルのアナログ
交流電圧に変換して出力するD/Aコンバータ14aとからな
る測定用信号源14を備えている。An apparatus for carrying out the present invention is shown in FIG. 1. In order to solve the above-mentioned problems, for example, a clock generator 14c capable of transmitting three types of clock pulses having different repetitive synchronizations, and the transmission pulse Counter 1 for counting a predetermined number
A measurement signal source 14 including a 4b and a D / A converter 14a that converts the count data into an analog AC voltage of a desired level and outputs the analog AC voltage is provided.
上記信号源14によると、測定信号として例えば所望レベ
ルで周波数が3種類の交流電圧が得られる。よってこれ
らの信号を測定対象回路網などに加えると、測定部18に
おいては信号の種類に対応した回路網全体としてのイン
ピーダンスが得られ、回路網を構成する部品個々を測定
しなくても基板の良否を検査することができる。According to the signal source 14, for example, an AC voltage having a desired level and three kinds of frequencies is obtained as a measurement signal. Therefore, when these signals are applied to the measurement target circuit network or the like, the impedance of the circuit network as a whole corresponding to the type of signal is obtained in the measuring unit 18, and the components of the circuit network are not required to be individually measured for the board. The quality can be inspected.
第1図を再び参照すると、例えば信号源14から発せされ
た所望そ測定用交流電圧はスキャナ15を介してテスト基
板16上のインピーダンスZxを有する部品又は回路網に加
えられ、その応答信号はスキャナ17を介して測定部18に
取り込まれ測定されるようになっている。この場合、信
号源14、テスト基板16、測定部18間の測定回路は基板16
に設けられた図示しない測定点に応じてスキャナ15,17
により切り換えられ、また、信号源14でも所定の測定用
信号が選択されるが、それらの動作は例えばコントロー
ラ19が測定部18内の検査プログラムに基づいて制御する
ようになっている。Referring again to FIG. 1, for example, the desired measuring AC voltage emitted from signal source 14 is applied via scanner 15 to a component or network having impedance Z x on test board 16 and the response signal is The measurement unit 18 is taken in through the scanner 17 and measured. In this case, the measurement circuit between the signal source 14, the test board 16, and the measurement unit 18 is the board 16
Depending on the measurement points (not shown)
The predetermined measurement signals are selected by the signal source 14, and their operations are controlled by the controller 19 based on the inspection program in the measuring unit 18, for example.
この実施例においては、上記信号源14から周波数の異な
る3つの測定用信号f1,f2,f3が発せられるようになっ
ている。各信号の周波数とレベルは第2図(イ)及び
(ロ)に示されるように2通りに設定されている。すな
わち、同図(イ)では周波数が例えばそれぞれ10kHz,1k
Hz,100Hzで各々約±0.2Vの同一レベルとされ、(ロ)で
はf1(10kHz)とf3(100Hz)が例えば約±0.2Vでf2(1k
Hz)は約±0.5Vとなっている。In this embodiment, the signal source 14 emits three measurement signals f 1 , f 2 and f 3 having different frequencies. The frequency and level of each signal are set in two ways as shown in FIGS. 2 (a) and 2 (b). That is, in the figure (a), the frequencies are, for example, 10 kHz and 1 k, respectively.
The same level of about ± 0.2V at Hz and 100Hz, respectively. In (b), f 1 (10kHz) and f 3 (100Hz) are, for example, about ± 0.2V at f 2 (1k
Hz) is about ± 0.5V.
これらの測定用信号を形成するため、クロック発生器14
cから例えば繰り返し周期の異なる3種類のクロックパ
ルスP1,P2,P3を発し、カウンタ14bに計数させるよう
になっている。カウンタ146の計数データはそれぞれD/A
コンバータ14aにてアナログ電圧に変換され、例えば図
示しないローパスフィルタ、増幅器等を経て上記信号f1
ないしf3が形成される。To generate these measurement signals, the clock generator 14
From c, for example, three types of clock pulses P 1 , P 2 and P 3 having different repetition periods are emitted and the counter 14b is caused to count. Count data of counter 146 is D / A
The signal f 1 is converted into an analog voltage by the converter 14a and is passed through, for example, a low-pass filter and an amplifier (not shown).
To f 3 are formed.
第3図を参照しながら補足説明をすると、クロック発生
器14cは例えば測定部18の親クロックを分周して繰り返
し同期1μsのパルスP1と、その1/10分周したり繰り返
し周期10μsのパルスP2、及び更に1/10分周したり繰り
返し周期100μsのパルスP3を形成し、コントローラ19
からの制御により例えばP1,P2,P3の順にそれぞれ100
個ずつ出力する。As a supplementary explanation with reference to FIG. 3, for example, the clock generator 14c divides the parent clock of the measuring unit 18 to generate a pulse P 1 of repetitive synchronization of 1 μs, and divides it by 1/10 or a repetition period of 10 μs. The pulse P 2 and the pulse P 3 which is further divided by 1/10 or has a repetition period of 100 μs are formed, and the controller 19
Control from 100 to 100 in the order of P 1 , P 2 and P 3 , respectively.
Output one by one.
カウンタ14bは例えばバイナリ8ビットアップダウンカ
ウンタとし、スタートは100カウントの位置、計数上,
下限値をそれぞれ125及び75とすると、上記3種のパル
スP1ないしP3を各々100個計数したときの時間は100μs,
1ms,10msとなる。よって、その計数データをD/Aコンバ
ータ14aにてアナログ電圧に変換すると、周波数10kHz,1
kHz,100Hzの三角波信号が得られる。これらを例えばロ
ーパスフィルタにて波形整形し、利得可変の増幅器を通
すと上記第2図に示す測定用信号f1ないしf3が得られ
る。The counter 14b is, for example, a binary 8-bit up / down counter, the start position is 100 count,
Assuming that the lower limit values are 125 and 75, the time required to count 100 of each of the above three types of pulses P 1 to P 3 is 100 μs,
It becomes 1ms and 10ms. Therefore, if the count data is converted into an analog voltage by the D / A converter 14a, the frequency of 10kHz, 1
A triangular wave signal of kHz and 100Hz can be obtained. The waveforms of these signals are shaped by, for example, a low-pass filter and passed through a variable gain amplifier to obtain the measurement signals f 1 to f 3 shown in FIG.
従来の検査方法においては一般に、例えば基板に装着さ
れた部品のL,C,Rの絶対値を測定して規格値などと比較
するようになっているから、測定用信号に交流を用いる
場合には測定誤差の原因となる波形ひずみを極めて小さ
くする必要がある。しかしこの実施例では上記したよう
に良品基板とテスト基板のインピーダンスを同一条件で
測定し比較するようになっているので、波形ひずみと測
定誤差とは直接的な関係が無いから簡単な波形整形で実
用上差し支えない。なお、上記カウンタ14bとクロック
発生器14cを例えばメモリに置き換えて第2図の信号に
対応する波形データを記憶させ、コントローラ19からの
番地信号にてそれらのデータをD/Aコンバータ14aに与え
るようにしてもよい。In the conventional inspection method, generally, for example, when the absolute values of L, C, and R of the components mounted on the board are measured and compared with the standard value, when an alternating current is used for the measurement signal, It is necessary to minimize the waveform distortion that causes measurement error. However, in this embodiment, since the impedances of the non-defective board and the test board are measured and compared under the same conditions as described above, there is no direct relationship between the waveform distortion and the measurement error, so simple waveform shaping is possible. There is no problem in practical use. The counter 14b and the clock generator 14c may be replaced with, for example, a memory to store the waveform data corresponding to the signals shown in FIG. 2, and the address signals from the controller 19 may be used to provide those data to the D / A converter 14a. You may
次に、上記第7図に示されるような並列部品で構成され
た回路網に対する検査方法の一例を説明すると、測定周
波数とインピーダンスの関係は例えば第4図に示される
ように抵抗に関しては周波数に関係無く一定で、周波数
が高くなるとコンデンサのインピーダンスは下がり、コ
イルのインピーダンスは上がる。ただし、同図の横軸、
縦軸はそれぞれ対数目盛にしてある。Next, an example of an inspection method for a circuit network composed of parallel components as shown in FIG. 7 will be described. The relationship between the measured frequency and the impedance is, for example, as shown in FIG. The impedance of the capacitor decreases and the impedance of the coil increases as the frequency increases, regardless of the constant. However, the horizontal axis of the figure,
The vertical axis is on a logarithmic scale.
ここで、第2図(イ)の信号を加えるとダイオードのカ
ットオフ電圧は約0.2〜0.4Vであるから作動せず、抵抗
とコンデンサの合成インピーダンスが測定できる。この
測定値が良品基板の測定データに対して所定の許容差、
例えば±3σ内にあれば良と判定する。抵抗とコイルの
合成インピーダンスも同様にして測定できる。なお、ダ
イオード等を含む回路のチェックには第2図(ロ)に示
す如く、f1,f2,f3の周波数を変えてL,C,R等の部品特
性を測定し、また、そのうちの一波、例えばf2を0.5Vの
信号とすることでダイオードの特性の判定も可能であ
る。Here, when the signal shown in FIG. 2 (a) is applied, the cutoff voltage of the diode is about 0.2 to 0.4 V, so that it does not operate and the combined impedance of the resistor and the capacitor can be measured. This measurement value has a predetermined tolerance with respect to the measurement data of the good board,
For example, if it is within ± 3σ, it is determined to be good. The combined impedance of the resistance and the coil can be measured in the same manner. Note that the check of a circuit including a diode or the like as shown in FIG. 2 (b), by changing the frequency of f 1, f 2, f 3 measured L, C, the part characteristics of R, etc., also, of which It is also possible to determine the characteristics of the diode by setting one wave of, for example, f 2 to be a signal of 0.5V.
以上、詳細に説明したように、この発明による回路基板
検査方法は例えば一つの信号源から周波数とレベルを可
変とする複数の測定用信号を発してテスト基板の同一測
定点に加え、その応答信号により測定した複数のインピ
ーダンスデータを同一条件で測定した良品基板のデータ
とそれぞれ比較してその良否を判定するようになってい
る。As described above in detail, in the circuit board inspection method according to the present invention, for example, a plurality of measurement signals whose frequency and level are variable are emitted from one signal source and added to the same measurement point on the test board, and its response signal is added. The plurality of impedance data measured by the above are respectively compared with the data of the non-defective substrate measured under the same condition, and the quality is judged.
したがって検査対象が並列部品からなる回路網などの場
合、部品個々の値を測定して規格値と比較する必要が無
いため使用者側の検査プログラム作成が容易になり、高
精度で基板検査を行うことができる。また、各種の信号
源や測定器を備える必要が無く、装置の簡素化とコスト
ダウンに大きく貢献することができる。Therefore, when the inspection target is a circuit network that consists of parallel components, it is not necessary to measure the individual component values and compare them with the standard values, making it easy for the user to create an inspection program and performing highly accurate board inspection. be able to. Further, it is not necessary to provide various signal sources and measuring instruments, which can greatly contribute to simplification of the device and cost reduction.
第1図ないし第4図はこの発明による回路基板検査方法
の実施例に係り、第1図はその装置構成の一例を示すブ
ロック線図、第2図は測定用信号の波形図、第3図は信
号源の内部動作説明図、第4図はインピーダンス測定例
の説明図、第5図は従来装置の構成を示すブロック線
図、第6図及び第7図は測定対象の一例を示す回路図で
ある。 図中、14は信号源、16は被検査回路基板、18は測定部、
Zxは測定対象回路のインピーダンスである。1 to 4 relate to an embodiment of a circuit board inspection method according to the present invention, FIG. 1 is a block diagram showing an example of the apparatus configuration, FIG. 2 is a waveform diagram of a measurement signal, and FIG. Is an explanatory diagram of the internal operation of the signal source, FIG. 4 is an explanatory diagram of an example of impedance measurement, FIG. 5 is a block diagram showing the configuration of a conventional device, and FIGS. 6 and 7 are circuit diagrams showing an example of a measurement target. Is. In the figure, 14 is a signal source, 16 is a circuit board to be inspected, 18 is a measuring section,
Z x is the impedance of the circuit under measurement.
Claims (1)
加えて得られる応答信号により測定部にて上記基板のイ
ンピーダンスを測定し、該測定データをあらかじめ良品
基板を測定して得られた基準データと比較して上記基板
の良否を判定する回路基板検査方法において、 上記信号源から上記被検査回路基板の同一測定点へ周波
数又はレベルの異なる複数の測定用信号を順に加え、そ
の応答信号により測定した複数のインピーダンスデータ
をそれぞれ基準データと比較することを特徴とする回路
基板検査方法。1. An impedance of the board is measured by a measuring section by a response signal obtained by adding a measurement signal to a circuit board to be inspected from a signal source, and the measurement data is obtained by measuring a good board in advance. In a circuit board inspecting method for judging the quality of the board by comparing with reference data, a plurality of measurement signals having different frequencies or levels are sequentially added from the signal source to the same measurement point of the circuit board to be inspected, and a response signal thereof A method for inspecting a circuit board, characterized in that a plurality of impedance data measured by the method are compared with respective reference data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63053365A JPH06103335B2 (en) | 1988-03-07 | 1988-03-07 | Circuit board inspection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63053365A JPH06103335B2 (en) | 1988-03-07 | 1988-03-07 | Circuit board inspection method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01227079A JPH01227079A (en) | 1989-09-11 |
| JPH06103335B2 true JPH06103335B2 (en) | 1994-12-14 |
Family
ID=12940783
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63053365A Expired - Fee Related JPH06103335B2 (en) | 1988-03-07 | 1988-03-07 | Circuit board inspection method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06103335B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001264398A (en) * | 1999-11-22 | 2001-09-26 | Fujitsu Ten Ltd | Inspection device and method for electronic component |
-
1988
- 1988-03-07 JP JP63053365A patent/JPH06103335B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01227079A (en) | 1989-09-11 |
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