JPH06103451B2 - Electronic circuit device - Google Patents

Description

Description: TECHNICAL FIELD [0001] The present invention relates to a method of configuring an electronic circuit device, and in particular, the same clock is phase-shifted in each circuit block of the electronic circuit device including a plurality of circuit blocks. The present invention relates to a circuit configuration for distributing without causing.

[Technical background of the invention and its problems]

In recent years, as electronic circuit devices have become larger and larger, the whole device is divided into several circuit blocks, and each circuit block is synchronized with a certain single clock to operate the entire device. It has become possible to be.

On the other hand, as semiconductor elements that make up electronic circuits have become faster and faster, the operating speed of electronic circuit devices has also become faster, and as a result, the frequency of clocks that synchronize the operation timing of electronic circuit devices has also become higher and The propagation delay when a signal propagates through the internal signal line cannot be ignored, and the shift of the distributed clock phase between circuit blocks has become a problem.

FIG. 4 shows a conventional example. For example, in an electronic circuit device configured by mounting semiconductor elements on a plurality of printed boards (boards), the wiring between the boards is several tens cm to several meters. An electric signal can travel only 30 cm per 1 second on the signal wiring,
A clock with a frequency exceeding several tens of MHz cannot suppress the phase shift. Therefore, at present, we are avoiding this problem in the direction of making electronic circuit devices small and high-density, but if we make them small and high-density, we have to consider a cooling method to release the heat generated by the element itself. Instead of using natural air cooling, there is no choice but to use more expensive cooling means such as forced air cooling that blows air with a fan, water cooling that circulates a liquid such as water by circulating a pipe. ing.

[Object of the Invention]

An object of the present invention is to improve the above-mentioned problems and to provide a means for distributing a clock having no phase shift to each circuit block of an electronic circuit device composed of a plurality of circuit blocks.

[Outline of Invention]

When distributing a clock signal to multiple circuit blocks, the signal line of the forward path that starts with the clock generator and transmits the signal while going through the circuit blocks one by one in order and starting from the clock generator The same clock signal is applied to two signal lines by using a signal line of a reverse path that transmits a signal while going around the same circuit block in a completely reverse order of the forward path while being almost along the signal line of the forward path. To distribute. As a result, each circuit block can receive both the signal that travels the far path and the signal that travels the near path of the paths that go around all the circuit blocks.

On the other hand, each circuit block has a variable frequency clock signal generator, which is adapted to generate a signal of approximately the same frequency as the clock distributed throughout. Further, it has two phase comparators for performing phase comparison, one of which has a phase difference between the clock signal given from the signal line of the forward path and the clock independently generated in each circuit block. On the other hand, the phase difference between the clock signal given from the signal line of the reverse path and the clock independently generated in each circuit block is compared. By controlling the variable frequency clock signal generator so that the sum of the phase differences of the two phase comparators is minimized by using the output signals of the respective comparators, the phase of the independently generated clock is The phase of the clock generated to distribute the signal to the circuit is delayed by exactly half the propagation delay time required for the signal to go through all the circuit blocks. All blocks have the same phase regardless of.

〔The invention's effect〕

According to the present invention, a clock signal is distributed to each circuit block of an electronic circuit device that is composed of a plurality of circuit blocks and that operates in synchronization with the same clock, without causing a phase shift between them. Therefore, without unnecessarily reducing the size and density of the device,
A large-scale and high-speed electronic circuit device can be constructed.

Example of Invention

An embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows an example in which the present invention is used and shows an electronic circuit device composed of six circuit blocks. One of the six circuit blocks (3 in FIG. 1) includes a circuit that generates a clock signal for distribution to the entire device, and the other five circuit blocks receive the clock signal and then deviate by a certain phase. A clock is generated in each circuit.

In the figure, from the circuit block 3 which is the source of the clock signal, a forward clock signal transmission path that goes around 1-3, 1-1, 1-2, 1-4, 1-5, and conversely 1- 5, 1-4, 1-2, 1-1, 1-
There are three reverse clock signal transmission paths, and the clock signal propagates on each path with a slight delay. Each circuit block has a variable frequency clock generator that supplies a clock signal to each block and a phase comparator that generates an error signal for adjusting the phase of the clock generator. And the clock signal in the block, and the signal on the backward signal transmission path and the clock signal in the block are compared in phase. The situation will be described with reference to FIG.

FIG. 2 shows the phase relationship of clock signals in the circuit blocks 1-1 and 1-5. First, the clock signal generated in the block 3 and distributed to the entire apparatus is as shown in FIG. 2 (a), and is transmitted on the forward signal transmission path and the backward signal transmission path with a slight delay. Circuit block
In 1-1, the signal traveling through the forward signal transmission path has a little less delay than the signal traveling through the reverse signal transmission path, as shown in FIG. 2 (b) and FIG. 2 (c), respectively. become. Since the clock generated in the circuit block 1-1 is controlled so that the sum of the phase shifts with respect to (b) and (c) is minimized, the phase in the middle between (b) and (c) is eventually reached. And becomes as shown in FIG. 2 (d). On the other hand, in the circuit block 1-5, the signal transmitted through the reverse signal transmission path has much less delay than the signal transmitted through the forward signal transmission path.
It becomes as shown in FIG. Since the clock generated in the circuit block 1-5 is controlled so that the sum of the phase shifts with respect to (e) and (f) is minimized, the phase that is just between (e) and (f) is eventually reached. And becomes as shown in FIG. 2 (g).

In this way, minimizing the sum of the phase shifts with respect to the signals transmitted on the forward signal transmission path and the backward signal transmission path is one circuit of the forward signal transmission path (or the backward signal transmission path). Since the phase delay is created until it reaches the intermediate position, the clocks of the same phase can be generated in the circuit block device regardless of the position. As can be seen from FIG. 2, the clock signal (d) generated in the circuit block 1-1 and the clock signal (g) generated in the circuit block 1-5 are in phase with each other.

The manner of creating the clock signal in each circuit block will be described with reference to FIG. In each block, a variable frequency clock generator (3-2) generates a frequency clock signal close to the clock distributed to the entire device (signal on 3-5). This clock signal is the phase comparator (3-1-1, 3-1-2)
The phase is compared with the clock (signal on 3-4-1 / 3-4-2) sent from each forward / reverse transmission path. The phase error signal with the forward path clock (signal on 3-6-1) and the phase error signal with the reverse path clock (signal on 3-6-2) are added by the adder (3-3). The error signal (3-7
The above signal) is supplied to the variable frequency clock generator to control the phase of the clock generated in the block.

The output of the phase comparator appears as a signal deviated from a certain output level in the + direction or one direction due to the advance / delay of the compared signal phases. Comparing the phases of the clocks sent from the forward / backward signal transmission paths and using the addition result of the outputs as the error signal is the middle of the two clock phases sent from the forward / reverse transmission path. Since the result of phase comparison with the clock signal of the phase is used as an error signal, the clock phase of the variable frequency clock generator is controlled to be in the middle of the two clock phases sent from the forward / reverse transfer paths. It is nothing but a thing.

Phase comparators and signal adders have been widely spread as integrated circuits. For example, an integrated circuit for a phase comparator manufactured by Toshiba
The TC5081P and CMOS4500 series 4568B can be used, and the signal adder can be used without problems if you select it from the popular operational amplifiers (op amps) considering speed and accuracy. As a variable frequency clock generator, 74124 of TTL74 series
Etc. can be used.

Although the description has been centered on the device having the board configuration, the scope of application of the present invention is not limited to the board, and the system in which the system such as VLSI is realized on a single chip, or the system is dispersed and installed in one building. It can be widely applied to such devices.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit block configuration example of a clock distribution system when the present invention is used, FIG. 2 is a diagram showing clock phase relationships when the present system is used, and FIG. FIG. 4 is a diagram showing a clock signal, and FIG. 4 is a diagram showing an example of a clock distribution system when the present invention is not used. In Fig. 1, 1-1 to 1-5 ... Circuit block 2-1 to 2-5 ... Portion including phase comparator, variable frequency clock generator, etc. 3 ... Clock for distributing to the entire device Circuit block including a clock generator for generation 4 ... Clock signal line for forward transmission path 5 ... Clock signal line for reverse transmission path

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Claims (1)

[Claims] 1. A system comprising a plurality of circuit blocks, and
In an electronic circuit device in which those circuit blocks operate in synchronization with the same clock, a clock generator for generating a clock signal to be distributed to each circuit block and a clock starting from the circuit block including the clock generator are required. A signal line of a forward path for transmitting a clock signal while sequentially going around the circuit blocks, and a reverse direction for starting from a circuit block including the clock generator and transmitting a clock signal while going around the circuit blocks in a reverse order to the forward path. A phase comparator provided in each of the circuit blocks and the signal line of the path for performing phase comparison, an adder for adding the comparison output signals of the two phase comparators, and a variable controlled by the output signal of the adder Equipped with a frequency clock signal generator,
The signal phase of the variable frequency clock signal generator is divided into a phase difference between a clock signal supplied from the signal line of the forward path and a clock signal supplied from the signal line of the reverse path. An electronic circuit device characterized by generating a clock signal to be supplied to each circuit block by controlling so that the sum of phase differences is minimized.