JPH06103474B2 - Buffer memory control system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a buffer memory (BS) for storing a copy of data on a main memory (MS) and a main memory address of data stored in the BS (BS). Directory to register MS address) (BA
The present invention relates to an information processing apparatus having A), and more particularly to a buffer storage control method for reducing the number of bits of an MS address (absolute address) registered in BAA.

[Conventional technology]

A conventional buffer storage control method will be described with reference to FIG. In Fig. 2, the BS adopts the set associative method. As a computer of this type, for example, HI
TAC M-180, M-200H and the like.

In FIG. 2, 201 is an address (logical address) given by the program, which is composed of 24 bits (numbering 08-31 is given from the leftmost bit), and a 16 MB logical (virtual) space can be accessed. Reference numeral 202 is a control circuit for obtaining the entry address of the address translation buffer (TLB) 203 from the logical address. TLB203 is a page (usually 4K bytes) that is the unit of replacement from virtual space to real memory MS
Is a buffer for accelerating the dynamic address translation mechanism (DAT) that calculates the address of relocation on the MS, and each entry has a logical address (08-15) and an absolute address corresponding to it one-to-one. (08-19) (this is called a page address) is stored. The logical address portion of the TLB 203 is input to the comparator 204 and compared with the logical address of 201. The output of the comparator 204 is input to the output of the TLB 203 and the gate 205 and gates the absolute address part (08-19) of the TLB 203.

On the other hand, BS209 is divided into a plurality of columns (128 in the example of FIG. 2), and each column is divided into a plurality of rows (8 in the example of FIG. 2). Correspondingly, MS is also divided into the same number of columns. That is, the data (block data) of an arbitrary block of the corresponding column on the MS is stored in each row (which is called a block) of a certain column on the BS 209. BAA2
06 is also divided into multiple columns and multiple rows similar to BS209, and when data (block data) is transferred from a column with MS to the same column of BS209, BS column address of the MS address (absolute address) The block data was written to the upper bits (08-19) of (20-26).
Register to the entry accessed in the relevant column and row of BS209.

Address within page (20-31) of logical address 201
Is invariant after address translation and prefix translation and is also an absolute address. The output of each row of BAA206 is
It is input to each comparator 207 for comparison with the gated output of the absolute address of the TLB 203. The output of each comparator 207 is input to the row encoder 208 and indicates the row of the BS 209 in which the block data is registered. If the corresponding address is not registered in any row of BAA 206, no row is accessed and a block transfer request to MS is issued.

[Problems to be solved by the invention]

The above-mentioned conventional technology does not consider the number of bits of the absolute address of the MS registered in the BAA, the real space is expanded, and the SC
As the absolute address accessed by P (system control program) increases, there is a problem that the number of bits of the absolute address registered in BAA must be increased. For example, in the configuration shown in Fig. 2, if the logical address is expanded from 24 bits to 31 bits to cope with the expansion of the user area and the virtual space is set to 2 GB and the real address is also set to 31 bits, the MS can access up to 2 GB. Although it is possible, it is necessary to add 7 bits to the absolute address registered in BAA. However, the memory elements required for BAA are often bipolar high-speed memory, and the speed of expansion of the degree of integration is lower than that of MOS. Therefore, it is very difficult to increase the capacity of 7 bits because of the physical restrictions.

An object of the present invention is to provide a buffer storage control method that can reduce an increase in the number of bits of an absolute address registered in BAA even if the real space is expanded.

[Means for solving problems]

The present invention focuses on the fact that the capacity of the memory element that can be actually mounted on the MS is less than that even if the real address becomes m bits and the maximum address 2m-1 can be accessed. When the address can be accessed with an absolute address of n bits and m> n, a means is provided for detecting that all the upper m−n bits of the absolute address m at BS access are “0”.

[Work]

Registering to the BAA registers the lower n bits only when the upper mn bits are all "0", and comparing the address in the BAA with the BS access address, the upper mn bits are all "0". "
It is determined that the predetermined data is stored in the BS only when the lower n bits are compared and matched at this time. If the upper mn bits are not all "0", an address exception is detected or a direct fetch request to the MS is issued and the address exception is detected in the MS.

〔Example〕

FIG. 1 shows a conceptual configuration of the method of the present invention in comparison with FIG. 101 indicates a logical address extended to 31 bits. Correspondingly, the absolute address stored in the TLB 102 is also expanded to 19 bits (01-19). The logical address part of the corresponding entry in the TLB 102 and the logical address of 101 are compared by the comparator 103 as in the case of FIG. On the other hand, the output of the high-order bits (3 bits of 01-03 in the example of FIG. 1) of the absolute address part of the corresponding entry of the TLB 102 is input to the non-zero detector 104 which determines whether all bits are 0, and the TLB 102
If all the upper bits of the absolute address existing in the corresponding entry are not 0, the address exception detection circuit 106 sends an address exception detection signal. The gate 105 gates the lower bits (04 to 19 in the example of FIG. 1) of the absolute address part of the corresponding entry in the TLB 102 when the comparator 103 matches and the non-zero detector 104 detects all zeros.

In the BAA107, among the 31 bits of the absolute address, the upper 3 bits (that is, in the example of FIG.
Since it is 6MB, the number of bits required to access the maximum absolute address, which is higher than 28 bits, is registered. The output of each row of the corresponding column of the BAA 107 is input to the comparator 108 and output from the gate 105.
It is compared to the corresponding bit in the absolute address in the TLB.
The comparison output of each comparator 108 is input to the encoder 109, and the row of BS 110 in which the block data is registered is encoded. In the case of FIG. 1, the rows of BS110 and BAA107 are 4
It is divided into one class (0 to 3) and has a logical address
Decoder 111 decodes bits 18-19 of 101 to indicate the corresponding class.

With the configuration shown in FIG. 1, the absolute address space up to the upper limit value of the MS capacity is transferred into the BS, and the address exception is detected for the absolute addresses higher than that.

Next, examples of the present invention will be described in detail.

FIG. 3 shows an overall block diagram of the information processing apparatus. MS30
1 is connected to a storage control device (hereinafter abbreviated as SC) 302 via a data bus 305, and the SC 302 is a buffer storage device (hereinafter abbreviated as BU) 303 and an arithmetic processing device (hereinafter abbreviated as EU) 303 via a data bus 307. It is connected to 304. The BU 303 is also connected to the EU 304 via the data bus 308. BU303 is T
It has LB403, BAA404 and BS422.

Fig. 4 shows the details of BU303. The output of a logical address register (hereinafter abbreviated as LAR) 401 is connected to its delay register (LARD) 402, address conversion buffer 403, and buffer address array (BAA) 404. LARD402
Output is divided into segment index (SX), page index (PX), and byte index (BX) fields and connected to the selector 405. Selector 405
Is connected to one input of an address conversion adder (TAA) 406. The other input of the TAA406 is a register (STO) 409 that stores the segment table origin, a register (STL) 410 that stores the segment table length, and a shifter that reads from the BS and shifts the output of the data register (TBR) 414. The output of 411 is connected. The output of TAA406 is
It is connected to the prefix conversion logic unit (PFX) 407.
The output of the prefix address register (PXR) 408 is also connected to the PFX407. The output of PFX407 is connected to LAR401 and absolute address storage register 0 (PAR0) 412.

When the logical address sent from EU304 is set in LAR401, TLB403 is accessed by the page address part (SX, PX field part) of LAR401, and the corresponding logical address is corresponded by the comparator 417 connected to TLB403. Compared to a bit. If they match, the latch (INTLB) 418 indicating that the absolute address corresponding to the logical address exists in the TLB 403 is set. If INTLB418 is not set, DAT is activated and TAA409 performs addition using the values of the STO409, SX field and PX field to obtain the real address. For more information on how this DAT works,
Since it deviates from the object of the present invention, its explanation is omitted here.

At the end of DAT, the output of TAA 406 is a real address and is input to prefix conversion logic unit (PFX) 407. Of the absolute addresses calculated by PFX407 and set in PARO412, the page address part is temporarily set in the absolute address delay register (PARO) 419, and then TLB40
It is written in the absolute address part (P) 416 of the corresponding entry of 3. At this time, the logical address before the address conversion is also written corresponding to the logical address part (L) 415 of the same column. As a result, the logical address exists in the TLB (hereinafter abbreviated as INTLB), so the INTLB latch 418 is set. At this time, when the non-zero detector (NZD) 420 connected to the output of the upper bit (01-03 in the embodiment) of the absolute address part (P) 416 detects that all the bits are not "0", the gated The output of 421 becomes active, and an address exception signal is sent to EU304. Absolute address part (P)
416 is an absolute address register 1 (PAR
1) Set to LARD419 via 413 and sent to SC302 as the address of the data transfer request.

In parallel with the access of the TLB 416, the column with BAA 404 is accessed by the in-page address (20-25 in the embodiment) of the LAR 401, and its multiple loads are read simultaneously. The number of bits of the absolute address stored in BAA404 is
The number of bits required to access the maximum address in the MS implementation by removing the upper bits (04-20 in the embodiment) is set. The absolute address read from the BAA404 is the comparator 42
One of the 5 inputs. The other input of the comparator 425 is either the absolute address (P) 416 of the TLB 403 or the output of the PARD 419 in which the absolute address after DAT is set via the selector. In INTLB, the former is selected, and in the other cases, the latter is selected, and the comparator 425 compares it with the output of the BAA 404.

Since the BS422 is accessed by an address including a logical address (18-19), a block in the same MS may be set in a different column of a certain row in the BS. Therefore, BS422 and BAA404 are divided into four classes (CLO-CL3) determined by logical addresses (18-19), and each row is composed of four classes as shown in FIG. The comparison by the comparator 425 is performed on the output for each class of each row.

Each output of the comparator 425 is a circuit (hereinafter abbreviated as INBS DETECT) for determining whether the address of the LAR401 is present in the BAA. 4
Connected to 23. As mentioned above, BS42 with the same logical address
In order to detect double registration to 2, the logical address (18-1
9) is input to INB DETECT 423. The INBS DETECT 423 determines whether or not it is INBS based on the output of the comparator 425 and the class number (uniquely determined by 18-19). For INBS,
The row number that is compared and matched (hereinafter abbreviated as HIT) is set in the register (POW) 426. The output of the ROW 426 is connected as the select signal of the selector 427 to which the output of each row of the BS 422 is connected. If not INBS (called NIBS),
Latch 425 is set.

In the case of NIBS in the conventional technology, the MS of data (called a block) including the double word to be accessed is unconditionally accessed.
Although the transfer transfer (referred to as block transfer) request from 201 to the BU 303 was issued to the SC 302, the output of the NIBS 425 is gated by the output of the NZD 420 at the gate 424 in this embodiment. That is, N
When ZD420 detects non-zero, block transfer request is not issued. In this case, if it is INTLB, an address exception is detected. Therefore, the part of the absolute address that exceeds the upper limit of the mounting capacity of MS301 becomes an address exception and is not registered in BS422. The part that does not exceed the upper limit is not blocked by the gate 424 even if it becomes NIBS, so block transfer is activated and BS422
A block is written to and the absolute address is registered in the corresponding column of BAA.

〔The invention's effect〕

According to the present invention, the number of bits of the absolute address registered in the BAA can be limited to the number of bits of the accessible address determined by the physical limitation of the MS, not by the real address space defined by the architecture. Therefore, it is possible to reduce the capacity (lateral capacity) of the memory element that realizes the BAA as compared with the conventional method. Also, as the number of bits in BAA is reduced, the amount of metal in the comparator that compares the output of BAA and the absolute address of TLB can be eliminated.

[Brief description of drawings]

FIG. 1 is a diagram showing a conceptual configuration of the present invention, FIG. 2 is a diagram for explaining a conventional technique, FIG. 3 is an overall block diagram of an information processing apparatus targeted by the present invention, and FIG. 4 is FIG. 3 is a detailed view of an embodiment of the buffer storage device in FIG. 102,403 …… Address translation buffer (TLB), 107,404…
… Buffer address array (BAA), 110,422 …… Buffer storage (BS), 104,420 …… Non-zero detector, 106,421,424
...... MS data transfer request circuit.

Claims (1)

[Claims] 1. A buffer memory for storing a copy of data on the main memory, a directory for registering a main memory address of the data stored in the buffer memory, and a physical access address of the main memory from a logical address ( Hereinafter, in an information processing device having an address conversion unit for obtaining an absolute address), m indicated by the absolute address obtained by the address conversion unit is shown.
Of the bits, a means for detecting all “0” s of the upper mn bits excluding the n bits (n <m) necessary for accessing the maximum absolute address determined by the physical implementation limitation of the main memory is provided. A buffer storage control method is provided, wherein when the mn bits are all "0", the lower n bits are used to register and refer to the main storage address of the directory.