JPH06103476B2 - Serialize instruction controller - Google Patents

Description

DETAILED DESCRIPTION [Outline] At least a buffer invalidation address is temporarily stored in a main memory unit (MSU), a plurality of central processing units (CPU) equipped with cache memories, and a system control unit (MCU). In a multi-processor system having a tag memory (TAG2) held in, the serialization request flag signal indicates the serialization request source identifier (RQTR ID) when the serialization process is activated and propagated to another central processing unit.
By providing a means for adding the following, the subsequent serialization process from another processing device is continuously activated while the preceding serialization request is being processed.

[Industrial application field]

The present invention includes at least a main memory unit (MSU), a plurality of central processing units (CPU) including cache memories,
The present invention relates to a serialization instruction control device in a multiprocessor system having a tag memory (TAG2) that temporarily holds a buffer invalidation address in a system control unit (MCU).

Conventionally, in a multiprocessor system equipped with a cache memory, serialization is performed to match the contents of the cache memory of each central processing unit (CPU) with the contents of the main memory (MSU). It has a command.

The serialize instruction is an instruction for serializing store access in each central processing unit (CPU), and has two types of pre-serialize and post-serialize.

The pre-serialize instruction is a store access of the central processing unit (CPU) before the instruction issuance, and the post-serialize instruction is a central processing unit before the instruction issuance including a store access activated at the same time as the instruction issuance ( The CPU has a function of interrupting store access and ending the invalidation processing of the cache memory in another central processing unit (CPU) in the system.

On the other hand, the central processing unit (CPU) has a built-in cache memory composed of a tag (TAG1) unit and a data unit for the purpose of speeding up the processing, and processing units other than the central processing unit (CPU) When the contents of the main memory (MSU) are rewritten, it is checked whether old data before being rewritten exists in the cache memory, and if it exists, the relevant part in the cache memory is checked. To invalidate.

This is called a buffer invalidation (BI) process, and its address is called a BI address. Normally, the BI address is temporarily held in the BI stack memory and is not immediately processed.

The serialize instruction propagates this BI address to all other processing units in the system, causes the processing unit that received it to temporarily suspend other processing, and instead places it in the BI stack. , The BI process of the unprocessed BI address is performed, and the contents of the cache memory of the processing device are
It works to match the contents of the main storage unit (MSU).

In the central processing unit (CPU) that has issued the serialization instruction, subsequent processing (store access) is restarted after it is confirmed that the instruction has been transmitted to all the other processing apparatuses in the system.

In such a serialization control method, as described above, the serialization instruction issuance serialization processing (BI
(Processing) Propagation of requests to other processing units Since this is the process of restarting subsequent store access, in a multiprocessor system, overlap processing is performed for serialization requests from multiple central processing units (CPUs). There is a need for an efficient serialization instruction control device that allows the.

[Problems to be solved by conventional technology and invention]

FIG. 3 is a diagram showing a configuration example of a conventional multiprocessor system, and FIG. 4 is a diagram showing a configuration example of an improved multiprocessor system.

First, in the multiprocessor system shown in FIG.
Each central processing unit (hereinafter, referred to as CPU) 3 itself is aware of an address for a main storage unit (hereinafter, referred to as MSU) 1 and is connected to an MSU1 to be accessed, which is a system control unit (hereinafter referred to as MCU). ) 2, the access is issued.

In this method, the address of the store access issued by a certain CPU3 is the MCU0 or MCU1 that received the store access.
From (2), all other CPUs 3 are notified. Each CPU3
This store address is held in a BI stack (not shown) provided in itself, and BI processing is sequentially executed.

In the multiprocessor system having such a configuration, there is a problem that the number of interface lines between the MCU0 or MCU1 (2) and all CPUs in the system increases. In particular, when the length of data to be processed is long, there is a problem that the increasing amount of hardware cannot be ignored.

Also, for one CPU3 (for example, CPU0),
BI address may be sent from CPU3 (for example, CPU1,2,3 ...), BI processing in CPU0 (3) may be congested, and there is a problem that processing capacity in each CPU3 is reduced. It was

Therefore, the system shown in FIG. 4 was considered as a multiprocessor system for improving these problems.

In the improved multiprocessor system, the MS
The MCU0 or MCU1 (2) that has received the U access request issues an access request to the corresponding MSU0, 1, 2, ... (1) through the inter-MCU interface.

Therefore, each MCU0,1 (2) corresponds to the access source CPU3,
It has a device (tag memory) that temporarily stores an address called TAG2, stores the fetch address from each CPU3, and if there is a store access from another CPU3, it compares it with the access address, When a match is detected, the match address is propagated to the CPU 3 in charge of itself as the BI address described above.

Each CPU 3 holds this BI address in its own BI stack, sequentially executes BI processing, and invalidates the corresponding entry in the cache memory.

Normally, the TAG2 has a register for temporarily holding other stages of registers and an address for speeding up the processing, but since it is not directly related to the present invention, its details will not be described here. Omit it.

In this improved multiprocessor system,
It takes some time for one store address to be transmitted to the entire system as a BI address (that is, registered in the BI stack of each CPU 3 through TAG2).

Therefore, when each CPU 3 issues a serialize instruction, it takes time to finish one serialize instruction as described above. Therefore, processing the serialize instructions without overlapping each other reduces the performance of the entire system. There was a problem of lowering.

On the other hand, when serializing instructions from each CPU 3 are processed so as to overlap each other, in TAG2 described above, a plurality of store access addresses are temporarily held.
There is a problem that the end of each serialize instruction is not guaranteed. Specifically, there was a problem that the serialization instruction issued by each CPU could not correspond to the BI address.

In view of the above-mentioned conventional drawbacks, the present invention adds an identifier (RQTR ID) indicating the issue destination of the serialization instruction at the time of starting and propagating the serialization instruction to overlap the serialization request from each central processing unit (CPU). A method that enables processing and prevents a decrease in processing speed by continuously activating and processing a subsequent serialization request from another processing device even while a preceding serialization request of a processing device is being processed. It is intended to be provided.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the serialize instruction control device of the present invention.

In the present invention, at least a plurality of main storage devices, a plurality of central processing units (CPU0,1,2, ...) 3 having cache memories, and a system control unit (MCU0,1) 2
In the multiprocessor system having the tag memory (TAG2) 21 for temporarily holding the buffer invalidation address in the system controller 2, the plurality of central processing units (CPU0, 1, 2, ...) 3 In order to process the serialization request from the device, an identifier (RQTR ID) indicating the requester of the serialization is added to the serialization request flag signal to another central processing unit 3 at the time of activation and propagation of the serialization. , When each TAG2 sends a serialization request flag by the SERIALIZE OUT signal to its own central processing unit 3, the serialization provided for each central processing unit (CPU0,1,2,3, ...) 3 The control circuit 22 is provided with means for feeding back the serialization request flag signal and the identifier (RQTR ID),
By this means, even during the serialization process from a certain central processing unit 3, subsequent serialization requests from other central processing units 3 are continuously activated, and each central processing unit (CPU0, 1, 2, ..) 3 recognizes the end of propagation of the serialization request issued by each of the serialization control circuits 22, and receives a new serialization request.

[Action]

That is, according to the present invention, at least the main memory (MS
U), multiple central processing units (CPU) with cache memory, and tag memory (TAG2) for temporarily holding buffer invalidation address in system control unit (MCU). By providing a means for adding an identifier (RQTR ID) indicating the serialization request source to the serialization request flag signal at the time of starting the processing and propagating to another processing device, during the processing of the preceding serialization request, Since the subsequent serialization process from another processing device is continuously activated, the overlapping serialization process can be performed between the processing devices, and the serialization instruction can be processed at high speed. is there.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 2 is a diagram showing one embodiment of the serialization control circuit of the present invention. The identifier (RQTR ID) input to TAG2 configured by the pipeline of FIG. 1 and the identifier ( The RQTR ID) feedback circuit is a necessary means for implementing the present invention. The same reference numerals indicate the same objects throughout the drawings.

The serialization instruction control device of the present invention will be described below with reference to FIGS. 1 and 2 while referring to the configuration of the improved multiprocessor system of FIG.

In the system shown in FIG. 4, the serialization control circuit 22 of FIGS. 1 and 2 exists in each MCU0, 1 (2) corresponding to the issuer device of the serialization instruction.

Here, ▲ ▼ is activated when the CPU0,1,2, ... (3) is not connected to the respective MCU0 or MCU1 (2), and forcibly resets the corresponding latches. Function to inhibit access to the latch.

First, for example, when the serialization request signal from the CPU0 (3) is accepted by the serialization control circuit 22 corresponding to the CPU0 (3), the latches a, b, and h are set, and the latch a (CPU0-SERIALIZE ) To priority circuit 23
To the local pipeline 24 via the serialization request flag indicating that the serialization request is activated, and, for example, an identifier (RQTR ID) indicating the issuer of the serialization request generated by encoding the serialization request flag signal. Is thrown in.

Needless to say, the identifier (RQTR ID) may be included in the serialization request signal from the beginning when the CPU0 (3) issues the serialization instruction. is there. In this case, the encoding mechanism is unnecessary.

The latch (INH-STORE-BY-SERIA) inhibits the activation of store access from the serialization request source CPU0 (3) in the priority circuit 23 during the serialization period. Until the end, CPU0 (3) store access is not started.

The interface signal from the MCU2 of the other system is input to the remote pipeline 25, and the fact that the CPU3 connected to the MCU2 of the other system has issued the serialization instruction propagates in the remote pipeline 25. It can be known from the serialization request flag signal and the identifier (RQTR ID).

TAG2 21 provided corresponding to each CPU 0, 1, 2, ... (3)
Takes in the necessary control signals, addresses, etc. from both the local and remote pipelines 24 and 25, and BI
Propagate the processing request as BI address.

A serialization request flag signal transmitted to the TAG222,
The identifier (RQTR ID) is input to a queue or the like (not shown) in the TAG2 21, and under the control of the TAG2 21, the serialization signal (SERIALIZE-OUT) signal corresponds to the CPU 0, 1, 2, ...
When sent to (3), at the same time, the serialization control circuit 22 whose details are shown in FIG.
Returned with ID).

Since the identifier (RQTR ID) is coded as described above, for example, it is decoded in the serialization control circuit 22 and operates to reset the corresponding latch of ha-e.

For example, the serialization instruction from CPU0 (3)
It is input to CPU1 TAG2 (21) other than AG2 (21), and from the CPU1 TAG2 (21), the serialization signal (CPU
1-TAG2-SERIALIZE-OUT) signal and identifier (RQTR ID) (C
When PU1-TAG2-RQTR-ID-CPU0) returns to the serialization control circuit 22 corresponding to CPU0 (3), the latch of C is reset under the condition of'P1 'shown in the figure.

In this way, when all the latches from ha to e are reset, the latches of b are reset next, which means that the serialize instruction is completed.

The serialized signal (SERI
The ALIZE-OUT) signal and the identifier (RQTR ID) are fed back to the serialization control circuit 22 throughout the system, but the identifier (RQTR ID) added by the present invention is a code indicating the issuer of the serialization instruction. Since this is information, only the corresponding latch existing in the serialization control circuit 22 corresponding to the access source CPU 3 indicated by the identifier (RQTR ID) is reset.

In this way, even if the preceding serialize instruction is being processed, the subsequent serialize instruction can be activated and overlapped, and the serialize instruction can be processed at high speed.

Thus, in the present invention, in a multiprocessor system, a serialization control circuit and a TAG2 are provided in the MCU in correspondence with each CPU, and a serialization request from a certain CPU is handled by the serialization control circuit corresponding to the CPU. When accepted, via all TAG2 other than TAG2 corresponding to self,
It is propagated to other CPUs, BI processing is performed in each CPU, and the serialized signal (SERI
ALIZE-OUT) and the identifier (RQTR ID) are fed back, and when the feedback signals from all the other TAG2 are received, it is recognized that the serialization processing has ended, and the next serialization command is accepted. , The feature is that the serialization process in multiple CPUs is made to overlap.

〔The invention's effect〕

As described above in detail, the serialization instruction control device of the present invention includes at least a main memory unit (MSU) and a plurality of central processing units (CPU) including cache memories.
Also, in a multiprocessor system having a tag memory (TAG2) that temporarily holds a buffer invalidation address in the system control unit (MCU), the serialization request flag is activated when the serialization process is activated and is propagated to another processing unit. By providing a means for adding an identifier (RQTR ID) indicating the source of the serialization request to the signal, during the processing of the preceding serialization request, the subsequent serialization processing from another processing device is continuously activated. Therefore, the serialization processing that overlaps between the processing devices can be performed, and the serialization instruction can be processed at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the serialize instruction control device of the present invention, FIG. 2 is a diagram showing an embodiment of the serialize control circuit of the present invention, and FIG. 3 is a configuration example of a conventional multiprocessor system. Figures 4 and 5 are diagrams showing an example of the configuration of the improved multiprocessor system. In the drawing, 1 is a main memory unit (MSU0,1,2, ...), 2 is a system control unit (MCU0,1), 3 is a central processing unit (CPU0,1,2, ...), 21 is a tag memory ( TAG2), 22 is a serialization control circuit, 23 is a priority circuit, 24 is a local pipeline, 25 is a remote pipeline, I to E are latches, P1 to P1 are reset conditions to latch, respectively.

Claims (1)

[Claims] 1. At least a plurality of main storage devices (1)
And a plurality of central processing units (3) having a cache memory, and a system control unit (2) for main memory access control. A buffer invalidation address is temporarily set in the system control unit (2). Tag memory to hold (TA
In a multiprocessor system having G2), in order to process the serialization request flag signals from the plurality of central processing units (3), activation of serialization processing and serialization instructions to other central processing units (3) are performed. At the time of propagation, an identifier (RQTR I
D) is added, and the identifier (RQTR ID) added by the adding means is used to recognize the propagation destination of the serialization instruction from a certain central processing unit (3), and another central processing unit A serialization instruction control device which continuously processes the subsequent serialization instruction from (3).