JPH06103594B2 - CMOS / DRAM with built-in divided bit line sense amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a divided bit line sensing type CMOS / DR.
To improve the operating characteristics and operating speed of AM,
Especially, CMOS / DR with divided bit line sense up which is suitable for manufacturing high density memory of 4M DRAM or more.
It is related to AM.

As the density of the DRAM becomes higher, the number of cells connected to the bit line is increased and the bit line is extended and the width between the bit lines is reduced. This leads to an increase in the resistance of the bit line and an increase in the capacitance, the margin width of the sensing signal is reduced, and the operation speed of the DRAM is reduced, such as a decrease in the sensing speed.

Therefore, in order to manufacture a high-density memory of 1 mega DRAM or more, it is necessary to solve the above-mentioned problems. Normally, the cell array is divided in the cell array and the sense amplifier configuration circuit, and each divided cell array is divided. A method of sensing the corresponding bit line for each cell array obtained by dividing each sense amplifier is used.

Such a split bit line sensing method is disclosed in Japanese Patent Application No. 87-8771 filed by the applicant of the present invention (name: CMOS / DR with a built-in split bit line sense amplifier).
AM) and application number 87-9401 (name: same as above).

In Korean Patent Application No. 87-9401, the cell array
It is divided into two, and the N-type latch sensing circuit and the P-type latch restore circuit are placed for each divided cell array. The capacitance between the bit lines is divided so that the bit lines are divided and sequentially sensed. Since the operating voltage margin and speed can be improved and the peak current can be minimized, 1M DRAM can be manufactured.

However, the above prior arts are only useful for making 1M DRAM, and when applied to make 4M DRAM or higher density DRAM, inoperability or error may occur. There is a problem that occurs.

For example, the read modify write cycle (Read-
During the Modify-Write Cycle), when the data modified by the I / O bus line has to modify the internal and external bit lines from the high level to the low level and from the low level to the high level through the isolation transistor, the first It takes, of course, much time to flip the second sense amplifier circuit and the second restore circuit after flipping the sense amplifier circuit and the first restore circuit and then passing through the transmission gate circuit. The margin has become very bad,
In some cases, the above-mentioned latch circuit cannot be flipped.

In particular, it is inevitable that the resistance of the bit line will become high in high-density memory of 4M DRAM or more, and the resistance value will be 10k.
If it is more than Ω, data correction writing is impossible.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a CMOS / DRAM having a divided bit line sense amplifier capable of manufacturing a high density memory of 4 mega DRAM or more in order to solve the problems of the conventional technology. Is.

In order to achieve the above object of the present invention, the present invention is a CM
In OS / DRAM, a row decoder, a column decoder, a pair of input / output bus lines, a pair of adjacent and parallel internal bit lines, a pair of adjacent and parallel external lines, and the above-mentioned pair of internal bit lines. And a pair of corresponding external bit lines in response to the separation clock for separating at a predetermined time during an active cycle, and a plurality of memory cells connected to the pair of internal bit lines. An internal cell array for selecting one memory cell by an internal word line selection clock output from a row decoder, one internal bit line connected to the internal cell array at a position opposite to the separating means, and the pair of input / output bus lines. And a transmission means connected between the column decoder and the column decoder for selecting the bit line in response to the column selection clock. First sense amplifying means connected between a pair of internal bit lines between the reaching means and the internal cell array to sense and amplify a voltage difference on the internal bit lines in response to a first sense clock; and the internal array. And a first sense amplifying means for connecting the pair of internal bit lines to amplify the amplified voltage sufficiently in response to a first restore clock to restore it to a selected memory cell. Restore means and connected to the pair of external bit line ends,
Equalization means for inputting an equalization clock during a precharge cycle to equalize the external bit line and the internal bit line to half the power supply voltage, and a plurality of memory cells connected to the pair of external bit lines. And an external cell array for selecting one memory cell by an external word line selection clock output from the row decoder,
A second sense bit line connected between the pair of external bit lines between the external cell array and the separating means to sense and amplify a voltage difference on the external bit lines in response to a second sense clock;
A sense amplifier is connected between the external cell array and the equalizer, and a pair of external bit lines are connected between the sense amplifier and the equalizer to sufficiently amplify the amplified voltage in response to a second restore clock to select the selected memory. Second restore means for restoring to a cell, and when any memory cell of the external cell array in the active cycle is selected, second sensing means,
The second restoring means, the separating means, the first sensing means, and the first restoring means operate in this order, and when any memory cell of the internal cell array is selected, the first sensing means, the first restoring means, and the separating means. , A second sensing means and a second restoring means, in order to operate, a CMOS including a sensing clock generating means for generating the first and second sensing clocks, the separated clock and the first and second restoring clocks.
Features a DRAM device.

Also, the ratio of the size of the current paths of the first restore means and the second restore means may be different, and the size of the current paths of the first sense amplification circuit and the second sense amplification circuit may be different. You can also do so.

Also, another equalization circuit may be connected between the pair of internal bit lines.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

As shown in the plan view of one chip shown in FIG. 1, the sense amplifier of the present invention is implemented as an embodiment in the configuration of 4M DRAM (hereinafter referred to as "DRAM"). Four blocks BL1 to BL4 are horizontally arranged in the center of the chip 1. A column decoder and an input / output (hereinafter referred to as I / O) bus line are located in the central area 27 of each of the blocks BL1 to BL4.

Regions 26a, 26 are sequentially provided on the left side and the right side of the central region 27 in each direction.
The first equalization circuit is provided in each of b, the first sense amplifier and the first restore circuit are provided in each of the regions 25a and 25b, the 256K internal cell array is provided in each of the regions 24a and 24b, and the transmission gate is provided in each of the regions 23a and 23b. A second sense amplifier is provided in each of the areas 22a and 22b, and 256k is provided in each of the areas 21a and 21b.
Of the external cell array, the second restore circuit is arranged in each of the areas 20a and 20b, and the equalizing circuit is arranged in each of the areas 19a and 19b.

Therefore, each block contains 1M memory cells.

In addition, the areas 26a, 25a, 24a, 23a, 22a, 21a, 20a of each block,
19a and regions 26b, 25b, 24b, 23b, 22b, 21b, 20b, 19b are arranged symmetrically to the left and right with respect to the central region 27. Here, the notations left and right indicate the left side and the right side with respect to the central area 27 of each block where the column decoder and the I / O bus line are located, and the inside and the outside are the positions with respect to the central area 27. It should be noted that it is a relationship.

A row address buffer is located in the area 13 at the left end of the chip 1. The row address buffer inputs the TTL level row address signals R0 to R9 with external pins, and the CMOS level true row address signals RA0 to RA9 and false (completion).
ment) row address signals ▲ ▼ to ▲ ▼.

Regions 14a and 14b in which row decoders and word line drivers for generating signals for selecting memory cells of the external cell array and the internal cell array are arranged above the blocks BK1, BK2, BK3 and BK4. , 14c, 14d
Are located respectively. The row decoder outputs row address signals RA0 to RA7 and ▲ ▼ to ▲ ▼ from the row address buffer.
Is a well-known circuit which inputs a signal and selects one memory cell in each of the left and right external cell arrays, or outputs a signal for selecting one memory cell in each of the left and right internal cell arrays. .

In addition, BK1, BK2, BK3, and BK4 according to the present invention, which generate sensing operation clocks when reading data from the blocks BK1 to BK4, are provided above the regions 14a, 14b, 14c, and 14d.
Area 12 where the sensing clock generation circuits of
There are a, 12b, 12c and 12d. The BK1 sensing clock generation circuit and BK3 sensing clock generation circuit use the row address buffer RA7, ▲ ▼ and ▲ ▼.
And a clock φ _S described later are input. Blocks BK1 and BK3
And a sensing operation clock for sensing data stored in the memory cells.

The BK2 sensing clock generation circuit and the BK4 sensing clock generation circuit are stored in the memory cells of the blocks BK2 and BK4 by inputting the row address signals ▲ ▼, RA7 and RA8 and the clock φ _S from the row address buffer. A sensing operation clock for sensing data is generated.

Therefore, the blocks BK1 and BK3 or the blocks BK2 and BK4 are selected by the row address signals ▲ ▼ and RA8.

Further, as will be described later, a data sensing operation is performed from the selected memory cell in the external cell array or the internal cell array in the selected block according to the row address signals ▲ ▼ and RA7.

In the area 10 other than the above-mentioned area, a column address buffer, a clock generator required for 4M DRAM operation, and an input / output buffer for data are built-in.

FIG. 2 is a diagram showing an example of one of the four blocks BK1 to BK4 on the left side of FIG.

It should be noted that one column on the right side also has the same configuration as in FIG. Bit lines 47 and 77 are connected through the channel passage of isolation transistor 60,
Bit lines 48 and 78 are connected through the channel passage of isolation transistor 61.

The isolation transistors 60 and 61 are all N-type channels
It is a MOS transistor (hereinafter referred to as “NMOS transistor”) and constitutes the transmission gate circuit 140. Isolation clock φIS is applied to each gate of the isolation transistors 60 and 61.
O is applied. Bit lines 47 and 48 are referred to as external bit lines BLO and ▲ ▼, respectively, and bit lines 77 and 78 are referred to as internal bit lines BLI and ▲ ▼, respectively.

A first equalization circuit 100 is connected to the outermost ends of the external bit line pair BLO and {circle around (▼)}. The second equalization circuit 100 includes an NMOS transistor 32 having a channel passage connected between the node 30 and the external bit line BLO, and an NMOS transistor 33 having a channel passage connected between the node 30 and the external bit line ▲ ▼. And external bit line BLO ▲
And an NMOS transistor 34 whose channel path is connected between the and.

Further, all the gates of the NMOS transistors 32, 33 and 34 are commonly connected to the node 31 and the equalized clock φEQ is applied.

Also, P is placed between the external bit line BLO and ▲ ▼.
Channel MOS (hereinafter referred to as "PMOS") transistor
The channel paths of 36 and 37 are connected in series through a connection node 38, and the gates of the transistors 36 and 37 are connected so as to cross the external bit lines BLO and B, respectively.

Also, the PMOS transistors 36 and 37 are the second restore circuit 1
Make up 10.

The connection node 38 has a second restore clock described later.
LA1 is applied. External bit line pair BLO and ▲ ▼
The channel paths of NMOS transistors 50 and 51 are connected in series between the bit lines BLO and ▲ ▼ through a connection node 52 on the right side of the transistors 50 and 51, respectively. Gate is the bit line above
BLO and ▲ ▼ are connected to the intersection.

The NMOS transistors 50 and 51 form a second sense amplifier circuit 130. The second sensing clock ▲ ▼ is applied to the connection node 52. Further, in the external bit line pair BLO and ▲ ▼ between the second restore circuit 110 and the second sense amplifier circuit 130, the memory cell 40, 41 forming the external cell array 120 is a known folding bit line (fol).
ded bit line) method. Each memory cell is composed of one NMOS transistor 45 and one storage capacitor 46.

The channel paths of the internal bit line pair BLI and B are connected to the I / O bus line 97 and B bus line 98 through transfer transistors 95 and 96 of NMOS transistors, respectively.

A signal φCD for selecting a column is applied from the column decoder to the gates of the transfer transistors 95 and 96.

Internal bit line pair BLI connected to transmission gate circuit 140
The channel paths of the NMOS transistors 68 and 69 are connected in series through the connection node 65 between the and ▲ ▼, and the gates of the NMOS transistors 68 and 69 cross the bit lines BLI and ▲ ▼. Connected.

Further, the first sensing clock ▲ ▼ is applied to the connection node 65.

The NMOS transistors 68 and 69 are the first sense amplifier circuit 15
Configures 0. Also, the transfer transistors 95, 96 and the first
Internal bit line BLI between the sense amplifier circuit 150 and
A first equalizing circuit 180 composed of an NMOS transistor 90 having a channel passage connected between and is connected to
The equalization clock φ is applied to the gate of the NMOS transistor 90.
EO is applied.

In addition, the first sense amplifier circuit 150 and the isolation transistor 60,
A channel path is serially connected through a connection node 82 between the internal bit line BLI and ▲ ▼, and PMOS transistors 80 and 81 whose gates are connected to the bit line BLI and ▲ ▼. The first restore circuit 170 composed of and is connected.

The internal bit line BLI between the isolation transistors 60 and 61 and the first restore circuit 170 and one NMO are connected to ▲ ▼.
An internal cell array 160 is connected in which memory cells 70 and 71 each including an S transistor 75 and one storage capacitor 76 are connected by a folding bit line method.

In the above, one end of the storage capacitor is Vcc / 2
The word line selection clocks φWLO1, φWLI1 and the like for selecting the row memory cell are applied from the row decoder to the gate of the NMOS transistor of the memory cell.

Also, it should be noted that in the present invention, the cell array does not use a damicel. In the above, the geometric size of the PMOS transistors 80 and 81 of the first restore means is the PMOS transistor 3 of the second restore means.
It is constructed larger than the geometric size of 6,37.

FIG. 3 is a diagram showing an embodiment of a sensing clock generation circuit for generating the used clock of FIG. 2 according to the present invention.

The sensing clock generation circuit 12 of FIG. 3 is used for the blocks BK1 and BK3 of FIG.
Row address ▲ ▼ is applied to 5,286, and block B
It should be noted that RA8 is applied to lines 280,290,285,286 when used for K2 and BK4.

In addition, the row address signals ▲ are written on the lines 283, 293 and 284 respectively.
▼, RA7 and clock φS are applied, terminals 281 and 2
A power supply voltage Vcc of 5V is applied to 91 and. Further, Vcc / 2 (2.5V) is applied to the terminals 310 and 320.

Reference numerals 202, 203, 204 and 20 are delay circuits each composed of an inverter, and reference numerals 206 and 207 are equalization circuits.

Reference numbers 230,240,250,252,260,261,270,271,272 are all NAND gates, reference numbers 231,232,234,241,242,24
4,251,253,254,263 and 273 are all inverters.

Each of the NAND gates is a 2-input IN1, IN2, 1 output (OUT) CMOS NAND gate using PMOS transistors 401 and 402 and NMOS transistors 403 and 404 as shown in FIG. 4A.

In addition, each of the above inverters is connected to the PM as shown in Fig. 4B.
A CMOS inverter composed of an OS transistor 405 and an NMOS transistor 40 is used.

It should be noted that the NAND gate and the inverter are known circuits.

The operation of the sensing clock generation circuit 12 shown in FIG. 3 will be described in detail.

When the row address signal RA8 (or ▲ ▼) is in the “low” state (Vss voltage), the output of the NAND gate 252 is “high”.
State (Vcc voltage).

Therefore, the line 30 is connected through the two inverters 253 and 254.
The separated clock φISO output from 1 goes to the “high” state.

Also, the outputs of NAND 230 and 240 are all "high".

Therefore, the gates of the CMOS transistors 233 and 243 are all in the “high” state through the inverters 231 and 232 and the inverters 241 and 242, and the two transistors 233 and 243 are all in the “OFF” state.

Also, because the outputs of NAND gates 262 and 272 are all "high", the outputs of inverters 263 and 373 are all "low" and all NMOS transistors 264 and 274 are off.

In addition, since the outputs of the inverters 234 and 244 are all in the “high” state, the NMOS transistor 3 that constitutes the equalization circuit 206 is
NMOS transistor 3 which forms equalizer 207 with 11,312,313
21,322,323 are all in the "ON" state.

Therefore, lines 302 and 303 and lines 304 and 305 are all equalized to Vcc / 2. That is, the second sensing clock ▲ ▼, the second restore clock LA1, the first restore clock LA2 and the first sensing clock ▲ ▼ are all precharged as Vcc / 2.

Also, since lines 282 and 292 are all "high", the output of NAND gate 250 is "low" and the output of inverter 251 is "high". Also, the outputs of the delay circuits 202 and 203 are all in the “high” state, and the delay circuits 204 and 205 maintain the “low” state.

After that, the row address signal RA8 (or ▲ ▼) becomes “high” state, and the row address signal RA7 becomes “low” state ▲
When ▼ becomes “high” state, the separated clock φ output to the line 301 by the “high” state of the output of the AND gate composed of the NAND gate 250 and the inverter 251.
S changes to "low" state.

Also, since lines 280 and 290 are all in a "high" state, equalization circuits 205 and 207 interrupt the equalization operation. After that, when the clock φS goes to the “high” state, the NAND gate
The output of 260 becomes "low", the output of NAND gate 261 becomes "high", and the output of NAND gate 262 becomes "low".

Therefore, an NMOS transistor whose gate is in the "high" state
Since the 264 is in the "ON" state, the second sensing clock ▲
▼ becomes “low”. Then, the output of the delay circuit 204 becomes "high" and the output of the NAND gate 230 becomes "low".
It becomes a state.

Therefore, a PMOS transistor whose gate is in the "low" state
233 becomes ON state, and the second restore clock LA1 becomes “high” state.

Further, since the line 282 is in the “low” state, the output of the inverter 251 is in the “low” state, and the separation clock φISO
Changes to the "high" state. After that, the “low” state of line 282 causes the output of delay circuit 203 to go to the “low” state, the output of NAND gate 271 to go to the “high” state, and
The output of AND gate 272 goes "low". Therefore, the NMOS transistor 274 whose gate is in the “high” state is
N "state, the first sensing clock ▲ ▼ is" low "
Change to state. The output of the delay circuit 205 then goes to the "high" state and the output of the NAND gate 240 goes to the "low" state.

Therefore, a PMOS transistor whose gate is in the "low" state
243 becomes "ON" state, and the first restore clock LA2 becomes "high" state.

On the other hand, when the row address signal RA8 (or ▲ ▼) changes to "high" when it is "low", RA7 is in "high" state, and when the clock φS is in "high" state, the separated clock φ
ISO is "low" state, 1st sensing clock ▲ ▼ is "low" state, 1st restore clock is "high" state,
The separation clock φISO is in the “high” state, the second sensing clock ▲ ▼ is in the “low” state, and the third restore clock LA1 is in the “high” state.

FIG. 5 is a drawing showing an operation timing chart of each part of FIG. 2 and FIG.

Hereinafter, the operation of FIG. 2 will be described in detail with reference to the timing chart of FIG.

Row address strobe ▲ ▼ before time t ₁ is “high”
Row address signal RA8 and ▲ ▼,
RA7 (and ▲ ▼) are all in the “low” state, and the precharge cycle is maintained by the “high” state of the equalization clock φEQ. Then, the separated clock φ
ISO becomes “high” state and constitutes the third equalization circuit 100.
NMOS transistors 32, 33, 34 are all in the "ON" state,
The NMOS transistor 90 that constitutes the first equalization circuit 180 is also "ON"
It becomes a state.

Therefore, the external bit line pair BLO and ▲ ▼ and the internal bit line pair BLI and ▲ ▼ are all precharged to Vcc / 2.

The address is input after ▲ ▼ goes to the “low” state (active cycle) at time t ₁ .

When the row address signal RA8 (or ▲ ▼) becomes "high" state and the row address signal RA7 becomes "low" state at time t ₂ , it is generated by a clock generation circuit (not shown) at the time of inputting an address. The equalized clock φEQ goes "low".

Further, the separated clock φISO is also set to the “low” state.

Therefore, the first and second equalization circuits 180 and 100 are turned off, and the separation transistors 60 and 61 are all turned off.

After that, the word line selection clock φLO1 for selecting the external cell array 120 becomes Vcc + 2VT (VT is a threshold voltage).
If the storage capacitor of memory cell 40 is “1”
If the (high) state is charged, the external bit line BLO is turned on by the charge distribution to the ON state of the NMOS transistor 45.
Indicates that the voltage is increased by about 200 mV from Vcc / 2 like reference numeral 500.

It should be noted that the used clock φS in FIG. 4 is a signal obtained by delaying the word line selection signal. When at time t ₃ clock φS becomes "high" state, the second sensing clock at time t ₄ as described previously ▲ ▼ is "low" and the state (501), the second restoration clock LA1 at time t ₅ " High ”state (502). Therefore, the time
The second sense amplifier circuit 130 operates between t ₄ and t ₅ to discharge the external bit line {circle around (5)} in the "low" state (505).

After time t ₅ , the restore circuit 110 operates and the external bit line BLO is amplified by Vcc (506) and the memory cell 4
Restore 0.

Since LA1 is in the “high” state, as described above,
In separate clock φISO time t ₆ becomes "high" state, all made in the ON state is the isolation transistors 60 and 61. Therefore, the charged charges on the external bit lines BLO and ▲ ▼ are transferred to the internal bit lines BLI and ▲ ▼ (507 and 508 in FIG. 5). First sensing clock ▲ ▼ becomes "low" state (503) at time t _7, the time the first restoration clock LA2 at t ₈ becomes "high" state (504), the transfer charge is first By the sense amplifier 130 and the first restore circuit 170, the internal bit line pair BLI and
▼ is amplified to Vcc and Vss respectively, and the above memory cell
40 is restored and is output to the I / O bus lines 97 and 98 through the transmission transistors 95 and 96 by the column selection signal φCD output by the column decoder.

On the other hand, at time t ₂ , the row address signal RA8 (or ▲ ▼)
Is in the “high” state, and RA7 is in the “high” state, the equalization clock φEQ is in the “low” state, and the separation clock φ
The ISO is also in the "low" state. Therefore, the first and second equalization circuits 180 and 100 and the isolation transistors 60 and 61 are turned off, and any one of the memory cells 70 in the first cell array 160 is turned on.
Select word line selection clock φWLI1 is Vcc + 2VT
become.

“1” (Vcc) in storage capacitor 76 of memory cell 70
Is stored, the charge charges the internal bit line BL1 as indicated by reference numeral 500.

After that, as described above, when the clock φS goes to the “high” state, the first sensing clock ▲ ▼ goes to the “low” state at time t ₄ (501), and the first sensing amplifier circuit 150 operates, thereby Bit line ▲ ▼ is Vss (50
Discharge to 5).

After that, when the restore clock LA2 becomes “high” state (502) at time t ₅ , the first restore circuit 170 operates to amplify the internal bit line BL1 to Vcc (506), and the memory cell 7
List 0. After that, at time t ₆ , the separated clock φISO
Goes "high".

Therefore, the charge of the internal bit line BL1 is transferred to the external bit line BLO, and the external bit line ▲
The charge charged to Vcc / 2 of ▼ is the internal bit line ▲
Discharge to ▼.

After that, at time t ₇ and time t ₈ , the second sensing clock ▲
▼ and the second restore clock LA1 are in the “low” state (5
03) and the "high" state (504), and the first and second sense amplifier circuits 150 and 130 and the first and second restore circuits 170 and 110 are all operated to cause the bit lines BLO and BLI.
And bit line ▲ ▼ and ▲ ▼ respectively Vcc
And Vss to restore the memory cell 70.

Thereafter, as described above, the charge stored in the internal bit line is output to the I / O bus lines 97 and 98 through the transfer transistors 95 and 96.

If ▲ ▼ is at time t ₉ active cycle is finished becomes "high" state, the word line selected clock φWLO1 or φWLI1 becomes "low" state, the row address signal RA8 (and ▲ ▼) and RA7 (and ▲
▼) are all "low", and the equalization clock φEQ is
It goes into the "high" state and enters the charge cycle. Then, the first and second sensing clocks ▲ ▼ and ▲
▼ and the first and second restore clocks LA2 and LA1 are all Vcc / 2, and all bit line pairs are precharged to Vcc / 2.

Separated internal and external bit lines BL1, ▲ ▼, BLO, ▲ during read modify write cycle of DRAM
The data of ▼ is changed to the corrected data coming in from the input / output lines 97 and 98. That is, the data on the internal and external bit lines BL1, ▲ ▼, BLO, ▲ ▼ are corrected from “high” level to “low” level or from “low” level to “high” level. At this time,
The drain-source current ratio between the NMOS transistor and the PMOS transistor of the N-type and P-type latch circuits forming the sensing circuit and the restore circuit is I _P / I _N.

Therefore, the voltage between the pit lines driving the N-type latch circuit must be higher than that of the P-type latch circuit. As a result, the first sense amplifier circuit 150, which is arranged most adjacent to the input / output lines 97, 98, has the internal bit line BL
Since the influence of the resistance at I and ▲ ▼ and the capacitance between the internal bit lines BLI and ▲ ▼ are minimized, the operation is performed at high speed.

Also, the first sense amplifier circuit 150 has a first end connected to the next end thereof.
The restore operation by the restore circuit 170 is because the drain-source current I _{P of} the PMOS transistor forming the P-type latch circuit is smaller than the drain-source current I _N of the NMOS transistor of the first sense amplifier circuit. The 1-restoring circuit 170 is flipped quickly without difficulty.

After that, after correcting the data of the cell corresponding to the internal cell array block 150 to the corrected level of the internal bit run-in BLI, ▲ ▼, the data of the external bit line BLO, ▲ ▼ separated by the transmission gate circuit 140 is corrected. .

At this time as well, the second sense amplifier circuit is similarly operated as described above.
Since 130 is closest to the transmission gate circuit 140, the second sensing and amplifying circuit 130 for data sensing does not have to operate quickly.

On the other hand, the second restore circuit 110 that restores data is
The input / output lines 97, 98 are the furthest apart, but their quick flipping operation is reasonable as described above.

In particular, since the size of the transistors forming the second restore circuit 110 is relatively smaller than the size of the transistors of the first restore circuit 170, the input / output lines 97, 9
Eight modified data will be easy to write.

〔The invention's effect〕

According to the present invention as described above, the data sensing speed and the voltage margin between the bit lines are improved, and the transmission and restoration of the corrected data during the read-modify-write cycle are stabilized and speeded up. It has the unique effect of enabling the production of high-density memory of 4M DRAM or more.

[Brief description of drawings]

FIG. 1 is a block diagram of a CMOS / DRAM chip according to the present invention, and FIG.
Figure is a circuit diagram showing memory cells, bit lines, sense amplifier circuit, restore circuit, equalization circuit, connection between input / output lines and bit lines, and Figure 3 generates the sensing clock necessary for the operation of Figure 2. Sensing clock generator circuit diagram, which is used as one component of Fig. 3
5 is a circuit diagram of the CMOS inverter, and FIG. 5 is an operation timing chart of FIG. 2 when reading data from the memory cell.

Claims (5)

[Claims] 1. In a CMOS / DRAM, a row decoder, a column decoder, a pair of input / output bus lines, a pair of adjacent parallel internal bit lines, a pair of adjacent parallel external lines, and Separation means for separating a pair of internal bit lines and a pair of external bit lines corresponding thereto at a predetermined time in an active cycle in response to a separation clock; and a plurality of memory cells connected to the pair of internal bit lines. An internal cell array for selecting one memory cell according to an internal word line selection clock output from the row decoder; an internal bit line connected to the internal cell array at a position opposite to the separating means; Is connected between the I / O bus line and the column decoder to select the bit line in response to the column selection clock. And a first sense amplifying means connected between a pair of internal bit lines between the transmitting means and the internal cell array and sensing and amplifying a voltage difference on the internal bit lines in response to a first sensing clock. , Is connected between the internal bit line pair between the internal cell array and the first sense amplifying means, sufficiently amplifies the amplified voltage in response to a first restore clock, and outputs the selected memory cell to the selected memory cell. First restore means for restoring and an end of the pair of external bit lines are connected to input an equalization clock during a precharge cycle to equalize the external bit line and the internal bit line to half the power supply voltage. It has an equalizing means for equalizing and a plurality of memory cells connected to the above-mentioned pair of external bit lines, and an external word line selection clock output by the row decoder. Is connected between an external cell array for selecting one memory cell and a pair of external bit lines between the external cell array and the separating means, and a voltage difference on the external bit line in response to a second sensing clock. Is connected between a pair of external bit lines between the external cell array and the equalizing means and senses and amplifies the amplified voltage sufficiently in response to a second restore clock. Then, the second restore means for restoring to the selected memory cell, and the second sensing means, the second restore means, the separating means, the first restore means when any memory cell of the external cell array in the active cycle is selected. The sensing means and the first restoring means operate in this order, and when any memory cell of the internal cell array is selected, the first sensing means, the first restoring means, and the Separating means, second sensing means, second
A CMOS / DRAM device comprising a sensing clock generating means for generating the first and second sensing clocks, the separated clock and the first and second restoring clocks so that the restoring means operates in the order. 2. The first and second sensing means, wherein each gate is connected to a pair of bit lines at intersections, channel passages are connected in series and connected to the bit lines, and a connection point of the channel passages is Each of the first and second restore means has a gate connected to a pair of bit lines and a connection point of a channel path, which is formed of a pair of NMOS transistors to which a first sense clock and a second sense clock are applied. 2. The CMOS / DRAM device according to claim 1, comprising a pair of PMOS transistors to which the first restore clock and the second restore clock are applied, respectively. 3. The CMOS / DRAM device according to claim 2, wherein the transistor size of the second restore circuit is relatively smaller than the transistor size of the first restore circuit. 4. The CMOS DRAM device according to claim 2, wherein the size of the transistor of the second sense amplifier circuit is relatively smaller than the size of the transistor of the first sense amplifier circuit. 5. The second restore circuit is connected between a pair of external bit lines between the external cell array and the second sense amplifier circuit, according to any one of claims 1 to 4. The described CMOS / DRAM device.