JPH06103597B2 - Semiconductor integrated circuit device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a voltage dividing circuit incorporated therein, and is used, for example, in a half precharge type dynamic RAM (random access memory). It relates to effective technology.

[Background technology]

For example, MOSFET (insulated gate type field effect transistor)
As the voltage dividing circuit configured in FIG. 4, a circuit in which an N-channel MOSFET Q61 of a P-channel MOSFET Q60 is connected in series with a resistance means as shown in FIG. In this case both MOSF
The output current is always smaller than the through current (DC current) flowing between ETQ60 and Q61. For this reason, if an attempt is made to set the output current to a relatively large value, the shoot-through current will become extremely large and power consumption will increase.

By the way, a 1-bit memory cell in a dynamic RAM is composed of an information storage capacitor Cs and an address selection MOSF.
It consists of ETQm and the information of logic "1" and "0" is the capacitor
It is stored in the form of whether or not there is an electric charge. To read information, the MOSFET Qm is turned on, the capacitor Cs is connected to the common data line D, and the potential of the data line D is changed to the capacitor Cs.
This is done by sensing what kind of change occurs depending on the amount of charge stored in the memory. Above capacitor Cs
Uses the MOS capacitance between the gate electrode and the channel. Therefore, a power supply voltage is constantly supplied to the gate electrode or a channel is formed on the semiconductor surface under the gate electrode by the ion implantation method. As a method of forming the read reference voltage of the memory cell, a data line half precharge method (or a dummy cellless method) is known [for example, ISSC 84, digest of technical page (ISSCC84, DIGIST OF TECHNICAL PAPERS) No. 276
Pp.-277, Nikkei McGraw-Hill Co., February 11, 1985, "Nikkei Electronics" pp.243-263]. In this case, when the power supply voltage or the ground potential of the circuit is used as the voltage applied to the gate electrode of the MOS capacitor, the read level margin deteriorates with respect to the fluctuation (bump) of the power supply voltage. For example, in a configuration in which the ground potential is applied to the gate electrode of the MOS capacitor, the power supply voltage Vcc of about 4V
The stored information of the memory cell written under
When a read operation is performed under a power supply voltage Vcc raised to about 6V, the half precharge voltage is raised to about 3V according to the fluctuation of the power supply voltage. The level margin for On the other hand, in the configuration in which the circuit power supply voltage is applied to the gate electrode of the MOS capacitor, the low level (ground potential side of the circuit) is raised to about 2V, so that the level margin on the low level side deteriorates. I will end up.

Therefore, the inventor of the present application considered setting the gate voltage of the MOS capacitor to about Vcc / 2 in the half precharge type dynamic RAM. However, if the voltage dividing circuit as shown in FIG. 4 is used, the power consumption will increase.

[Object of the Invention]

An object of the present invention is to provide a semiconductor integrated circuit device including a voltage generation circuit that realizes low power consumption.

Another object of the present invention is to provide a dynamic RAM with low power consumption and improved operation margin.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention]

The following is a brief description of the outline of a typical embodiment of the invention disclosed in the present application. That is,
The divided voltage is level-shifted through the diode-shaped first and second conductivity type MOSFETs so that the threshold voltage is set to be larger in absolute value than the threshold voltage of the MOSFET. The voltage is supplied to the gate of a source follower type output MOSFET having the same conductivity type as that of the diode type MOSFET, and a voltage corresponding to the divided voltage is obtained from a common source of these output MOSFETs.

[Embodiment 1] FIG. 1 shows a circuit diagram of an embodiment in which the present invention is applied to a dynamic RAM. Each circuit element in the figure is formed on a semiconductor substrate such as one single crystal silicon by a known CMOS (complementary MOS) integrated circuit manufacturing technique. In the figure, the MOSFET in which a straight line is added between the source and drain is a P-channel type.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single crystal P-type silicon. N-channel MOSFET
Is a gate electrode made of polysilicon formed through a thin gate insulating film on the surface of the semiconductor substrate between the source region and the drain region and between the source region and the drain region. Composed of. The P-channel MOSFET is formed in the N-type well region formed on the surface of the semiconductor substrate. As a result, the semiconductor substrate has a plurality of N channel MOs formed thereon.
Configure a common substrate gate for SFETs. The N-type well region constitutes the body gate of the P-channel MOSFET formed thereon. The substrate gate of the P-channel MOSFET, that is, the N-type well region, is coupled to the power supply terminal Vcc in FIG. The substrate bias voltage generation circuit VBG generates a negative back bias voltage −Vbb to be supplied to the semiconductor substrate. As a result, a back bias voltage is applied to the substrate gate of the N-channel MOSFET to reduce the parasitic capacitance value between the source and drain of the N-channel MOSFET and the substrate, so that the circuit can operate at high speed.

A more specific structure of the integrated circuit will be roughly described as follows.

That is, of the surface portion of the semiconductor substrate formed of single crystal P-type silicon and in which the N-type well region is formed, other than the surface portion that is the active region, in other words, the semiconductor wiring region, the capacitor formation region, and the N channel and A field insulating film having a relatively large thickness formed by a known selective oxidation method is formed on the source and drain of the P-channel MOSFET and a surface portion which is a channel forming region (gate forming region). The capacitor formation region is not particularly limited, but on the capacitor formation region,
The first polysilicon layer is formed via an insulating film (oxide film) having a relatively thin thickness. The first polysilicon layer extends to above the field insulating film. A thin oxide film formed by thermal oxidation of itself is formed on the surface of the first polysilicon layer. Although not particularly limited, an N-type region (channel region) formed by an ion implantation method is formed on the surface of the semiconductor substrate in the capacitor formation region. As a result, a capacitor composed of the first polysilicon layer, the thin insulating film and the channel region is formed. The first polysilicon layer on the field oxide film is regarded as one kind of wiring.

On the channel formation, a second polysilicon layer for forming a gate electrode is formed via a thin gate oxide film. The second polysilicon layer extends over the field insulating film and the first polysilicon layer. Although not particularly limited, the word line in the memory array described later is composed of the second polysilicon layer.

Source, drain and semiconductor wiring regions are formed on the surface of the active region which is not covered by the field insulating layer, the first and second polysilicon layers, by a known impurity introduction technique using them as an impurity introduction mask. .

A relatively thick interlayer insulating film is formed on the surface of the semiconductor substrate including the first and second polysilicon layers, and a conductor layer made of aluminum is formed on the interlayer insulating film. . The conductor layer is electrically coupled to the polysilicon layer and the semiconductor region via a contact hole provided in the insulating film thereunder. The data line in the memory array described later is composed of a conductor layer extended on this interlayer insulating film, although not particularly limited thereto.

The surface of the semiconductor substrate including the interlayer insulating film and the conductor layer is covered with a final passivation film composed of a silicon nitride film and a phosphine silicate glass film.

The memory array M-ARY is of a two-intersection (folded bit line) system, although not particularly limited thereto. FIG. 1 specifically shows the pair of rows. A pair of parallel arranged complementary data lines (bit line or digit line) D,
Address select MOSFET Qm and information storage capacitor Cs
Input / output nodes of a plurality of memory cells configured by are distributed and coupled with a predetermined regularity as shown in FIG.

The precharge circuit PC includes a switch MOSF provided between the complementary data line D and the MOSFET Q5 shown as a representative.
Composed of ET. The MOSFET Q5 is turned on in the chip non-selected state by supplying a precharge signal φpc generated in the chip selected state to its gate. This ensures that in the previous operating cycle,
Complementary data line by amplification operation of sense amplifier SA described later
The high level and the low level of D, are short-circuited to set the complementary data line D, to a precharge voltage of about Vcc / 2. RAM
Is in the chip unselected state, and the above-mentioned precharge MOSFET Q5
The sense amplifier SA is set to a non-operational state before the above are turned on. As a result, the complementary data line D, holds a high level and a low level in a high impedance state. When the RAM is put into operation, the precharge MOSFET Q5 and the like are turned off before the sense amplifier SA is put into operation. This allows
The complementary data line D, holds the harp precharge level in the high impedance state.

In such a half precharge system, since the high level and the low level of the complementary data line D, are simply short-circuited and formed, the power consumption can be reduced. Further, in the amplifying operation of the sense amplifier SA, since the complementary data line D, which changes around the precharge level in the common mode such as the high level and the low level, can reduce the nozzle level generated by capacitive coupling. Become.

The unit circuit USA of the sense amplifier SA is shown as an example, and the P-channel MOSFETs Q7 and Q9 and the N-channel MOS are shown.
It is composed of a CMOS latch circuit composed of FETs Q6 and Q8, and its pair of input / output nodes is coupled to the complementary data line D. In addition, although not particularly limited, the latch circuit is supplied with the power supply voltage Vcc through the P-channel MOSFETs Q12 and Q13 arranged in parallel, and the N-channel MOSFET Q arranged in parallel.
The ground voltage Vss of the circuit is supplied through 10, Q11. These power switch MOSFETs Q10, Q11 and MOSFET Q12, Q13
Are commonly used for latch circuits (unit circuits) provided in other similar rows in the same memory mat. In other words, the sources PS and SN of the P-channel MOSFET and the N-channel MOSFET in the latch circuit in the same memory mat are commonly connected.

The gates of the MOSFETs Q10 and Q12 have complementary timing pulses φpa for activating the sense amplifier SA in the operation cycle.
1, pa1 is applied, and complementary timing pulses φpa2, pa2 delayed from the timing pulses φpa1, pa1 are applied to the gates of the MOSFETs Q11, Q13. By doing so, the operation of the sense amplifier SA is divided into two stages. When the timing pulses φpa1 and pa1 are generated, that is, in the first stage, the minute read voltage applied between the pair of data lines from the memory cell by the current limiting action of the MOSFETs Q10 and Q12 having a relatively small conductance is It is amplified without undergoing unwanted level fluctuations. When the timing pulse φpa2, pa2 is generated after the difference between the complementary data line potentials is increased by the amplifying operation of the sense amplifier SA, that is, when the second stage is entered, the MOSFET having a relatively large conductance.
Q11 and Q13 are turned on. The amplification operation of the sense amplifier SA is accelerated by turning on the MOSFETs Q11 and Q13. In this way, the sense amplifier is divided into two stages.
By performing the SA amplification operation, it is possible to perform high-speed reading of data while preventing undesired level changes of the complementary data lines.

Although not particularly limited, the row decoder R-DCR is composed of a combination of row decoders R-DCR1 and R-DCR2 divided into two. In the figure, the second row decoder R
One DCR2 circuit (4 word lines) is shown as a representative. According to the configuration shown, the address signals 2 to
NAND by a CMOS circuit composed of N-channel MOSFETs Q32 to Q34 receiving m and P-channel MOSFETs Q35 to Q37
The four word line selection signals are formed by the (nand) circuit. The output of the NAND circuit is inverted by the CMOS inverter IV1 and transmitted to the gates of the transmission gate MOSFETs Q24 to Q27 as the switch circuits through the cut MOSFETs Q28 to Q31.

Although the specific circuit of the first row decoder R-DCR1 is not shown, 2-bit complementary address signals a0,0 and a1,
The four word line selection timing signals φx00 to φx11 from the word line selection timing signal φx through the switch circuit composed of the transmission gate MOSFET and the cut MOSFET similar to the above selected by the decode signal formed by 1.
To form. These word line selection timing signals φx0
0 to φx11 is transmitted to each word line via the transmission gate MOSFETs Q24 to Q27.

Although not particularly limited, the timing signal φx00 is set to the high level in synchronization with the timing signal φx when the address signals 0 and 1 are set to the high level. Similarly, the timing signals φx01, φx10 and φx11 are the timing signals φx when the address signals a0 and 1 and 0 and a1 and a0 and a1 are at high level, respectively.
It goes high in sync with.

As a result, the address signals a1 and 1 are generated by a word line group (W0, W1, hereinafter referred to as a first word line group) corresponding to the memory cells coupled to the data line D of the plurality of word lines, It is regarded as a kind of word line group selection signal for identifying the word line group (W2, W3, hereinafter referred to as the second word line group) corresponding to the memory cells coupled to the data line D.

By dividing the row decoder into two such as the row decoders R-DCR1 and R-DCR2, the pitch (interval) of the row decoder R-DCR2 and the pitch of the word lines can be matched. As a result, no wasted space is produced on the semiconductor substrate. MOSFETs Q20 to Q23 are connected between each word line and ground potential.
Is provided, and the output of the NAND circuit is applied to the gate thereof to fix the word line in the non-selected state to the ground potential. Although not particularly limited, reset MOSFETs Q1 to Q4 are provided on the far end side (end opposite to the decoder side) of the word line, and these MOSFETs Q1 to Q4 are turned on by receiving a reset pulse φpw. By entering the state, the selected word line is reset from its both ends to the ground level.

The column switch C-SW is a MOSF shown as a representative.
Like ETQ42 and Q43, the complementary data line D and the common complementary data line CD, ▲ ▼ are selectively coupled. These MOSFE
A selection signal from the column decoder C-DCR is supplied to the gates of TQ42 and Q43.

The row address buffer R-ADB is activated by a timing signal (not shown) formed by a timing generation circuit TG described later based on the row address strobe signal ▲ ▼ supplied from the external terminal. Row address strobe signal ▲
Address signal A0 ~ supplied from the external terminal in synchronization with ▼
Captures Am, to form an internal complementary address signal a 0 to a m tell the row address decoders R-CDRl and R-DCR2 holds it. Here, the address signal A0 supplied from the external terminal, the internal address signal a0 having the same phase, and the internal address signal 0 having the opposite phase are combined and expressed as a complementary address signal a0 (hereinafter the same). Row address decoder R-DCR1 and R-DC2 has decodes the complementary address signal a 0 to a m as described above, performs the selection operation of the word line in synchronization with the word line select timing signal .phi.x.

On the other hand, the column address buffer C-ADB has a column address strobe signal ▲ ▼ supplied from an external terminal.
An address signal A0 supplied from an external terminal in synchronization with the column address strobe signal ▲ ▼ is activated by a timing signal (not shown) formed by a timing generation circuit TG described later based on captures .about.An, convey to the column address decoder C-DCR to form the internal complementary address signal a 0 to a m holds it.

The column decoder C-DCR controls the column selection timing by the data line selection timing signal φy and has a complementary address composed of the internal address signals a0 to an supplied from the column address buffer C-ADB and the address signals 0 to n of opposite phase. forming a selection signal to be supplied to the column switch C-SW by decrypting the signal a 0 to a m.

In the figure, the row address buffer R-ADB
And the column address buffer C-ADB are collectively represented as address buffers R and C-ADB.

A precharge MOSFET Q44 which constitutes a precharge circuit similar to the above is provided between the common complementary data lines CD, ▴. A pair of input / output nodes of a main amplifier MA having a circuit configuration similar to that of the sense amplifier USA of the above unit is coupled to the common complementary data line CD ,.
The output signal of this main amplifier is the data output buffer DO.
It is sent to the external terminal Dout via B. If it is a read operation, the data output buffer DOB outputs its timing signal r
The operation signal is activated by w, and the output signal of the main amplifier MA is amplified and sent from the external terminal I / O. In the write operation, the output of the data output buffer DOB is set to the high impedance state by the timing signal φrw.

The common complementary data line CD, ▲ ▼ is connected to the output terminal of the data input buffer DIB. If it is a write operation,
The data input buffer DIB is activated by its timing signal φrw, and the complementary write signal according to the write signal supplied from the external terminal Din is transmitted to the common complementary data line CD, ▲ ▼ to select the selected memory. Writing to the cell is performed. If it is a read operation,
Data input buffer DI by the timing signal φrw
The output of B is put in a high impedance state.

In the write operation to the dynamic memory cell composed of the address selecting MOSFET Qm and the information storing capacitor Cs as described above, the information storing capacitor Cs is fully written. In other words, the address selecting MOSFET is
A word line bootstrap circuit (not shown) activated by the word line selection timing signal φx is provided in order to prevent a write high level level loss in the information storage capacitor Cs due to a threshold voltage such as Qm. It is provided. This word line bootstrap circuit uses the word line selection timing signal φx and its delay signal to change the high level of the word line selection timing signal φx to the power supply voltage Vc.
Higher level than c.

The various timing signals described above are formed by the following timing generation circuit TG. The timing generation circuit TG forms the main timing signals and the like shown as the above representative. That is, the timing generation circuit TG receives the address strobe signals ▲ ▼ and ▲ ▼ supplied from the external terminals and the write enable signal ▲ ▼, and forms the above-mentioned series of various timing pulses.

The circuit signal REFC is an automatic refresh circuit, which includes a refresh address counter and a timer. The automatic refresh circuit REFC is not particularly limited, but the column address strobe signal ▲ ▼ is set to the low level before the row address strobe signal ▲ ▼ is set to the low level by the logic circuit which receives the address tostrobe signals ▲ ▼ and ▲ ▼. At this time, it is determined to be the refresh mode, and the refresh address signals a0 'to am' generated by the address counter circuit using the row address strobe signal (1) as a clock are transmitted. The refresh address signals a0 'to am' are transmitted to the row address decoder circuits R-DCR1 and R-DCR2 via the row address buffer R-ADB having a multiplexer function.
For this reason, the refresh control circuit REFC generates a control signal (not shown) for switching the address buffer R-ADB in the refresh mode. As a result, the refresh operation is executed by selecting one word line corresponding to the refresh address signals a0 'to am' (CAS before RAS refresh).

In this embodiment, in order to increase the relative level margin between the half precharge voltage as the read reference voltage and the holding voltage of the memory cell, which fluctuates according to the fluctuation of the power supply, the information storage capacitor forming the memory cell is formed. Cs
The plate voltage VG set to Vcc / 2 which is almost the same as the half precharge voltage is supplied to the gate (plate). The plate voltage VG is formed by the voltage generation circuit VGG.

In the half precharge method, since the floating complementary data line is short-circuited at the end, if the chip non-selection period is lengthened, the drain leakage current of the address selecting MOSFET coupled to the complementary data line, etc. Will cause the level to drop. Therefore, in this embodiment, the voltage VG is used also for the level compensation. That is, the voltage VG is supplied to the one common source line NS in each unit circuit USA through the switch MOSFET Q50. A switch MOSFET Q51 is provided between the common source line NS and one data line. These switch MOSFETs Q50 and Q51 are turned on only during the precharge period by supplying the precharge signal φpc to their gates. As a result, during the chip non-selection period (precharge period), the voltage VG is supplied to the data line via the switch MOSFETs Q50 and Q51.
At this time, since the data line is connected to the other data line D by the precharge MOSFET Q5, both data lines are
It is possible to perform level compensation by the leakage current of the precharge voltage of D ,. Instead of the above configuration, the other data line D has a switch MOSFET similar to the switch MOSFET Q51.
By providing, the level compensation voltage VG may be supplied more evenly to both the complementary data lines D. A switch MO having the gate supplied with the precharge signal φpc is connected between the common source lines NS and PS.
The SFETQ49 is provided, and the sense amplifier is provided during the precharge period as in the precharge operation of the complementary data line D.
The common source lines NS and PS of SA are set to a half precharge potential.

FIG. 2 shows a circuit diagram of an embodiment of the voltage generating circuit VGG.

Between the power supply voltage Vcc and the voltage dividing point (Vcc / 2), a P-channel MOSFET 52 is connected in series with a diode-type N-channel MOSFET 53 whose drain and gate are commonly connected. Between the voltage dividing point (Vcc / 2) and the ground potential Vss of the circuit, a diode-type P-channel MOSFET Q54 and N-channel MOSFET Q55, whose gates and drains are commonly connected
And are connected in series. P-channel MOSFET Q52 and N
Although not particularly limited, the gate of the channel MOSFET Q55 is operated as a resistance means by being connected to the voltage dividing point Vcc / 2. These MOSFETs Q52 and Q55
Is set to a small value, so that the current value of the direct current flowing therethrough is set to a small value.

The common gate and drain of the diode type N-channel MOSFET Q53 is the same as the N-channel output MOSFET Q5.
It is supplied to the 6th gate. The common gate and drain of the diode-type P-channel MOSFET Q54 are supplied to the gate of the P-channel output MOSFET Q57. The drains of these output MOSFETs Q56 and 57 are connected to the power supply voltage Vcc and the ground potential of the circuit, and
The sources are connected together to deliver the output voltage VG.

To prevent direct current (through) current from flowing through both output MOSFETs Q56 and Q57, in other words, to prevent both MOSFETs Q56 and Q57 from being turned on at the same time by the divided voltage Vcc / 2. , The threshold voltage Vthn1 of the MOSFET Q53 is set to be smaller in absolute value than the threshold voltage Vthn2 of the corresponding output MOSFET Q56,
The threshold voltage Vthp1 of the OSFET Q54 is set to be absolutely smaller than the threshold voltage Vthp2 of the corresponding output MOSFET Q57.

Therefore, for example, when the output voltage VG is Vcc / 2, the output MOSFE
The source voltage of TQ56 is set to Vcc / 2. On the other hand, the gate voltage thereof is set to a voltage Vcc / 2 + Vthn1 obtained by level-shifting the divided voltage of Vcc / 2 above the threshold voltage of the diode type MOSFET Q53. In this situation,
The MOSFET Q56 has a threshold voltage Vt of the MOSFET Q53 which is smaller than its threshold voltage Vthn2 between its gate and source.
It is turned off because only hn1 is applied. This also applies to the P-channel output MOSFET Q57. As a result, both output MOSFETs Q56 and Q57 are turned off, so that no direct current flows through both MOSFETs Q56 and Q57.

Due to the rise of power supply voltage Vcc, the above voltage VG is output MOSFET Q
When the gate voltage of 56 (Vcc / 2 + Vthn1) is lowered relatively and the difference voltage is made larger than Vthn2, the MOSFE
TQ56 is turned on and output voltage VG is changed to Vcc / 2 ＋ Vthn1－Vt
Increase to hn2. At this time, the output MOSFET Q57 maintains an off state as a result of deeper reverse bias between the gate and the source thereof as the gate voltage (Vcc / 2−Vthp1) rises.

Due to the decrease of power supply voltage Vcc, the above voltage VG is output MOSFET Q
When the gate voltage of 57 (Vcc / 2-Vthp1) is made relatively high and the difference voltage is made larger than Vthp2, the MOSFE
TQ57 is turned on. By turning on this MOSFET Q57, the output voltage VG is lowered to Vcc / 2−Vthp1 + Vthp2. When the power supply voltage Vcc drops in this way, the N-channel MOSFET Q56 is turned on by its gate voltage (Vcc / 2 + Vthp
With the decrease in 1), the gate and source are deeply reverse biased, and as a result, the off state is maintained.

If the voltage VG fluctuates due to leakage current when the power supply voltage Vcc is constant, the fluctuation is compared with the threshold voltage Vthn1 of the corresponding MOSFET Q53 and Q56 with reference to the divided voltage Vcc / 2. When the difference between the threshold voltage Vthn2 and the threshold voltage Vthp1 between the MOSFETs Q54 and Q57 is exceeded, the respective output MOSFET Q56 or Q57 is turned on, and the level compensation is performed.

Both the output MOSFETs Q56 and Q57 are not turned on at the same time, and their operating currents are all output currents. Therefore, it is possible to set a large conductance of the output MOSFETs Q56 and Q57 and reduce a large output current, in other words, an output impedance.

[Embodiment 2] FIG. 3 shows a circuit diagram of another embodiment of the voltage generating circuit VGG.

In this embodiment, resistance elements R1 and R2 are used instead of the MOSFETs Q52 and Q55 shown in FIG. These resistive elements
Although not particularly limited, R1 and R2 are formed of a polysilicon layer having a high resistance value. In this embodiment, since the divided voltage is formed, the divided voltage having a high accuracy according to the pattern ratio (for example, Vcc is not affected by the process variation of the absolute resistance value of each polysilicon layer). /
2) can be formed.

[Effect]

(1) A source follower type N-channel output MOSFET and a P-channel output MOSFET are connected in series to obtain an output voltage from a common source point, and at the gates of both output MOSFETs,
Both of the above MOSFETs are level-shifted and supplied by a diode of the same conductivity type that has a threshold voltage that is larger in absolute value than the threshold voltage of each output MOSFET. It is possible to prevent a direct current from flowing between them. This allows the output MOSF
Since all the current flowing through the ET can be used as the output current, it is possible to obtain an effect that it is possible to obtain a voltage generating circuit with low power consumption and a large output current.

(2) Since the voltage generating circuit with low power consumption can be configured, the plate voltage (gate voltage of MOS capacitor) of the memory cell of the dynamic RAM of the half precharge system can be used without compromising the low power consumption. Can be equal to As a result, the reference voltage of the information storage capacitor can be changed by following the half precharge voltage (reading reference voltage) that changes corresponding to the fluctuation of the power supply voltage Vcc. As a result, the voltage held in the information storage capacitor due to fluctuations in the power supply changes in accordance with the half precharge voltage, so that the level margin can be increased.

(3) From the above (2), the technical problem of deterioration of the operation margin for the power supply bump, which is a major obstacle in adopting the half-precharge type dynamic RAM, can be solved at once, and thus its characteristic feature is low power consumption. , Dynamic type with a large storage capacity that takes advantage of low noise
The effect that RAM can be obtained is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. Nor. For example, a diode-type MOSFET in a voltage generator and its corresponding output
As a method of making the threshold voltage different from that of the MOSFET, various embodiments such as making the channel length of the MOSFET different and making the film pressure of the gate insulating film different can be adopted. Further, the output voltage formed by the voltage generating circuit is set according to its application.

Various embodiments can be adopted as a concrete circuit configuration of the other peripheral circuits constituting the dynamic RAM. For example, the address signals may be supplied from independent external terminals. The automatic refresh circuit is not particularly required.

[Field of application]

This invention is a dynamic type of half precharge system.
In addition to RAM, it can be widely used for various semiconductor integrated circuit devices including a voltage generating circuit that forms an output voltage by dividing a power supply voltage.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a dynamic RAM to which the present invention is applied, FIG. 2 is a circuit diagram showing an embodiment of a voltage generation circuit thereof, and FIG. 3 is the voltage generation circuit. FIG. 4 is a circuit diagram showing another embodiment of the present invention, and FIG. 4 is a circuit diagram showing an example of a voltage dividing circuit considered prior to the present invention. M-ARY ... Memory array, PC ... Precharge circuit, S
A ... Sense amplifier, UAS ... Unit circuit, C-SW ... Column switch, R-ADB ... Row address buffer, CA
DB ... Column address buffer, R-DCR1, R-DCR2 ...
Row address decoder, C-DCR ... Column address decoder, MA ... Main amplifier, TG ... Timing generation circuit, REFC ... Automatic refresh circuit, DOB ... Data output buffer, DIB ... Data input buffer, VBG ... Substrate bias generator, VGG ... Voltage generator

Claims (3)

[Claims] 1. A first resistance means, a first conductivity type first MOSFET in the form of a diode, a second conductivity type second MOSFET in the form of a diode, and a second resistance means. A voltage divider circuit sequentially connected in series, and a first conductivity type first output MOSFET in which the gate is connected to a commonly connected gate and drain of the first MOSFET.
And a second output MOSFET of the second conductivity type in which the gate is connected to the commonly connected gate and drain of the second MOSFET.
And the threshold voltages of the first and second MOSFETs are set to be smaller in absolute value than the threshold voltages of the corresponding first and second output MOSFETs, respectively. Output MOSFET
A semiconductor integrated circuit device comprising a voltage generation circuit configured to obtain an output voltage from a common source of the above. 2. The semiconductor integrated circuit device is a dynamic RAM of a half precharge system, and the voltage generating circuit forms a voltage of about 1/2 of a power supply voltage and is composed of a MOS capacitor. Claim 1 characterized by supplying to the plate electrode of the capacitor for use in
The semiconductor integrated circuit device according to the paragraph. 3. A voltage generating circuit for level compensating for a leak current of a data line in a half precharge state, according to claim 1.
The semiconductor integrated circuit device according to the paragraph.