JPH06105488B2 - Waveform compensation circuit - Google Patents

Description

The present invention relates to a waveform compensation circuit in a read circuit system of a magnetic storage device such as a magnetic disk device.

[Conventional technology]

FIG. 4 is a block diagram showing an example of a conventional waveform compensating circuit shown in, for example, Proc. This is called a waveform equalizer circuit. In the figure, 1 is a waveform equalizer circuit, 2 is a delay line, 3 is a matching resistor for inputting the read waveform A of the delay line 2, and 4 is a delay line 2. Attenuation circuit 5 whose matching end is connected to the input is delay line 2
Is a differential amplifier circuit in which the reflection end of is connected to the positive input and the output of the attenuation circuit 4 is connected to the negative input, and outputs the read waveform D equalized.

Next, the operation will be described. FIG. 5 is an operation explanatory diagram of the write and read circuit system of the magnetic disk device, and FIG. 6 shows an example of each signal of the waveform equalization circuit 1.
First, the operation of the read circuit system will be described with reference to FIG.
The signal E is an example of a write current signal, and the signal A is a read waveform at this time. The read circuit system detects the peak of the read waveform A and produces a peak detection pulse F. Generally, it is considered that the read waveform A is obtained by superimposing an isolated read waveform read when the peaks are sufficiently separated from each other at the timing of recording. Therefore, when high-density recording is performed, isolated read waveforms interfere with each other, and a gap G occurs in the peak timing. This shift is called peak shift, and demodulation becomes impossible when the peak shift becomes large, but this limit can be predicted by the amount of interference between isolated read waveforms. This amount of interference depends on the spread of the isolated read waveform, but this spread can be expressed by the half-value width of the isolated read waveform. The waveform equalization circuit 1 removes the tail of an isolated read waveform and reduces the peak shift that occurs in the read waveform.

Next, the operation of the waveform equalization circuit 1 of FIG. 4 will be specifically described with reference to FIG.

When the isolated read waveform A is input, the read waveform B delayed by the delay line 2 by a predetermined amount is generated at the reflection end of the delay line 2. The reflected read waveform is combined with the input waveform at the matching end of the delay line 2 and input to the attenuation circuit 4. Differential amplifier circuit 5
Outputs the subtracted output waveform C attenuated by the attenuator circuit 4 from the read waveform B delayed by the delay line 2. Attenuation circuit 4
The output waveform C of 1 has an amplitude similar to that of the isolated read waveform B at two time points separated from each other by a certain time or more from both sides of the peak of the isolated read waveform B, and thus is equalized by the differential amplifier circuit 5. The read waveform D has a small amplitude in the tail portion of the isolated read waveform B. Therefore, the equalized read waveform D reduces interference between adjacent waveforms. However, the output waveform C of the attenuating circuit 4 does not have an amplitude of 0 even near the peak of the isolated read waveform B, so the peak amplitude I of the equalized read waveform D is the peak of the isolated read waveform B. The amplitude becomes smaller than the amplitude H, and the signal-to-noise ratio deteriorates.

[Problems to be solved by the invention]

Since the conventional waveform equalization circuit is configured as described above, the waveform equalization has to subtract the waveform synthesized by using the input waveform from the input waveform. There is a problem that deterioration of the noise-to-noise ratio cannot be avoided.

The present invention has been made to solve the above problems, and an object thereof is to obtain a waveform compensating circuit capable of reducing the peak shift without deteriorating the signal-to-noise ratio.

[Means for solving problems]

The waveform compensating circuit according to the present invention includes a peak detection window pulse generating circuit that outputs a peak detection window pulse that becomes true when the absolute value of the amplitude of the read signal is equal to or greater than a predetermined value, and the peak detection window pulse is true. When the peak of the read signal is detected, a peak detection circuit that outputs a peak detection pulse that becomes true, and the time interval from the time when the peak detection window pulse becomes true to the time when the peak detection pulse becomes true and the peak detection pulse are Compensation amount detection circuit that detects the time interval from the time when it becomes true to the time when the peak detection window pulse becomes false and outputs this time difference as a compensation amount, and the delay amount of the peak detection pulse according to this compensation amount. And a phase compensation circuit that outputs a peak detection pulse that is changed and compensated within a predetermined range.

[Action]

The compensation amount detection circuit according to the present invention includes a time interval from the time when the peak detection window pulse becomes true to the time when the peak detection pulse becomes true and the time point when the peak detection window pulse becomes false from the time when the peak detection pulse becomes true. By detecting the time interval up to and outputting this time difference as a compensation amount, the direction and magnitude of the peak shift occurring in the peak detection pulse are output to the phase compensation circuit. The delay time of the detection pulse is changed within a predetermined range to compensate for the timing shift of the peak detection pulse.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. First
FIG. 1 is a configuration diagram showing a waveform compensation circuit according to an embodiment. In the figure, 6 is an automatic gain control amplifier circuit for making the peak amplitude of a read waveform substantially constant, and 7 is an amplitude of a read waveform A whose peak amplitude is almost constant. A peak detection window pulse generation circuit that outputs a peak detection window pulse J that becomes true when the absolute value of is greater than a certain value. Reference numeral 8 indicates a read waveform A by inputting the read waveform A and the peak detection window pulse J. It is a peak detection circuit that outputs a peak detection pulse F corresponding to the peak time. Reference numeral 9 denotes a compensation amount detection circuit that inputs the peak detection window pulse J and the peak detection pulse F and outputs the waveform compensation potential K as a compensation amount. Reference numeral 10a indicates charging at the time when the peak detection window pulse J becomes true and then peaks. The first charging / discharging circuit 10b starts discharging when the detection pulse F becomes true, 10b starts charging when the peak detection pulse F becomes true, the peak detection window pulse J becomes false, and the output of the knot gate 12 becomes true. The second charge / discharge circuit that starts discharging at a certain time, 11a is a first sample / hold circuit that samples / holds the output R of the first charge / discharge circuit 10a when the peak detection pulse F becomes true, and 11b is a When the peak detection window pulse J becomes false and the output of the knot gate 12 becomes true, the second charge / discharge circuit 10
The second sample / which samples / holds the output S of b
A hold circuit, which is the first sample / hold circuit 11
The output of a is the positive input of the differential amplifier circuit 5, the second sample /
The output of the hold circuit 11b becomes a negative input and the waveform compensation potential K is output. On the other hand, 13 receives the waveform compensation potential K and the peak detection pulse F, and outputs the compensated peak detection pulse Q by changing the delay amount of the peak detection pulse F within a predetermined range according to the waveform compensation potential K. 14a is a first reference potential generating circuit that outputs a positive reference potential L, and 14b is a negative reference potential M.
The second reference potential generating circuit 15a outputs the first compensation amount control signal 15a which receives the waveform compensation potential K and the positive reference potential L as input and becomes true when the waveform compensation potential K is higher than the reference potential L.
The first voltage comparator that outputs Ta, 15b is the waveform compensation potential K
And a negative reference potential M are input to output a second compensation amount control signal Tb which is true when the waveform compensation potential K is lower than the reference potential M, and 16 is a first compensation amount. Control signal Ta
And a second compensation amount control signal Tb are input to output a third compensation amount control signal Tc that is true when both are false, and 17 is a peak detection pulse F input to delay time τ + τ
_{The first} delay peak detection pulse N with ₁ (τ ₁ > 0), the second delay peak detection pulse O with delay time τ−τ ₂ (τ ₂ > 0), and the third delay peak detection pulse with delay time τ A tapped delay line for outputting P and 18 are input with the first to third compensation amount control signals Ta to Tc and the first to third delayed peak detection pulses N to P to perform the first compensation amount control. When the signal Ta is true, the first delayed peak detection pulse N is output. When the second compensation amount control signal Tb is true, the second delayed peak detection pulse O is output.
Is a gate circuit that outputs the third delayed peak detection pulse N as a compensated peak detection pulse Q when the compensation amount control signal Tc is true, and includes AND gates 18a to 18c and an OR gate 18d.

Next, the operation will be described. FIG. 2 is an operation explanatory diagram of the write and read circuit system of the magnetic disk device, and FIG. 3 shows an example of each signal of the compensation amount detection circuit 9. First, the operating principle of the present invention will be described with reference to FIG. As described above, the read waveform A corresponding to the write current E causes the peak shift G when high density recording is performed. The peak detection circuit 8 needs a peak detection window pulse J that becomes true only at the time when a peak is considered to be present so that the peak is not mistakenly detected by noise when detecting the peak of the read waveform A. The peak detection window pulse J becomes true when the amplitude of the read waveform A is larger than a certain value Z. Generally, the peak shift G occurs when there is a difference in time interval between the peak causing the peak shift G and the peaks before and after the peak. The read waveform A is considered to be a superposition of isolated read waveforms each having a peak at each inversion time of the write current E, and peak shift occurs when interference occurs between these isolated read waveforms. Normally, an isolated read waveform is a symmetrical waveform centered on a peak. Therefore, when the peak interval between a certain isolated read waveform and the isolated read waveform before and after it is the same, interference with the isolated read waveform before and after Although the amounts are the same and there is no peak shift, if there is a difference in the peak intervals, a difference also occurs in the interference amount, resulting in a peak shift.

Generally, when performing high-density recording, since the peak time interval is as small as the half-value width of an isolated read waveform, the slope before and after the peak of the read waveform correlates with the time interval with the preceding and following peaks. That is, if the difference in inclination before and after a certain peak of the read waveform is known, the peak shift occurring in that peak can be predicted. When the read waveform near the peak is approximated by a triangle, the difference between the slopes of both hypotenuses is
It corresponds to the difference in the reciprocal of the length between the intersection of the vertex corresponding to the peak and the bottom when a line perpendicular to the bottom is drawn, and both the vertexes of the bottom. The difference between the reciprocals of this length is the time V from the time when the peak detection window pulse J in FIG. 2 becomes true to the time when the peak detection pulse F becomes true, and the peak from the time when the peak detection pulse F becomes true. This corresponds to the difference from the time W until the detection window pulse J becomes false. Therefore, the time V and the time W
The peak shift G can be predicted by detecting the difference between and, and appropriate compensation can be performed. Since this compensation does not need to directly add the read waveform A, the compensation can be performed without degrading the signal-to-noise ratio of the read waveform as in the waveform equalization circuit.

Next, the operation of the compensation amount detection circuit 9 will be specifically described with reference to FIGS. 1 and 3. As shown in FIG. 3, the first charge / discharge circuit 10a starts charging when the peak detection window pulse J becomes true, and starts discharging when the peak detection pulse F becomes true. The first sample / hold circuit 11b, to which the output signal R of the first charge / discharge circuit 10a is input, samples / holds the peak amplitude X of the signal R when the peak detection pulse F becomes true. This peak amplitude X is proportional to the time V. The other second charge / discharge circuit 10b
Starts to discharge when the peak detection pulse F becomes true, and starts discharging when the output of the knot gate 12 becomes true, that is, when the peak detection window pulse J becomes false. The second sample / hold circuit 11b, which receives the output signal S of the second charge / discharge circuit 10b as an input, samples the peak amplitude Y of the signal S at the time when the output of the knot gate 12 becomes true.
Hold on. The peak amplitude Y is proportional to the time W. The differential amplifier circuit 5 is the first sample / hold circuit.
A waveform compensation potential K obtained by subtracting the output of the second sample / hold circuit 11b from the output of 11a is output. Since the correct waveform compensation potential K is output after the peak detection window pulse J becomes false, the peak detection pulse F must be corrected to the maximum value Wmax of the time W in order to correctly compensate the peak detection pulse F.
You need to delay it by a longer time. At the time of the next peak detection pulse, the first sample / hold circuit
Since the output of 11a changes, the delay time of the peak detection pulse F must be shorter than the minimum value Tpmin of the intervals of the peak detection pulses. First sample / hold circuit 11
When the output of a is larger than the output of the second sample / hold circuit 11b, it corresponds to the case where the time V is longer than the time W, so the slope after the peak is larger than the slope before the peak, and the peak is It is considered that it appears earlier than the timing of writing. That is, when the waveform compensation potential K is positive, the peak detection pulse F must be compensated in the direction of being delayed. When the waveform compensation potential K is negative,
On the contrary, the peak detection pulse F must be compensated in the forward direction.

Next, the operation of the phase compensation circuit 13 will be described with reference to FIG.

The phase compensation circuit 13 classifies the waveform compensation potential K into three types,
The delayed peak detection pulse delayed by the corresponding delay time is output as the compensated peak detection pulse Q. The first voltage comparator 15a makes the first compensation amount control signal Ta true when the waveform compensation potential K is higher than the positive reference potential L. Further, the second voltage comparator 15b makes the second compensation amount control signal Tb true when the waveform compensation potential K is lower than the negative reference potential M. Further, the NOR gate 16 is configured such that when both the first compensation amount control signal Ta and the second compensation amount control signal Tb are false, that is, the waveform compensation potential K is lower than the positive reference potential L and the negative reference potential M. When it is higher, the third compensation control signal Tc becomes true. The gate circuit 18 selects and compensates the three types of delayed peak detection pulses N, O, P which are the outputs of the tapped delay line 17 corresponding to the three types of compensation amount control signals Ta, Tb, Tc. Output as peak detection pulse Q. That is, when the waveform compensation potential K is positive and sufficiently high, the peak detection pulse F is delayed and output by τ + τ _1, and when the waveform compensation potential K is negative and sufficiently low, the peak detection pulse F is τ−τ.
_The output is delayed by ₂ and when the waveform compensation potential K is close to 0, the peak detection pulse F is delayed by τ and output to compensate the timing by + τ ₁ or −τ ₂ .
Note that, as described above, τ, τ ₁ and τ ₂ are limited due to the operating conditions of the compensation amount control signal 9. If this is shown below, τ−τ ₂ > Wmax τ + τ ₁ <Tpmin.

〔The invention's effect〕

As described above, according to the present invention, the waveform compensation circuit outputs the peak detection window pulse that becomes true when the absolute value of the amplitude of the read signal is equal to or more than the predetermined value, and the peak detection window pulse generation circuit. A peak detection circuit that outputs a peak detection pulse that becomes true when the peak of the read signal is detected when the detection window pulse is true, and the time from the time when the peak detection window pulse becomes true to the time when the peak detection pulse becomes true. A compensation amount detection circuit that detects the time interval from the time when the interval and the peak detection pulse are true to the time when the peak detection window pulse is false and outputs this time difference as a compensation amount.
A phase compensation amount circuit that changes the delay amount of the peak detection pulse within a predetermined range according to this compensation amount and outputs the compensated peak detection pulse, and performs waveform compensation without degrading the amplitude of the read waveform. Therefore, the peak shift can be reduced without deteriorating the signal-to-noise ratio.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a waveform compensating circuit according to an embodiment of the present invention, FIG. 2 is an operation explanatory diagram of a write and read circuit system of a magnetic disk device, and FIG. 3 is a diagram showing signals of a compensation amount detecting circuit. FIG. 4 shows an example, FIG. 4 is a circuit configuration diagram of a waveform equalization circuit which is a conventional waveform compensation circuit, FIG. 5 is an operation explanatory diagram of a write / read circuit system of a magnetic disk device, and FIG. 6 is a conventional waveform. It is a figure which shows an example of each signal of the waveform equalization circuit which is a compensation circuit. 5 is a differential amplifier circuit, 6 is an automatic gain control amplifier circuit, 7 is a peak detection window pulse generation circuit, 8 is a peak detection circuit, 9 is a compensation amount detection circuit, 10a is a first charge / discharge circuit, and 10b is a second circuit. Charge / discharge circuit, 11a is the first sample / hold circuit, 11b
Is the second sample / hold circuit, 12 is the knot gate,
13 is a phase compensation circuit, 14a is a first reference potential generation circuit, 14b
Is a second reference potential generation circuit, 15a is a first voltage comparator, 1
5b is a second voltage comparator, 16 is a NOR gate, 17 is a delay line with taps, and 18 is a gate circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] 1. A waveform compensating circuit for compensating for a timing shift of a peak detection pulse due to waveform interference of a read signal in a magnetic memory device, wherein a peak that becomes true when the absolute value of the amplitude of the read signal is a predetermined value or more. A peak detection window pulse generation circuit that outputs a detection window pulse, a peak detection circuit that outputs a peak detection pulse that becomes true when the peak of the read signal is detected when this peak detection window pulse is true, and the peak detection window pulse The time interval from the time when the peak is true to the time when the peak detection pulse is true and the time interval from the time when the peak detection pulse is true to the time when the peak detection window pulse is false are detected, and this time difference is used as the compensation amount. Compensation amount detection circuit to output, and the peak amount compensated by changing the delay amount of the peak detection pulse within a predetermined range according to the compensation amount. Waveform compensation circuit, characterized in that consisted phase compensation circuit for outputting as output pulses. 2. The compensation amount detection circuit starts charging when the peak detection window pulse becomes true, and starts discharging when the peak detection pulse becomes true, and the peak detection pulse becomes true. The first sample / hold circuit that samples / holds the potential of the first charging / discharging circuit, and the charging starts when the peak detection pulse becomes true, and discharges when the peak detection window pulse becomes false. A second charge / discharge circuit for starting, a second sample / hold circuit for sampling / holding the potential of the second charge / discharge circuit when the peak detection window pulse becomes false, and the first sample / hold circuit And a differential amplifier circuit that subtracts the output potential of the second sample / hold circuit from the output potential of the second amplification circuit and outputs the waveform compensation potential, and the phase compensation circuit outputs a positive reference potential. Position generating circuit, a second reference potential generating circuit that outputs a negative reference potential, and a first voltage that outputs a first compensation amount control signal that is true when the waveform compensation potential is higher than the positive reference potential. A comparator, a second voltage comparator that outputs a second compensation amount control signal that becomes true when the waveform compensation potential is lower than a negative reference potential, and both the first and second compensation amount control signals. A NOR gate that outputs a third compensation amount control signal that is true when false, a first delayed peak detection pulse having a delay time τ + τ ₁ by inputting the peak detection pulse, and a _second delay peak τ−τ ₂ A delay line with a tap that outputs a delayed peak detection pulse and a third delayed peak detection pulse having a delay time τ; and a first delayed peak detection pulse when the first compensation amount control signal is true, When the compensation amount control signal is true, the second delay peak detection pattern 2. A gate circuit for outputting the third delay peak detection pulse as a compensated peak detection pulse when the third compensation amount control signal is true, respectively. Waveform compensation circuit.