JPH06105550B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device, and more particularly to prevention of read error when reading data.

[Conventional technology]

As a conventional semiconductor memory device of this type, there is one having a circuit whose configuration is shown in FIG.

In the figure, BL, ▲ ▼ are paired bit lines, WL ₀ , W
L ₁ is a word line that intersects the bit line in a matrix, Cs ₀ ,
Cs ₁ represents memory cells arranged at the intersections thereof, and T _G0 and T _G1 represent transfer gates having word lines connected to the gates and switching between the bit lines and the memory cells Cs. DWL ₀ and DWL ₁ are dummy word lines intersecting the bit line, C
_D0 , C _D1 are dummy cells placed at those fulcrums, T _D0 , T
_D1 represents a dummy gate which is connected to the gate with a dummy word line and switches between the bit line and the dummy cell C _D.
The dummy gates connected to each of the bit line pairs and switching between the dummy cells C _D are shown. The dummy cell C _D connected to each bit line pair has a precharge voltage generator (PV
G) is connected between the bit line pairs, and a sense amplifier SA including a flip-flop circuit that amplifies the voltage generated between the bit line pairs is connected. In addition, the bit line pair selected according to the column address is connected to the data input / output line pair I / O, ▲
Transfer gates Q ₁ and Q ′ ₁ connected to ▼ are provided, and the output of the column decoder 2 is input to these gates.

In such a configuration, for example, when the word line WL ₀ is selected and this word line WL ₀ rises, the memory cell Cs ₀ connected to the bit line BL is selected, and the bit line ▲ ▼ on the side opposite to the bit line BL is selected. Connected dummy gate
T _D1 is turned on by the dummy word line DWL ₁ . Since the precharge voltage is already given to the dummy cells C _D0 and C _D1 , the precharge voltage is connected to the bit line ▲ ▼ connected to this dummy gate T _D1.
Given by C _D1 . The voltage thus generated between the pair of bit lines is amplified by the sense amplifier SA and the data is read.

[Problems to be solved by the invention]

However, since there is a stray capacitance as shown in FIG. 7 between the bit lines, a noise voltage is superimposed on the data voltage generated between the bit line pairs, which impairs the read signal voltage, lowers the operating margin, and causes malfunctions. .

In FIG. 7, a pair of Represents a bit line pair, C ₁ is the stray capacitance to the ground voltage (fixed potential) via the cell plate or substrate, and C ₂
Is the stray capacitance between the bit line pairs, and C ₃ is the stray capacitance for the bit lines of the adjacent bit line pairs.

Therefore, as shown in FIG. 8, each of the bit line pairs is intersected at two points, and the bit line pair is divided into three at this intersection, and the intersection of the adjacent bit line pairs is the center of the other division. As an example, a semiconductor memory device configured to be adjacent to is proposed. In the figure, parts that are the same as or correspond to those in FIG.

In FIG. 8, BLx, ▲ ▼ (x = 1,2,3) represents the above-mentioned bit line pair, and WLy, WLy ′ (y = 1,2,3) represents the word line. It is assumed that the transfer gate T _G and the memory cell Cs are connected to the mark “◯” indicated by the reference numeral 3 as in the case of FIG. The bit line pairs intersect at the points indicated by CP _{1 to} CP ₄ , and are divided into sections a, b, and
It is divided into c and d.

In the semiconductor memory device having such a configuration, each of the bit line pairs receives the same capacitive coupling noise from the adjacent bit line pairs, the two are canceled, and the noise voltage generated between the bit line pairs can be ignored. .

However, it is impossible to apply the precharge voltage to each bit line pair by applying the dummy word line and the dummy cell used in FIG. 6 to the semiconductor memory device in which the bit line pair is crossed as described above.

That is, the dummy word line DW shown by the alternate long and short dash line in FIG.
L ₀ , DWL ₁ , each of these bit line pairs using a dummy gate T _D and a dummy cell C _D (not shown) located at the mark “□” shown by reference numeral 4 and arranged at the intersection of these bit line pairs. The precharge voltage cannot be applied to all of the above.
Next, this will be described depending on the selected type of word line.

First, consider the case where a word line in section a is selected.
When the word line WL ₀ is selected, the dummy word line DWL ₁ may be raised so that the dummy cell existing on the bit line opposite to the bit line in contact with the memory cell arranged on this line is selected. For the word line WL ₀ ′, similarly, the dummy word line DWL ₀ may be raised.

Second, consider the case where a word line in section b is selected.
When word line WL ₁ is selected, bit line pair , The dummy word line DWL ₁ is selected so that the dummy cell existing on the opposite bit line on which the memory cell exists is selected.
Should be started, but the bit line pair For, the dummy word line DWL ₀ must be raised. Similarly for the word line WL ₁ ′, a different dummy word line must be raised for each bit line pair. When two dummy word lines are simultaneously activated for one word line in this way, all dummy cells are selected and normal selection of dummy cells becomes impossible.

Note that the word lines in the sections c and d also have the above first and second
It becomes similar to the case of.

In view of the above problems, the present invention is not affected by the capacitive coupling noise superimposed on the bit line at all, and it is possible to correctly apply the precharge voltage to the bit line pair in accordance with a certain law. It is an object of the present invention to provide a semiconductor memory device having no data read error.

[Means for solving problems]

The present invention forms a pair, each pair of bit lines intersecting each other, and four dummy word lines intersecting the bit line,
The semiconductor memory device includes a dummy cell arranged at the intersection of the bit line and the dummy word line, and a dummy word line selection system for selecting and connecting the dummy cell corresponding to the bit line on the side where the memory cell is not selected and connected. It is provided.

[Action]

Capacitive coupling noise is superposed equally on each bit line pair,
In addition, dummy cells corresponding to the selected memory cell can be obtained for all bit line pairs.

〔Example〕

Next, the present invention will be described with reference to the drawings. FIG. 1 is a first embodiment of the present invention, FIG. 2 is a second embodiment, and a third embodiment.
The figure is a block diagram showing a third embodiment. In the figure, the same or corresponding parts as those in FIG. 8 are designated by the same reference numerals and the description thereof is omitted.

In Fig. 1, DWL ₀ and DWL ₁ are intersections C at the ends of bit lines.
Two dummy word lines, DWL ₂ and DWL, which are arranged outside P _4.
Reference numeral ₃ represents two dummy word lines arranged inside this crossing point CP ₄ , and the dummy gate T _D and the dummy cell are placed at the positions indicated by the mark “□” at the intersections of the respective dummy word lines and bit lines. Let C _D exist.

FIG. 2 shows that the dummy word lines DWL ₀ and DWL ₁ are arranged inside the intersection CP ₄ and the dummy word lines DWL ₂ and DWL ₃ are arranged outside the intersection CP ₄ .

FIG. 3 shows that all of these four dummy word lines are arranged on one side of the intersection CP ₄ of the bit line pair ends.

Further, in these configuration diagrams, each section a to d is a row address which is a signal given from the outside of the semiconductor memory device.
It corresponds to the values of RAi and RAj (i ≠ j) as shown in the figure.

That is, it is as follows.

Category a: RAi = 0, RAj = 0 Category b: RAi = 0, RAj = 1 Category c: RAi = 1, RAj = 0 Category d: RAi = 1, RAj = 1 Also, each word line has a row address RAk. (K ≠ i, k ≠ j)
And correspond as follows. That is, row address RAk
"0" of corresponds to word lines WL ₀ , WL ₁ , WL ₂ , WL ₃ ,
"1", the word line _{WL 0 ', WL 1',} WL 2 ', WL 3' correspond to the. That is, one memory cell existing on each bit line pair on a specific word line in a specific section always corresponds to one logical combination created by three kinds of row addresses.

In such a configuration, if two of the four dummy word lines are selected as shown in Table 1 according to the word line selected by the row address, the selected memory cell will be properly formed. Corresponding dummy cells are obtained for all bit line pairs.

Table 1 can be applied to the above-mentioned three embodiments, and when the row address RAi, RAj, RAk is 0, 0, 0, the word line WL ₀ in the section a is selected and corresponds to this. This means that DWL ₁ and DWL ₃ should be selected as the dummy word lines. Others have the same meaning.

That is, in FIG. 1, FIG. 2 and FIG. 3, when the word line WL ₀ is selected, the bit line pair is selected. For, the memory cell in contact with the bit line BL ₀ is selected,
The dummy cell is the bit line on the opposite side of this bit line BL _0. You can choose the one that comes into contact with. Dummy word line is DWL ₁ , DWL
₃ is selected and the bit line pair Dummy word line DWL ₁
Since the one that is in contact with is selected, this matches the dummy cell described above and is a normal one. Bit line pair , The memory cell in contact with the bit line BL ₁ is selected, and the bit line is selected as the dummy cell corresponding to this memory cell. The one adjacent to is selected by the dummy word line DWL ₃ , which is in agreement with the normal one. The same is true for other bit line pairs.

This is the same even if the selected word line is of another section, and the dummy cell is selected by two dummy word lines which are different from each other in the adjacent bit lines.
A dummy cell corresponding to all the selected memory cells can be properly selected, and the precharge voltage can be applied to the correct bit line side.

A concrete implementation of such dummy word line selection is
FIG. 5 is a circuit diagram shown in FIG. 4.

In the figure, Aj and Ak represent address lines to which the row addresses RAj and RAk described above are input, and ▲ ▼ and ▲ ▼ represent address lines to which inverted signals of Aj and Ak are input. Reference numerals 5 and 6 are NOR circuits, 7 is a NOT circuit, 8 is a boosting transistor whose gate is lifted to the power supply potential, 9 is a transistor to which the dummy word line rising signal φ _R is input to the source, and 10 is a transistor 9 It is a transistor that switches in the opposite direction. Also, NOT circuit 7 and transistor
Dummy word lines DWL ₀ , DWL ₁ , DWL ₂ , and DWL ₃ are connected to the same circuit at four locations constituted by 8, 9, and 10 via resistors R, respectively.

In such a configuration, the addresses given to the address lines according to the row addresses RAj and RAk are decoded by the NOR circuits 5 and 6 and the NOT circuit 7. Dummy word line DWL
₀ , DWL ₁ , DWL ₂ , DWL ₃ and corresponding transistor 9 respectively
Called T ₀ , T ₁ , T ₂ , T ₃ , these are switched by the decoded address as shown in Table 2, and two dummy word lines for one address rise to the power supply voltage.

In Table 2, "○" indicates that the transistor is on, and "X".
Indicates off. As an example of how to read the table, for example, when the uppermost address line Aj = 0 and Ak = 0, that is, when the row address RAj = 0 and RAk = 0, the transistors T ₁ , T ₃
The gate of the gate turns to high level and turns on, and the dummy word line
DWL ₁ and DWL ₃ rise to the selected state as the dummy word line rise signal φ _R rises. Similarly, the dummy word lines are selected for the other ones according to Table 2.

In addition, although the above-mentioned three embodiments have been described as being divided into four sections (a, b, c, d) depending on the intersection of the bit line pairs, this is not limited to four sections, and is an integer of this. It may be doubled (for example, 8 divisions, 12 divisions, 16 divisions), and even in such a case, the dummy cells corresponding to all the selected memories can be properly selected by the four dummy word lines. The same effect as that of the above embodiment is obtained. this is,
Four dummy word lines are selected only by two row addresses RAj, RAk, and four combinations of these shown in Table 2 are divided into sections a and b, section c and This is because it is only repeated every two sections like d. FIG. 5 shows an example of the structure of the eight categories. Note that the reference numerals in the figure correspond to those in FIG. 1, and description thereof will be omitted.

Next, in the semiconductor memory device having such a configuration, capacitive coupling noise that each bit line pair receives from an adjacent bit line pair will be described. As an example, 4 shown in FIG.
A description will be given on behalf of those that are divided into two categories.

Bit line pair Received by the adjacent bit line pair Is given by the following equation. Incidentally, the reference numeral represented by adding a subscript to ΔV represents noise generated from the bit line indicated by the subscript.

However, α and γ are shown as follows from the stray capacitance generated in this semiconductor memory device as in FIG. 7.

The first term, the second term, the third term, and the fourth term in parentheses on the right side of both equations representing the above noise correspond to the categories a, b, c, and d. In this way, the noises shown in both equations are exactly the same. The same applies to other bit line pairs.

Therefore, the potential difference appearing between the bit line pair has no influence from the noise because these noises are equally superimposed on both bit line pairs. The same can be said for things such as 8 categories.

In all of the above embodiments, the case where the dummy cell connected to the bit line on the opposite side, which is paired with the bit line to which the selected memory cell is connected, is selected is selected. Even when a dummy cell connected to the same bit line as that to which the cell is connected is selected (dummy reversal method or the like), the same effect as that of the above embodiment is obtained.

〔The invention's effect〕

As described above, according to the present invention, bit lines forming a pair and intersecting each of the pairs, four dummy word lines intersecting with the bit line, and arranging at the intersections of the bit line and the dummy word line are arranged. The dummy memory cell and the dummy word line selection system for selecting and connecting the dummy cell corresponding to the bit line on the side where the memory cell is not selected and connected are provided in the semiconductor memory device. Coupling noise is superposed equally, and since dummy cells that correspond to the selected memory cell are obtained for all bit line pairs, there is no influence of capacitive coupling noise at all, and bit line pairs are not affected. In addition, there is an effect that a semiconductor memory device capable of correctly applying the precharge voltage according to a certain law and having no data read error is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment according to the present invention, FIG. 2 is a block diagram showing a second embodiment according to the present invention, and FIG.
FIG. 4 is a block diagram showing a third embodiment according to the present invention, FIG. 4 is a circuit diagram used for decoding a dummy word line applied to the first, second, and third embodiments, and FIG. FIG. 6 is a configuration diagram showing a fourth embodiment of the invention, FIG. 6 is a circuit diagram showing a conventional semiconductor memory device using dummy cells, FIG. 7 is a configuration diagram showing stray capacitance, and FIG. 8 is a conventional bit line pair. FIG. 3 is a configuration diagram showing a semiconductor memory device in which an intersection is provided in FIG. BLx, ▲ ▼ (x = 0,1,2,3) …… bit line, WLy, WL
y ′ (y = 0,1,2,3) …… Word line, CP ₁ , CP ₂ , CP ₃ , CP ₄ ….
... Crossing points, 1 ... Sense amplifier, 3 ... Transfer gate and memory cell, 4 ... Dummy gate and dummy cell.

Claims (4)

[Claims] 1. A pair, each pair of which intersects and divides the pair at this intersection, and the intersection of the adjacent pair is a bit line adjacent to the center of another division, and this bit line. Word lines intersecting in a matrix, memory cells arranged at intersections of these bit lines and word lines, four dummy word lines intersecting with the bit lines, and intersections of these bit lines and dummy word lines. Dummy cells that are arranged,
A dummy word line selection system for selecting and connecting a dummy cell corresponding to a bit line on the side where the memory cell of the dummy cells connected to each of the bit line pair is not selected and connected, and a connection between the bit line pair A semiconductor memory device including a sense amplifier that amplifies the voltage generated between the pair of bit lines. 2. A dummy cell is selected by a dummy word line of any two of these four dummy word lines for a certain bit line pair, and a bit line adjacent to this bit line pair is selected. 2. The semiconductor memory device according to claim 1, wherein the dummy cell is selected by the other two dummy word lines for the other pair. 3. The four dummy word lines, two of which are arranged outside the intersection of bit line pair ends and the other two of which are arranged inside the intersection. Range second
The semiconductor memory device according to the item. 4. The semiconductor memory device according to claim 2, wherein all of the four dummy word lines are arranged on one side of the intersection of bit line pair ends.