JPH06105675B2 - Method of forming flat resist film - Google Patents
Method of forming flat resist filmInfo
- Publication number
- JPH06105675B2 JPH06105675B2 JP62232822A JP23282287A JPH06105675B2 JP H06105675 B2 JPH06105675 B2 JP H06105675B2 JP 62232822 A JP62232822 A JP 62232822A JP 23282287 A JP23282287 A JP 23282287A JP H06105675 B2 JPH06105675 B2 JP H06105675B2
- Authority
- JP
- Japan
- Prior art keywords
- resist
- film
- thin film
- forming
- flat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Photosensitive Polymer And Photoresist Processing (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、凹凸段差を有する基板上に平坦なレジスト薄
膜を形成する方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for forming a flat resist thin film on a substrate having uneven steps.
従来の技術 従来、半導体素子の高集積化に伴い、パターン形成の微
細化や、微細パターン形成のための平坦化の技術的改善
が図られている。2. Description of the Related Art Conventionally, as semiconductor elements have been highly integrated, technical improvements have been made in fine pattern formation and in planarization for fine pattern formation.
従来のレジスト膜形成方法では、第３図Ａのような凹凸
段差を有する基板31において、第３図Ｂおように幅の広
い凹部にレジストパターン32を形成し凹部の幅を所望の
幅以下にする。次にレジスト薄膜33を形成し表面を平坦
にし、平坦なレジスト膜を形成するというものである。According to the conventional resist film forming method, a resist pattern 32 is formed in a wide concave portion as shown in FIG. 3B on a substrate 31 having uneven steps as shown in FIG. 3A so that the width of the concave portion is equal to or smaller than a desired width. To do. Next, a resist thin film 33 is formed, the surface is made flat, and a flat resist film is formed.
発明が解決しようとする問題点 しかし、第３図に示した従来の形成方法では、レジスト
パターン32の形成後にも深い溝がそのまま残っているた
め、次の薄いレジスト薄膜33を形成しても溝上部でレジ
ストの窪みができ平坦化されない。また、凹部の疎密に
よっても、レジスト薄膜33が変化する。つまり、レジス
トパターン32を形成した後に残る溝部の密度が高くなる
ほどレジスト薄膜33が薄くなり全体を均一にできない。
レジスト薄膜33の窪みや、膜厚の不均一によりマスク露
光による微細パターン形成の際には、パターン線幅が異
なるという問題を生じ、レジスト薄膜を用いたエッチバ
ックによる下地素子の平坦化では、レジスト薄膜33の表
面形状がそのまま転写されるため一様に平坦化すること
ができないうえ、膜厚が不均一のため、エッチバックの
エッチング量が異なるという問題を生じる。However, in the conventional forming method shown in FIG. 3, since the deep groove remains as it is even after the resist pattern 32 is formed, even if the next thin resist thin film 33 is formed, the groove on the groove is not formed. There is a dent in the resist at the part and it is not flattened. The resist thin film 33 also changes depending on the density of the recesses. In other words, the higher the density of the groove portions remaining after forming the resist pattern 32, the thinner the resist thin film 33, and it becomes impossible to make the whole uniform.
When the fine pattern is formed by mask exposure due to the depression of the resist thin film 33 or the non-uniformity of the film thickness, there arises a problem that the pattern line width is different. Since the surface shape of the thin film 33 is directly transferred, it cannot be flattened uniformly, and the film thickness is not uniform, which causes a problem that the etching amount of the etch back is different.
またレジスト薄膜33により、平坦でかつ均一な膜厚にし
ようとすると非常に厚く形成せねばならず、微細パター
ン形成には適応できず、素子の平坦化に用いる際もエッ
チバックの面内均一性が著しく要求されるので困難とな
る。In addition, if the resist thin film 33 is used to form a flat and uniform film, it must be formed to be extremely thick, and it cannot be applied to the formation of a fine pattern. Is extremely required, which makes it difficult.
問題点を解決するための手段 本発明の平坦なレジスト膜の形成方法は、一主面上に凹
凸パターンを有する基板に第１のレジスト薄膜を形成す
る工程と、前記第１のレジスト薄膜を所望の量エッチバ
ックして除去する工程と、この第１のレジスト薄膜上に
第２のレジスト薄膜を形成する工程を含み、凹凸パター
ン面に平坦かつ均一な膜厚のレジスト薄膜を形成するよ
うにしたものである。Means for Solving the Problems A method for forming a flat resist film according to the present invention comprises a step of forming a first resist thin film on a substrate having a concavo-convex pattern on one main surface, and the first resist thin film is desired. And a step of forming a second resist thin film on the first resist thin film to form a resist thin film having a flat and uniform thickness on the uneven pattern surface. It is a thing.
作用 本発明は、上記構成により、以下のように作用する。Action The present invention acts as follows with the above configuration.
第１のレジスト薄膜を形成し、凹部を埋めて表面を
ほぼ平坦にした後に、エッチバックにより第１のレジス
ト薄膜を適量除去することにより、凹部段差を軽減でき
る。その上に第２のレジスト薄膜を形成するので、第２
のレジスト薄膜を薄くしても、表面を平坦にすることが
できるうえ、基板凹部密度による第２のレジスト薄膜の
膜厚変化を小さくできる。By forming a first resist thin film, filling the recesses to make the surface substantially flat, and then removing an appropriate amount of the first resist thin film by etch back, the recess step can be reduced. Since the second resist thin film is formed on it, the second
Even if the resist thin film is thinned, the surface can be made flat and the change in film thickness of the second resist thin film due to the substrate recess density can be reduced.
第２のレジスト薄膜を薄くかつ平坦で均一な膜厚に
できるので、以後の工程でマスク露光による微細パター
ン形成が精度良く行なうことができる。また、エッチン
グによる素子の平坦化に用いる場合もバラツキがなく平
坦にすることができる。Since the second resist thin film can be made thin, flat, and uniform in thickness, a fine pattern can be accurately formed by mask exposure in the subsequent steps. Further, even when it is used for flattening an element by etching, it can be flattened without variation.
実施例 以下、本発明の平坦なレジスト膜形成方法を実施例にも
とづいて説明する。Examples Hereinafter, a method for forming a flat resist film of the present invention will be described based on Examples.
（第１実施例） 第１図は本発明の第１の実施例を説明するための工程断
面図であり、まずＡに示すような凹凸パターン（例えば
深さ１μｍ程度）の形成された基板11上に、マスク露光
などを用いて幅の広い凹部（例えば幅２μｍ以上となる
凹部）にレジストパターン12（例えば膜厚１μｍ）を形
成して、凹部の溝幅をすべて所定の幅（例えば１μｍ）
以下としてＢを得る。次にＣのように第１のレジスト薄
膜としてレジスト膜13（例えば膜厚１μｍ程度）を形成
する。この段階では、前の従来の技術での問題点で述べ
たように、溝部ではレジスト膜13上に窪みができるほ
か、溝部の密度の疎密により、レジスト膜13の膜厚が異
なっている（上記の寸法で行なった際、段差が0.3μｍ
程度、膜厚の差が0.3μｍ程度）。次に、エッチバック
によりＤのように凸部上のレジスト膜13をすべて除去す
る。これにより凹部のレジスト膜13は低くなる（0.3μ
ｍ程度）。さらに、第２のレジスト薄膜としてのレジス
ト膜１所望（例えば膜厚１μｍ程度）を形成して第１図
Ｅを得る。レジスト膜13をエッチバックしてＤを得た段
階で表面上の段差は軽減されているため溝部でのレジス
ト膜14の窪む量を著しく減少（0.1μｍ以下）するとと
もに、溝部密度による膜厚の変化もほとんど生じない
（0.1μｍ以下）。よって、非常に平坦で、膜厚の均一
なレジスト膜の形成ができる。(First Embodiment) FIG. 1 is a process sectional view for explaining a first embodiment of the present invention. First, a substrate 11 having an uneven pattern (for example, a depth of about 1 μm) as shown in A is formed. A resist pattern 12 (for example, a film thickness of 1 μm) is formed on a wide recess (for example, a recess having a width of 2 μm or more) by using mask exposure or the like, and the groove width of the recess is set to a predetermined width (for example, 1 μm).
B is obtained as follows. Next, as in C, a resist film 13 (for example, a film thickness of about 1 μm) is formed as a first resist thin film. At this stage, as described in the problem in the prior art described above, in addition to the formation of depressions on the resist film 13 in the groove portion, the film thickness of the resist film 13 is different due to the uneven density of the groove portion (above). The step size is 0.3 μm
Difference of about 0.3 μm). Next, by etching back, the resist film 13 on the convex portions as shown by D is entirely removed. As a result, the resist film 13 in the recess is lowered (0.3 μm).
m). Further, a desired resist film 1 (for example, a film thickness of about 1 μm) is formed as a second resist thin film to obtain FIG. 1E. Since the step on the surface is reduced when the resist film 13 is etched back to obtain D, the amount of depression of the resist film 14 in the groove portion is significantly reduced (0.1 μm or less), and the film thickness depends on the groove density. Change hardly occurs (0.1 μm or less). Therefore, a very flat resist film having a uniform film thickness can be formed.
（第２実施例） 第２図は本発明の第２の実施例を説明するための工程断
面図であり、第２図Ａに示すように、基板11上全面に薄
膜としてのCVD−SiO2膜25を形成した後、以下、第２図
Ｂ〜Ｄの如く、第１の実施例と同様にして平坦で、均一
な膜厚のレジスト膜を形成できる。(Second Embodiment) FIG. 2 is a process sectional view for explaining a second embodiment of the present invention. As shown in FIG. 2A, CVD-SiO 2 as a thin film is formed on the entire surface of the substrate 11. After forming the film 25, a flat resist film having a uniform film thickness can be formed in the same manner as in the first embodiment, as shown in FIGS.
第１実施例および第２実施例において凹凸パターンを基
板11の凹凸として説明したが、この基板11の凹凸は配線
パターンや素子分離後に残る段差、その他の何の段差で
あっても良い。Although the concavo-convex pattern is described as the concavity and convexity of the substrate 11 in the first and second embodiments, the concavo-convex pattern of the substrate 11 may be a wiring pattern, a step left after element isolation, or any other step.
発明の効果 以上述べてきたように本発明の平坦もレジスト膜形成方
法によれば以下のような効果が得られる。EFFECTS OF THE INVENTION As described above, according to the method for forming a flat resist film of the present invention, the following effects can be obtained.
第１のレジスト薄膜の形成およびエッチバックによ
る除去により、凹凸段差を軽減した後に第２のレジスト
薄膜を形成するので、非常に平坦性が良く均一な膜厚の
レジスト膜形成ができる。Since the second resist thin film is formed after the unevenness is reduced by forming the first resist thin film and removing it by etching back, it is possible to form a resist film having a very good flatness and a uniform film thickness.
第２のレジスト薄膜を薄くかつ平坦・均一にできる
ので、以後の工程でのマスク露光あるいはエッチバック
による素子の平坦化が精度良く行なえる。Since the second resist thin film can be made thin and flat and uniform, the element can be accurately flattened by mask exposure or etch back in the subsequent steps.
第１図は本発明の第１実施例方法を説明するための工程
断面図、第２図は本発明の第２の実施例方法を説明する
ための工程断面図、第３図は従来の方法を説明するため
の工程断面図である。 11……基板、12……レジストパターン、 13……レジスト膜（第１のレジスト薄膜）、 14……レジスト膜（第２のレジスト薄膜）、 25……CVD−SiO2膜（薄膜）。FIG. 1 is a process sectional view for explaining a first embodiment method of the present invention, FIG. 2 is a process sectional view for explaining a second embodiment method of the present invention, and FIG. 3 is a conventional method. FIG. 6 is a process cross-sectional view for explaining FIG. 11 ...... substrate, 12 ...... resist pattern, 13 ...... resist film (first resist film), 14 ...... resist film (second resist film), 25 ...... CVD-SiO 2 film (thin film).
───────────────────────────────────────────────────── フロントページの続き (72)発明者 山本 真一 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (56)参考文献 特開 昭62−111447（ＪＰ，Ａ) 特開 昭62−45032（ＪＰ，Ａ) 特開 昭62−33445（ＪＰ，Ａ) 特開 昭62−1232（ＪＰ，Ａ) 特開 昭61−8946（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of front page (72) Shinichi Yamamoto 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) Reference JP 62-111447 (JP, A) JP 62-45032 (JP, A) JP 62-33445 (JP, A) JP 62-1232 (JP, A) JP 61-8946 (JP, A)
Claims (4)
１のレジスト薄膜を形成する工程と、前記第１のレジス
ト薄膜を所望の量、エッチバックして除去する工程と、
この第１のレジスト膜上に第２のレジスト薄膜を形成す
る工程を含み、凹凸パターン面に平坦でかつ均一な膜厚
のレジスト薄膜を形成するようにした平坦なレジスト膜
の形成方法。1. A step of forming a first resist thin film on a substrate having an uneven pattern on one main surface, and a step of etching back and removing a desired amount of the first resist thin film.
A method of forming a flat resist film, which comprises the step of forming a second resist thin film on the first resist film, so as to form a resist thin film having a flat and uniform film thickness on an uneven pattern surface.
ーンを形成した基板を使用する特許請求の範囲第１項記
載の平坦なレジスト膜の形成方法。2. The method for forming a flat resist film according to claim 1, wherein a substrate having a resist pattern formed on a desired portion of the substrate recess is used.
薄膜を２μｍ以下の膜厚とする特許請求の範囲第１項記
載の平坦なレジスト膜の形成方法。3. The method for forming a flat resist film according to claim 1, wherein the first resist thin film and the second resist thin film have a film thickness of 2 μm or less.
して使用する特許請求の範囲第１項記載の平坦なレジス
ト膜の形成方法。4. The method for forming a flat resist film according to claim 1, wherein a substrate having a thin film formed on the entire surface of the uneven portion is used as the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62232822A JPH06105675B2 (en) | 1987-09-17 | 1987-09-17 | Method of forming flat resist film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62232822A JPH06105675B2 (en) | 1987-09-17 | 1987-09-17 | Method of forming flat resist film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6474723A JPS6474723A (en) | 1989-03-20 |
| JPH06105675B2 true JPH06105675B2 (en) | 1994-12-21 |
Family
ID=16945321
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62232822A Expired - Fee Related JPH06105675B2 (en) | 1987-09-17 | 1987-09-17 | Method of forming flat resist film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06105675B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2701991B2 (en) * | 1990-12-21 | 1998-01-21 | ローム株式会社 | Wire bonder |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS618946A (en) * | 1984-06-25 | 1986-01-16 | Toshiba Corp | Manufacture of semiconductor device |
| JPS621232A (en) * | 1985-06-26 | 1987-01-07 | Matsushita Electronics Corp | Flattening method for insulating film |
| JPS62111447A (en) * | 1985-07-18 | 1987-05-22 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JPS6233445A (en) * | 1985-08-07 | 1987-02-13 | Nec Corp | Multilayer interconnection and production thereof |
| JPS6245032A (en) * | 1985-08-22 | 1987-02-27 | Nec Corp | Manufacture of semiconductor device |
-
1987
- 1987-09-17 JP JP62232822A patent/JPH06105675B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6474723A (en) | 1989-03-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |