JPH06105778B2 - Read-only semiconductor memory device and manufacturing method thereof - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a read-only semiconductor memory device capable of achieving high integration and a manufacturing method.

[Technical Background of the Invention and Problems Thereof] Generally, a read-only semiconductor memory device (hereinafter, referred to as a ROM) is called a mask program ROM because data is written using a mask during a wafer manufacturing process. There is. As a method widely adopted for writing data in this mask program ROM, a contact method,
So-called SD that writes data depending on the presence or absence of a transistor
There are three methods: a G (source, drain, gate) method and a method in which the threshold voltage of a transistor is changed according to write data.

On the other hand, NOR type ROM and NADN-based on the memory cell circuit configuration
There is also a method called NOR type ROM, and there are also methods called synchronous ROM and asynchronous ROM when the ROM is viewed from the system side. And NORA as a ROM suitable for high-speed operation
When the type ROM is low speed, NAND-NOR type ROM is often used.

Among the methods of dividing the ROM according to the above method, NOR type ROM suitable for high-speed operation has all the data writing process in addition to its circuit design, data writing ease and certainty. Since it is in the latter half, the contact method is often adopted because it is effective in terms of production.

FIG. 6 is a pattern plan view showing the configuration of a memory cell portion of a conventional ROM adopting this contact method. In the figure, a region surrounded by a broken line is one memory cell 1, and a plurality of memory cells 1 are arranged in a matrix in the horizontal and vertical directions. One memory cell 1 is composed of one MOS transistor, and this MOS transistor further includes a diffusion region 2 serving as a drain region, a diffusion region 3 serving as a common source region of a plurality of MOS transistors arranged in the horizontal direction in the drawing, and a lateral region. It is composed of a word line 4 and the like made of polycrystalline silicon which serves as a common gate electrode of a plurality of MOS transistors arranged in the direction. The drains (diffusion regions 2) of a plurality of MOS transistors arranged in the vertical direction in the figure are connected to a data line 6 made of aluminum through a contact hole 5 selectively provided according to write data. ing.

FIG. 7 is an equivalent circuit diagram of a ROM having such a pattern. Since the contact type ROM, as its name implies, writes data when forming a contact in the wafer process, the presence or absence of a contact through the contact hole 5 corresponds to the "1" level and "0" level of the data.

By the way, in a ROM having a pattern as shown in FIG.
The diffusion region 2 serving as the drain region of the memory cell MOS transistor is connected to the data line 6 through the contact hole 5. Here, this diffusion region 2 is made of silicon, while the data line 6 is made of aluminum. Silicon and aluminum have different work functions, and it is necessary to increase the area of the contact hole 5 in order to sufficiently reduce the contact resistance between materials having different work functions. Moreover, in order to prevent a short circuit with the substrate, it is necessary to secure a sufficient distance between the periphery of the contact hole and the periphery of the diffusion region. As a result, the area occupied by each drain region is increased, and the ROM with a large storage capacity is
In this case, there is a disadvantage that the chip area becomes large and the price increases.

A ROM of Japanese Patent Application No. 58-75026 is known as a ROM for eliminating such inconvenience. FIG. 8 is a plan view of the pattern, and the ROM will be described below. This ROM uses an N-channel MOS transistor as a memory cell, and the area surrounded by a broken line in FIG. 8 is one memory cell 10. A plurality of memory cells are arranged in a matrix in the horizontal and vertical directions. Similar to the case of FIG. 6, one memory cell is composed of one MOS transistor. On the P-type silicon semiconductor substrate 11, an n ⁺ type region 12 to be the drain region of each memory cell 10 is formed by a method such as diffusion. Further, in the figure, an N ⁺ type region 13 serving as a common source region for a plurality of laterally arranged methyl cells is formed on the substrate 11 in the lateral direction by a diffusion method. Further, in a plurality of memory cells arranged in the lateral direction, a word composed of the first-layer polycrystalline silicon that serves as a common gate electrode of the plurality of memory cells so as to straddle the n ⁺ type regions 12 and 13 respectively. The line 14 is extended. Further, the surface of the N ⁺ -type region 12 that serves as the drain region of each memory cell is connected to the second layer of the multi-layer via the contact hole 15 that is commonly opened for every two columns of memory cells arranged in the lateral direction. It is connected to a wiring 16 made of crystalline silicon, and an end portion of this wiring 16 is provided so as to extend onto the word line 14 which is the common gate electrode. In a plurality of memory cells arranged in the lateral direction, a contact hole 17 in which an N ⁺ type region 12 as a drain is selectively provided according to write data 17
Is connected to the data line 18 made of aluminum.

FIG. 9 shows a sectional structure of one memory cell taken along the line AA 'in the pattern plan view of FIG. 20 in the figure
Is a field oxide film for element isolation, and 21 is a word line
Reference numeral 22 is a gate oxide film provided below 14 and reference numerals 22 to 24 are oxide films. An inversion prevention layer 25 is provided on the surface of the substrate 11 below the field oxide film 20.

The ROM having such a configuration does not directly connect the data line 18 made of aluminum to the N ⁺ type region 12 which is the drain region of the memory cell transistor,
First, a wiring 16 made of a polycrystalline silicon layer is connected to the surface of the N ⁺ type region 12 through a contact hole 15, and the wiring 16 is further connected through a contact hole 17 selectively provided according to write data. It is designed to be connected to the data line 18 made of aluminum. The wiring 16 extends to above the word line 14. Here, since the N ⁺ type region 12 and the wiring 16 both use silicon as a constituent material, they have the same work function. Therefore, the contact resistance between the two can be made sufficiently low even if the contact area is small, whereby the area of the contact hole 15 on the N ⁺ type region 12 can be reduced. Furthermore, the N ⁺ type region 12 and the wiring are connected through the contact hole 15.
When connecting with 16, the field oxide film 20 side can have a self-aligned structure, and the contact hole 15 only needs to maintain an appropriate distance only on the word line 14 side. Therefore, the area of the N ⁺ type region 12 itself can be made sufficiently small and can be reduced by about 20 to 50% as compared with that of FIG. 6 in terms of memory cells.

On the other hand, when connecting the data line 18 and the wiring 16 which are respectively made of aluminum and polycrystalline silicon having different work functions, the wiring 16 is extended to above the word line 14 and its planar distance. Is made sufficiently longer than the N ⁺ type region 12, the contact hole 17 which is a contact portion between the data line 18 and the wiring 16 can have a sufficiently large area regardless of the area of the N ⁺ type region 12. As a result, the voltage and current characteristics of the MOS transistor based on the size of the contact resistance determined by the area of the contact hole are less deteriorated, and the density can be increased.

As described above, the ROM having the pattern as shown in FIG. 8 can be significantly reduced in area as compared with the ROM shown in FIG.

By the way, in order to further increase the density, the ROM in Fig. 8
If you try to make it smaller than the area of contact hole 17,
Due to the grain size relationship of the aluminum and the like, the contact resistance between the wiring 16 made of polycrystalline silicon of the second layer and the data 18 made of aluminum becomes large. In order to prevent this, it is conceivable to use a so-called barrier metal or the like between the wiring 16 and the data line. However, if such a barrier metal is used, the process must be changed significantly,
There is a drawback that the manufacturing process becomes complicated.

Further, if the density of the ROM cell shown in FIG. 8 is increased while keeping the contact size almost constant, patterning and wiring 16 for separating the wirings 16 made of polycrystalline silicon are performed. Contact hole for
The alignment margin when forming 17 becomes severe, short circuit between wirings 16 and contact hole 17 for wiring 16
Due to the dropout, the margin for manufacturing troubles such as short-circuiting of the data line 18 to be formed thereafter becomes small, and a problem such as a decrease in yield is expected.

[Object of the Invention] The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a read-only semiconductor memory device capable of realizing high integration of memory cells with a high yield and a manufacturing method thereof. Especially.

SUMMARY OF THE INVENTION In order to achieve the above object, according to the present invention, a common gate electrode is formed on one conductivity type semiconductor substrate so as to be sandwiched by insulating films and extends in a predetermined direction. A plurality of memory cell transistors formed of the other conductivity type source and drain regions formed in the semiconductor substrate, and drain regions of the plurality of memory cell transistors arranged along the extension direction of the common gate electrode. A plurality of first polycrystalline silicon layers which are formed so as to contact with the surface of the first polycrystalline silicon layer and are brought into a low resistance state by introducing impurities, and the first polycrystalline silicon layers which are arranged between the first polycrystalline silicon layers. Provided is a read-only semiconductor memory device including a plurality of second polycrystalline silicon layers formed integrally with a crystalline silicon layer and in a high resistance state without introducing impurities. It has been.

Embodiments of the Invention Embodiments of the present invention will be described below with reference to the drawings. First
1a to 1d are cross-sectional views sequentially showing manufacturing steps of the memory device according to the present invention. The storage device in this embodiment is a ROM
Therefore, the N-channel MOS transistor is used as a memory cell.

First, as shown in FIG. 1a, a P-type silicon semiconductor substrate
Selective oxidation is applied to 31 to form a field insulating film 32, and element isolation is performed. If necessary, before forming the field insulating film 32, an inversion preventing impurity is introduced into the substrate surface in this portion, and when forming the field insulating film 32, an inversion preventing layer is formed as shown by a broken line in the figure. May be. Then the substrate
A gate insulating film 33 is formed on the exposed surface of 31. After the gate insulating film 33 is formed, a first-layer polycrystalline silicon layer 34 containing phosphorus (P) is deposited on the gate insulating film 33 to a thickness of 4000 Å to 6000 Å by, for example, a CVD method (chemical vapor deposition method). Form. The first polycrystalline silicon layer 34 is initially
It may be formed in a state where impurities are not doped, and then phosphorus may be doped as an impurity.

Next, as shown in FIG. 1b, the first-layer polycrystalline silicon layer 34 is patterned by PEP (photo-etching technique) to extend the polycrystalline silicon gate electrode 35 in a predetermined direction.
To form. After that, the entire surface is oxidized by a method such as acid oxidation to form an insulating film 36 on the surface of the polycrystalline silicon layer gate electrode 35. Next, using the polycrystalline silicon gate electrode 35 and the field oxide film 32 as a mask, N-type impurities such as arsenic (As) are ion-implanted into the substrate 31, and the N-type drain region 37 and the source region 38 are self-aligned. Form. After that, an insulating film 39 having a thickness of about 3000 Å is deposited and formed on the entire surface by the CVD method by low temperature oxidation or oxidation in a high temperature oxidizing atmosphere.

Next, as shown in FIG. 1c, the insulating film 36 is formed by the PEP technique.
And 39, a contact hole 40 communicating with the surface of the drain region 37 is opened. After that, a second polycrystalline silicon layer which is not doped with impurities and has a low conductivity and a high resistance state is deposited and formed on the entire surface by the CVD method. Then, this polycrystalline silicon layer is patterned by the PEP technique so as to be extended in a direction parallel to the extension method of the polycrystalline silicon gate electrode 35, and the drain region 37
The shape is left only in the vicinity of. Next, a photoresist film (not shown) is applied and formed on the entire surface, and PEP is applied to this.
By patterning by a technique, a window (not shown) is opened at a position corresponding to a portion to be a contact pad of the second polycrystalline silicon layer. Then, using the photoresist film thus patterned as a mask, phosphorus or arsenic ions are selectively implanted into the second polycrystalline silicon layer. At this time, in the portion of the polycrystalline silicon layer that is in contact with the surface of each of the drain regions 37, a polycrystalline silicon layer 41 having a low resistance is formed by introducing impurities of phosphorus or arsenic. Then, the low-resistance polycrystalline silicon layer 41 is separated into stripes by the polycrystalline silicon layer 42 in which impurities are not introduced and which remains in the original high-resistance state.

Next, as shown in FIG. 1d, a low-temperature oxide film 43 having a thickness of about 10000Å is deposited and formed on the entire surface by a CVD method, and a contact hole 44 reaching the surface of the low-resistance polycrystalline silicon layer 41 is formed.
Are selectively opened according to write data. Next, an aluminum layer 45 is deposited and formed by, for example, a vacuum vapor deposition method, the aluminum layer 45 is further deposited and formed, and the aluminum layer 45 is subjected to a predetermined patterning by the PEP technique (see a dashed line in FIG. 1d). ). After that, a surface protection film (not shown) is formed on the entire surface to complete the memory cell portion of the ROM.

FIG. 2 shows a pattern plan view of the memory cell portion of the ROM manufactured by such a process. In FIG. 2, the polycrystalline silicon gate electrode 35 is used as a word line for a plurality of cells, and the aluminum layer 45 is used as a data line. The area surrounded by the broken line becomes one memory cell. The aluminum layer 45 serving as the data line is only the cell in which the contact hole 44 is opened, and is connected to the drain region 37 via the low resistance polycrystalline silicon layer 41.

Here, in the ROM of this embodiment, the second polycrystalline silicon layers 41 and 42 after being patterned as shown in FIG. 1b.
The difference between the two-dimensional shape and the conventional second polycrystalline silicon layer 16 shown in FIG. 9 will be described with reference to the sectional views of FIGS. 3 and 4. FIG. 3 is a cross-sectional view of a conventional one, in which each of the second-layer polycrystalline silicon layers 16 is formed into a striped pattern which is physically separated and independent. On the other hand, in the case of FIG. 4 according to the above embodiment,
The low-resistance polycrystalline silicon layer 41 to be a contact pad is not physically separated, and the original high-resistance polycrystalline silicon layer is partially reduced in resistance to electrically connect to each other. It is separated.

Therefore, when the cell is further miniaturized and the density is further increased, the resistance-changed polycrystalline silicon layer 41 is used.
On the other hand, even if a displacement occurs when the contact hole 44 is formed, the contact hole 44 only shifts onto the polycrystalline silicon layer 42 in the high resistance state.
Therefore, the contact hole does not substantially fall off, and even if the aluminum layer 45 formed thereafter contacts a part of the polycrystalline silicon layer 42 in the high resistance state through the contact hole 44, there is no inconvenience. Does not happen. Therefore, a short circuit with the polycrystalline silicon gate electrode 35 does not occur, and patterning of the second-layer polycrystalline silicon layer for each cell is not necessary. In the conventional device, the cell size is determined by the patterning for separating the second-layer polycrystalline silicon layer 16, but in the device of the above embodiment, the cell size is determined by the interval between the aluminum layers 45.
For this reason, the cell area is about 70 compared to the conventional device in FIG.
It can be reduced by about%.

As described above, the device of the above-described embodiment can prevent the yield decrease due to the contact shift, and can achieve the high density.

5a and 5b are sectional views showing steps according to another embodiment of the present invention. In the method of the above embodiment, when the second-layer polycrystalline silicon layer is separated into a high resistance portion and a low resistance portion, first, the polycrystalline silicon layer is patterned and then impurities are introduced to partially In the method of this embodiment, as shown in FIG. 5a, first, impurities are selectively introduced to reduce the resistance of the polycrystalline silicon layer 41 and the high resistance state of the polycrystalline silicon layer 41. After forming the crystalline silicon layer 42, patterning is performed as shown in FIG. 5b.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a read-only semiconductor memory device capable of realizing high integration of memory cells with a high yield and a manufacturing method thereof.

[Brief description of drawings]

FIG. 1 is a sectional view sequentially showing the manufacturing process for manufacturing a memory device according to an embodiment of the present invention, FIG. 2 is a pattern plan view of the device manufactured by the above process, and FIG. FIG. 5 is a sectional view for explaining the device of the above embodiment, FIG. 5 is a sectional view showing a manufacturing process according to another embodiment of the present invention, and FIG. 6 is a pattern plane showing a structure of a memory cell portion of a conventional ROM. FIG. 7 is an equivalent circuit diagram of the ROM of FIG. 6, FIG. 8 is a pattern plan view of a conventional ROM, and FIG. 9 is a sectional view of the ROM of FIG. 31 ... P-type silicon semiconductor substrate, 32 ... Field insulating film, 33 ... Gate insulating film, 34 ... First-layer polycrystalline silicon layer, 35 ... Polycrystalline silicon gate electrode, 36 ... Insulating film, 37 ...
Drain region, 38 ... Source region, 39 ... Insulating film, 40 ... Contact hole, 41 ... Second polycrystalline silicon layer having low resistance, 42 ... Second polycrystalline silicon layer in high resistance state, 43 … Low temperature oxide film, 44… Contact hole, 45… Aluminum layer.

Claims (2)

[Claims] 1. A common gate electrode which is formed on a semiconductor substrate of one conductivity type so as to be sandwiched by insulating films and extends in a predetermined direction, and a source of the other conductivity type formed in the semiconductor substrate. A plurality of memory cell transistors each having a drain region, and arranged along the extension direction of the common gate electrode, formed so as to contact the surface of each drain region of the plurality of memory cell transistors, and having impurities introduced therein. And a plurality of first polycrystalline silicon layers which are brought into a low resistance state and are formed between the first polycrystalline silicon layers and are integrally formed with the first polycrystalline silicon layer, and impurities are introduced. A read-only semiconductor memory device comprising: a plurality of second polycrystalline silicon layers which are not brought into a high resistance state. 2. A step of forming a common gate electrode having a three-layer structure extending in a predetermined direction so as to be sandwiched between insulating films on a conductive type semiconductor substrate, and using the common gate electrode as a mask. A step of forming a source / drain region of the other conductivity type by introducing an impurity of the other conductivity type into the semiconductor substrate, a step of depositing an insulating film on the entire surface, and a step of communicating the surface of the drain region with respect to the insulating film A step of forming holes and a step of depositing a high-resistance polycrystalline silicon layer on the entire surface and leaving the polycrystalline silicon layer only in the vicinity of the drain region in a stripe shape along the extension direction of the common gate electrode. And a part where impurities are not introduced by selectively introducing impurities into the regions of the polycrystalline silicon layer that are in contact with the surfaces of the drain regions. Is left in the high resistance state so that the polycrystalline silicon layer in the low resistance portion is separated from the polycrystalline silicon layer in the high resistance state portion. Device manufacturing method.