JPH06105835B2 - High-density mounting module manufacturing method - Google Patents
High-density mounting module manufacturing methodInfo
- Publication number
- JPH06105835B2 JPH06105835B2 JP1149971A JP14997189A JPH06105835B2 JP H06105835 B2 JPH06105835 B2 JP H06105835B2 JP 1149971 A JP1149971 A JP 1149971A JP 14997189 A JP14997189 A JP 14997189A JP H06105835 B2 JPH06105835 B2 JP H06105835B2
- Authority
- JP
- Japan
- Prior art keywords
- chip capacitor
- ceramic chip
- solder
- mounting
- fitting hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Ceramic Capacitors (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は複数枚の配線パターンとセラミックチップコン
デンサを内蔵した多層構成の高密度実装モジュールの製
造方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a high-density mounting module having a multilayer structure in which a plurality of wiring patterns and ceramic chip capacitors are incorporated.
（従来の技術とその課題） 例えば、配線パターンを有する樹脂基板を数枚積層し、
その積層基板中にセラミックチップコンデンサを内蔵
し、平面化することにより小型化を目的とした通信機器
用の高密度実装モジュールがある。(Prior art and its problems) For example, by stacking several resin substrates having a wiring pattern,
There is a high-density mounting module for communication equipment, which is intended to be miniaturized by incorporating a ceramic chip capacitor in the laminated substrate and planarizing it.
従来の、この種の装置は、セラミックチップコンデンサ
を内蔵する場合配線パターンの一部の部品取付ランドを
予じめ半田クリームなどを印刷し、セラミックチップコ
ンデンサを半田接合し、更にビアホールを有する回路基
板を、その上層部として取付け、同様の方法を繰返し乍
ら積層化を進める。上層側基板は取付けるチップコンデ
ンサの衝合部分に嵌合孔などを設け、また基板相互の回
路接合には半田バンプ法などを使用する。この取付けた
セラミックチップコンデンサの容量値の変化や耐熱衝撃
性の低下を生じる欠点があった。第４図は従来の実施例
の説明図でセラミックチップコンデンサを内蔵した積層
基板の拡大断面図である。In a conventional device of this type, when a ceramic chip capacitor is built in, a circuit board having a via hole is prepared by printing solder cream or the like in advance on a part mounting land of the wiring pattern and solder bonding. Is attached as an upper layer portion, and the lamination is advanced by repeating the same method. The upper side substrate is provided with a fitting hole or the like at the abutting portion of the chip capacitor to be attached, and the solder bump method or the like is used for circuit bonding between the substrates. There are drawbacks that the capacitance value of the attached ceramic chip capacitor changes and the thermal shock resistance decreases. FIG. 4 is an enlarged cross-sectional view of a laminated substrate incorporating a ceramic chip capacitor, which is an explanatory view of a conventional example.
第４図に示すように、その構造はセラミックチップコン
デンサ５を取付け、数枚の基板を積層化した際、その間
の熱的繰返しは数回に及びセラミックチップコンデンサ
５の取付け用外部電極７を構成している銀厚膜材料が使
用する半田材料８の錫成分との相互拡散現象を発生し、
電極の破損を生じ、セラミックチップコンデンサ５の内
部電極６の相互間が不連続となり容量値が変化する。ま
た、熱的衝撃を加えた場合セラミックチップコンデンサ
５の取付け用外部電極７が剥離を生じ易い不具合を生じ
ていた。As shown in FIG. 4, the structure is such that the ceramic chip capacitor 5 is attached, and when several substrates are laminated, thermal repetition between them is performed several times and the external electrode 7 for attaching the ceramic chip capacitor 5 is configured. The silver thick film material that is being used causes a mutual diffusion phenomenon with the tin component of the solder material 8 used,
The electrodes are damaged, the internal electrodes 6 of the ceramic chip capacitor 5 are discontinuous with each other, and the capacitance value changes. In addition, the external electrode 7 for mounting the ceramic chip capacitor 5 is liable to peel off when a thermal shock is applied.
（課題を解決するための手段） 本発明は、これらの欠点を解決するために、セラミック
チップコンデンサの取付ランドを有する基板に前記セラ
ミックチップコンデンサの嵌合のための嵌合孔を穿つ工
程と、前記取付ランド面に前記嵌合孔を覆って粘着性の
仮固定膜を張り付ける工程と、前記セラミックチップコ
ンデンサを前記嵌合孔に嵌合して前記仮固定膜に貼り付
ける工程と、前記嵌合孔にエポキシ樹脂を充填する工程
と、前記仮固定膜を除去する工程と、前記取付ランドと
前記セラミックチップコンデンサとを半田により固定す
る工程とを有することを特徴とし、その目的は取付電極
面の接合領域を内部電極から分離し、また、使用する半
田量を僅少とすることにより半田拡散に伴う電極の破損
をなくし容量値の変化のない熱的衝撃に対しても優れた
高密度実装モジュールの提供にある。(Means for Solving the Problems) In order to solve these drawbacks, the present invention comprises a step of forming a fitting hole for fitting the ceramic chip capacitor in a substrate having a mounting land for the ceramic chip capacitor, A step of sticking an adhesive temporary fixing film to the mounting land surface so as to cover the fitting hole; a step of fitting the ceramic chip capacitor in the fitting hole and pasting it to the temporary fixing film; The method is characterized by including a step of filling the interlocking hole with an epoxy resin, a step of removing the temporary fixing film, and a step of fixing the mounting land and the ceramic chip capacitor by soldering. The joint area of is separated from the internal electrodes, and the amount of solder used is minimized to prevent damage to the electrodes due to solder diffusion and to prevent thermal shock that does not change the capacitance value. Even so, it is to provide an excellent high-density mounting module.
（実施例） 第１図、第２図は本発明の実施例の工程説明図、第３図
は本発明の実施例の説明図でセラミックチップコンデン
サを内蔵した積層基板の要部拡大断面図である。図にお
いて、１は耐熱性エポキシ樹脂から成る第１層基板、２
は第２層基板、３は第１層基板の銅箔などにより構成し
た部品取付ランド、４は第２層基板を取付けた際、セラ
ミックチップコンデンサの衝合部分を基板小型化にする
ため切削加工をした嵌合孔、５は高誘電体材料からなる
セラミックチップコンデンサ、６は白金厚膜などから成
る内部電極、７は内部電極６と接する面へ銀厚膜を介
し、ニッケル層さらに半田層からなる取付用外部電極、
８は銀、錫、鉛の成分からなる接合用半田、９はセラミ
ックチップコンデンサ５を嵌合孔４中へ固定するための
充填樹脂である。嵌合孔４を有し、部品取付ランド３を
有する第１層基板１の取付面１′へ、予じめ部品の固定
化のために、例えば、シリコン樹脂系の粘着層を有する
ポリエステルフィルムなどをベースとした粘着テープの
仮固定膜10を張り付ける。その後嵌合孔４へセラミック
チップコンデンサ５を挿入し、仮固定膜10へ貼り付けて
固定しエポキシ充填樹脂９を注入し固化する。その後、
仮固定膜10を剥離することにより取付面１′は基板の部
品取付ランド３およびセラミックチップコンデンサ５の
取付用外部電極７の一面のみを表面に有する第２図の構
成を得る。斯る平面状の取付面１′へ半田接合を必要と
する部分のみへ半田クリームを印刷して昇温し、セラミ
ックチップコンデンサ５を回路パターンと半田接合をす
る。斯る構成ではセラミックチップコンデンサ５の半田
接合面は取付け電極の一面のみであり、また、誘電体の
内部電極６の端部露出面と半田接合することがない。半
田付けのための半田量は同一平面上での固定状態のため
僅少量で回路形成のための接合を得ることが出来る。こ
の結果チップコンデンサ取付電極面を構成する銀厚膜
と、半田に含まれる錫との比率を僅少値に抑えることが
出来るため昇温の際に発生する拡散に伴う取付電極の破
損を回避することが出来る。(Embodiment) FIGS. 1 and 2 are process explanatory views of an embodiment of the present invention, and FIG. 3 is an explanatory view of an embodiment of the present invention, which is an enlarged cross-sectional view of a main part of a laminated substrate containing a ceramic chip capacitor. is there. In the figure, 1 is a first-layer substrate made of heat-resistant epoxy resin, 2
Is a second layer substrate, 3 is a component mounting land made of copper foil of the first layer substrate, and 4 is a cutting process for reducing the size of the abutting portion of the ceramic chip capacitor when the second layer substrate is attached. Fitted holes 5 are ceramic chip capacitors made of a high dielectric material, 6 are internal electrodes made of platinum thick film, 7 is a silver film on the surface in contact with the internal electrodes 6, and a nickel layer and a solder layer External electrodes for mounting,
Reference numeral 8 is a solder for joining, which is composed of components of silver, tin, and lead, and 9 is a filling resin for fixing the ceramic chip capacitor 5 in the fitting hole 4. A polyester film having a silicone resin adhesive layer, for example, for fixing the preliminarily attached component to the attachment surface 1'of the first layer substrate 1 having the fitting hole 4 and having the component attachment land 3. The temporary fixing film 10 of the adhesive tape based on is attached. After that, the ceramic chip capacitor 5 is inserted into the fitting hole 4, adhered and fixed to the temporary fixing film 10, and the epoxy filling resin 9 is injected and solidified. afterwards,
By removing the temporary fixing film 10, the mounting surface 1'obtains the structure of FIG. 2 having only one surface of the mounting land 3 of the substrate and the mounting external electrode 7 of the ceramic chip capacitor 5 on the surface. The solder cream is printed only on the portion where solder bonding is required on the flat mounting surface 1'and the temperature is raised to solder-bond the ceramic chip capacitor 5 to the circuit pattern. In such a configuration, the solder joint surface of the ceramic chip capacitor 5 is only one surface of the mounting electrode, and the end portion exposed surface of the internal electrode 6 of the dielectric is not soldered. Since the amount of solder for soldering is fixed on the same plane, it is possible to obtain a small amount of joint for forming a circuit. As a result, the ratio of the thick silver film that forms the chip capacitor mounting electrode surface to the tin contained in the solder can be suppressed to a very small value, so avoiding damage to the mounting electrode due to diffusion that occurs during temperature rise. Can be done.
更につけ加えて説明すると、例えば、外形寸法が2.0mm
×1.2mmで高さが0.6mmのセラミックチップコンデンサ
を、従来の寸法で平面へ取付けた場合、底面、側面、端
面の夫々が半田との濡れフィレットを形成するため取付
電極面積当りに要求する半田量は約12mg/mm2を要する
が、本発明の予じめセラミックチップコンデンサを樹脂
中に埋め込み取付けた場合2.4mg/mm2で、ほぼ1/5の値と
なり拡散量を抑制することが出来る。更に半田印刷を施
してからチップを搭載する方法と比較して、半田溶融時
の半田ボールの発生がない。この現象は半田クリーム上
に部品が搭載されている場合、クリーム中のフラックス
成分が昇温に伴い部品下面にて突沸を生じ、この際半田
が飛散すること、またフラックス成分としてのアビエチ
ン酸などの雰囲気が不均質となり酸化物の分解機能が低
下するためと考えられる。To explain further, for example, the external dimensions are 2.0 mm.
When a ceramic chip capacitor with a size of 1.2 mm and a height of 0.6 mm is mounted on a flat surface with the conventional dimensions, the bottom surface, side surface, and end surface each form a wet fillet with solder. The amount is about 12 mg / mm 2 , but when the preliminary ceramic chip capacitor of the present invention is embedded and mounted in resin, it is 2.4 mg / mm 2 , which is almost 1/5 and the diffusion amount can be suppressed. . Further, as compared with the method of mounting the chip after solder printing, no solder balls are generated when the solder is melted. This phenomenon is because when the component is mounted on the solder cream, the flux component in the cream causes bumping on the lower surface of the component as the temperature rises, and at this time, the solder is scattered and the flux component such as abietic acid It is considered that the atmosphere becomes heterogeneous and the decomposition function of the oxide deteriorates.
（発明の効果） 以上説明したように多層配線パターンを有する基板に嵌
合孔を設け、予め仮固定膜を張り付け取付ランド面と同
一平面上にセラミックチップコンデンサを挿入し樹脂を
充填して固定してから半田クリームを印刷し、昇温を加
え半田付けするから、使用する半田量を僅少量に抑制す
ることにより、積層化のための熱履歴の繰返しを加えて
もセラミックチップコンデンサの電極の破損に伴う容量
変化のない、また熱衝撃に対しても強固な多層高密度モ
ジュールを提供出来る利点がある。(Effects of the Invention) As described above, the fitting hole is provided in the substrate having the multilayer wiring pattern, the temporary fixing film is attached in advance, the ceramic chip capacitor is inserted on the same plane as the mounting land surface, and the resin is filled and fixed. After that, solder cream is printed and soldering is performed by raising the temperature.Therefore, by suppressing the amount of solder used to a very small amount, the electrode of the ceramic chip capacitor is damaged even if repeated thermal history for lamination is applied. There is an advantage that it is possible to provide a multi-layer high-density module that does not change in capacity due to the above and is robust against thermal shock.
第１図、第２図は本発明の実施例の工程説明図、第３図
は本発明の実施例の積層基板の要部拡大断面図、第４図
は従来の実施例図で、積層基板の拡大説明図である。 １……第１層基板、２……第２層基板、３……部品取付
ランド、４……嵌合孔、５……セラミックチップコンデ
ンサ、６……内部電極、７……取付用外部電極、８……
接合用半田、９……充填樹脂層、10……仮固定膜。1 and 2 are process explanatory views of an embodiment of the present invention, FIG. 3 is an enlarged cross-sectional view of a main part of a laminated substrate of an embodiment of the present invention, and FIG. FIG. 1 ... First layer substrate, 2 ... Second layer substrate, 3 ... Component mounting land, 4 ... Fitting hole, 5 ... Ceramic chip capacitor, 6 ... Internal electrode, 7 ... Mounting external electrode , 8 ……
Bonding solder, 9 ... Filling resin layer, 10 ... Temporary fixing film.
Claims (1)
ップコンデンサを搭載して多層構成とする高密度モジュ
ールの製造方法において、前記セラミックチップコンデ
ンサの取付ランドを有する前記基板に前記セラミックチ
ップコンデンサの嵌合のための嵌合孔を穿つ工程と、前
記取付ランド面に前記嵌合孔を覆って粘着性の仮固定膜
を張り付ける工程と、前記セラミックチップコンデンサ
を前記嵌合孔に嵌合して前記仮固定膜に貼り付ける工程
と、前記嵌合孔にエポキシ樹脂を充填する工程と、前記
仮固定膜を除去する工程と、前記取付ランドと前記セラ
ミックチップコンデンサとを半田により固定する工程と
を有する高密度モジュールの製造方法。1. A method of manufacturing a high-density module in which a ceramic chip capacitor is mounted on a substrate having a wiring pattern to form a multilayer structure, wherein the ceramic chip capacitor is fitted to the substrate having mounting lands for the ceramic chip capacitor. To form a fitting hole for the mounting, a step of attaching an adhesive temporary fixing film to the mounting land surface so as to cover the fitting hole, and the ceramic chip capacitor is fitted into the fitting hole. The method includes a step of attaching to the fixing film, a step of filling the fitting hole with an epoxy resin, a step of removing the temporary fixing film, and a step of fixing the mounting land and the ceramic chip capacitor with solder. Method of manufacturing a density module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1149971A JPH06105835B2 (en) | 1989-06-13 | 1989-06-13 | High-density mounting module manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1149971A JPH06105835B2 (en) | 1989-06-13 | 1989-06-13 | High-density mounting module manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0314292A JPH0314292A (en) | 1991-01-22 |
| JPH06105835B2 true JPH06105835B2 (en) | 1994-12-21 |
Family
ID=15486628
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1149971A Expired - Fee Related JPH06105835B2 (en) | 1989-06-13 | 1989-06-13 | High-density mounting module manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06105835B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4885366B2 (en) * | 2000-01-31 | 2012-02-29 | 日本特殊陶業株式会社 | Wiring board manufacturing method |
| JP2002237683A (en) * | 2001-02-08 | 2002-08-23 | Ngk Spark Plug Co Ltd | Wiring board manufacturing method |
| JP4714510B2 (en) * | 2005-06-15 | 2011-06-29 | 日本特殊陶業株式会社 | Wiring board manufacturing method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS647696A (en) * | 1987-06-30 | 1989-01-11 | Japan Radio Co Ltd | High density package hybrid integrated circuit |
-
1989
- 1989-06-13 JP JP1149971A patent/JPH06105835B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0314292A (en) | 1991-01-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |