JPH06105870B2 - Level shift circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a level shift circuit used in an integrated circuit, and is particularly used when the power supply voltage of the output section is large.
The present invention relates to a level shift circuit using a high voltage N channel double diffused MOS transistor and a high voltage PNP transistor.

[Conventional technology]

Conventionally, this type of circuit generally has the configuration shown in FIG. That is, digital signal processing is performed by CMOS logic using a low-voltage (generally 5V) power source, and a high-voltage output section is provided with an N-channel double diffusion transistor and its complementary PNP transistor The load is connected to the collector of the PNP transistor and the other end is grounded. In this circuit, when the gate of the high voltage N-channel double diffusion transistor 8 is driven to the high voltage side level (eg 5V) of the low voltage power supply circuit by the low voltage CMOS logic of the P channel transistor 13 and the N channel transistor 14, the high voltage N channel 2 The heavy diffusion transistor 8 is turned on to drive the base of the high voltage PNP transistor 9 to a saturated state,
Raise the collector potential to the high voltage side of the high voltage power supply circuit. Also, the high-voltage N-channel double diffusion transistor 8
Turns off when the gate is driven to the ground potential, for example, OV by CMOS logic, the high-voltage PNP transistor 9 also turns off, and the collector voltage becomes OV.

In this way, the signal level of the low-voltage logic section (for example, 5V, 0
V) is level-shifted to the signal level of the voltage power supply circuit (high-side voltage 10V).

[Problems to be solved by the invention]

In the conventional level circuit described above, the P-channel transistor could not be formed to have a high breakdown voltage, so the PNP transistor
The transistor 9 must be used, and the N-channel transistor 8 must be a double diffusion transistor in order to have a high breakdown voltage. The PNP transistor 9 has a drawback that leakage current easily flows from the emitter connected to the high voltage power supply wiring to the base, and the double diffusion transistor 8 has a transistor characteristic that it is difficult to control the channel width and the channel length. There is a drawback that the amount cannot be controlled so as to reduce the amount, and as a result, the high voltage power supply line 3 passes through the emitter / base of the PNP transistor 9 and the double diffusion transistor 8 while the high voltage power supply circuit is on. There is a drawback in that the drain current becomes a leakage current and the leakage current continues to flow in the ground wiring 11, resulting in a large power consumption. In order to reduce this leakage current, it is necessary to adjust the transistor characteristics of the double diffusion transistor 8 or the gate applied voltage, but as described above, it is difficult to adjust the transistor characteristics of the double transistor. The gate applied voltage was determined by the low voltage power supply 2 and could not be adjusted. As described above, in the conventional level circuit, most of the power consumption is due to the drain current of the high-voltage N-channel double diffusion transistor. Therefore, it is necessary to control this drain current to a sufficient value by making it necessary for other circuit operations. There is.

Since this transistor has a double diffusion structure, it cannot be freely set by the ratio of the channel width and the channel length like the normal structure used in the low voltage CMOS logic part. This is because the channel length of the double diffusion transistor is the wafer. Since it is determined by the heat treatment time during the process, it is possible to arbitrarily change only the characteristics of the transistor in the level shift section without changing the characteristics of the double diffusion transistor used for other purposes simultaneously formed. It depends on what you cannot do. Therefore, it is controlled only by the gate width, but this is determined by the accuracy of the photolithography used in the wafer process, and there is a limit even when trying to make a small current, and it often flows more than necessary.

[Means for solving problems]

In the level shift circuit of the present invention, the source is connected to the high voltage side of the low voltage power supply circuit, and the gate and the drain are connected.
A low-voltage P-channel transistor operating as a load transistor, a first high-voltage N-channel double-diffused transistor whose gate and drain are also connected to the connection point of the gate and drain of this low-voltage P-channel transistor and whose source is grounded; A second high-voltage N-channel double diffusion transistor for level shifting, the gate of which is connected to the connection point of the gate and the drain of both transistors, and the source of which is grounded, and the drain of the second high-voltage N-channel double diffusion transistor. Is connected to the base and the emitter is connected to the high voltage side of the high voltage power supply circuit, and
It is characterized in that the low voltage P-channel transistor and the drain have a transfer gate connected to one end and the other end grounded.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The low-voltage P-channel transistor 6 acts as a resistance because the gate and drain are connected in common, and this resistance value can be easily changed by the ratio of the channel length and the channel width because the low-voltage P-channel transistor does not have a double diffusion structure. it can. or,
Since the gates and drains of the N-channel transistors 7 are also commonly connected, the gates of both transistors 6 and 7,
The drain-determined current flows into the drain of the N-channel transistor 7 and generates the gate voltage of the high-voltage N-channel double diffusion transistor 8. At this time, when the transfer gate composed of the P-channel transistor 4 and the N-channel transistor 5 has a gate input so that it is in an open state and voltage is applied to 1, 1 ',
When the gate of the high-voltage N-channel double diffusion transistor 8 is biased and the drain currents flowing at that time are the same in channel width of the transistors 7 and 8, both transistors 7 and 8 constitute a so-called current mirror circuit to form a low voltage P.
A drain current that is the same as the drain current controlled by adjusting the resistance value of the channel transistor 6 flows, and if different, it flows at a ratio of the channel width to drive the base of the PNP transistor 9 to saturate it, and the collector of the PNP transistor 9 To the high-voltage power supply circuit to the high-voltage side voltage level.
In this way, when the N-channel transistors 7 and 8 have the same transistor characteristics, the gate voltages are the same, and the drain currents of the two are also the same. Further, the gate voltage can be freely changed by adjusting the channel width and the channel length of the P-channel transistor 6. That is, the P-channel transistor 6
If the drain current is reduced and the gate voltages of the transistors 7 and 8 are set to be low, the drain current of the transistor 8 can be reduced and the leakage current can be reduced. When a voltage is applied to the gate inputs 1, 1'so that the transfer gate is turned on, the high voltage N-channel double diffusion transistor 8 is turned off because the gate is grounded, and the base current of the PNP transistor 9 disappears. 9 is turned off and the collector becomes the ground potential. In this way, the function of level shift is fulfilled.

〔The invention's effect〕

As described above, the present invention provides a high voltage N for level shift.
The drain current of the channel double diffusion transistor is the ratio of the channel length to the width of the low voltage P channel transistor, and the channel width of the high voltage N channel double diffusion transistor and the level shifting high voltage N channel double diffusion transistor connected to this transistor. The degree of freedom is high because it can be set by the ratio of the above, and the drain current can be much smaller than the drain current determined by the photolithography accuracy by the conventional method, and the power consumption in the level shift circuit can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a level shift circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional level shift circuit. 1,1 '... Gate input, 2 ... Low-voltage power supply wiring, 3 ... High-voltage power supply wiring, 4,13 ... P-channel transistor, 5,14
...... N-channel transistor, 6 ... Low-voltage P-channel transistor, 7,8 ... High-voltage N-channel double diffusion transistor, 9 ... High-voltage PNP transistor, 10 ... Load, 11 ... Ground wiring, 12 ... CMOS inverter input.

Claims (1)

[Claims] 1. A low-voltage P-channel transistor having a source connected to a high-voltage side of a low-voltage power supply circuit and a gate connected to a drain, and a gate and a drain connected to a connection point between the gate and the drain of the low-voltage P-channel transistor. A first high-voltage N-channel double-diffused transistor having a source installed, and a second high-voltage N-channel double-diffused transistor having a gate connected to a connection point between the gate and drain of both transistors and a source installed; The second high-voltage N-channel double diffusion transistor has a drain connected to the base and a high-voltage PNP transistor having an emitter connected to the high-voltage side of the high-voltage power supply circuit, and a connection point between the gate and the drain of the low-voltage P-channel transistor is one end. And a transfer gate connected to the other end and grounded at the other end. Level shift circuit.