JPH06105897B2 - Interference compensation circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a configuration of an interference compensation circuit that removes interference from other systems that a digital signal receives in a digital communication system.

(Conventional Circuit) A configuration example of a conventional interference compensation circuit (for example, Japanese Patent Application No. 60-2878).
81) is shown in FIG. Hereinafter, FIG. 4 will be described.
The main signal (here, a digital signal is considered) received from the main antenna 1 for receiving the main signal is subject to interference from other systems. The signal is passed through the band pass filter 2 if necessary.
After passing through, the frequency is converted to the IF band by the receiver 3. On the other hand, a signal which becomes a source of interference is received using the auxiliary antenna 4 and, if necessary, passed through a band pass filter 5 to improve the S / N thereof, and then a local oscillator 7 common to the main signal receiver is used. Then, the receiver 6 frequency-converts into the IF band. Pass the interference signal through the circuits 8 and 10 that change the phase and amplitude,
The interference component is eliminated by adding it by the adder 11 with the same amplitude and opposite phase as the interference component leaked into the main signal. In order to control the variable phase circuit 8 and the variable amplitude circuit 10, first, after addition is performed by the adder 11, the added signal is passed through the demodulator in order to detect the in-phase and quadrature components of the remaining interference component. In the demodulator, the regenerated reference carrier wave 20 is used for detection by the quadrature phase synchronous detection circuits 12 and 13 to obtain an in-phase component (13 output) and a quadrature component (12 output). These signals are passed through the harmonic elimination filters 14 and 15 and then passed through the error signal generating circuits 102 and 103 for detecting the residual interference component, thereby obtaining the in-phase and quadrature error signals. On the other hand, the interference signal is divided into two after passing through the variable phase circuit, and one of them is input to the quadrature phase detectors 22 and 23 to decompose the interference signal into the in-phase component and the quadrature component. Here, the local oscillator uses the same one as the main signal demodulator. Then, the interference signal divided into the in-phase component and the quadrature component is
After passing through 4,25, binarization is performed through the identifying circuits 27, 28 using the timing signal of the main signal demodulator. Here, the case where digital processing is performed later is shown, so this identification circuit is necessary, but when performing analog processing, this circuit is not necessary. When outputting the output of the error signal generating circuit as a digital signal, an A / D converter may be used. That is, for example, when the main signal is a 16QAM signal, the demodulated signal becomes a four-valued signal, and if sampled by an A / D converter having an output of 3 bits or more, as shown in FIG. The upper 3rd bit obtains a binary signal indicating the direction of the error. Then, the results of identification of the in-phase and quadrature component error signals and the in-phase and quadrature component interference signals are correlated.

That is, a signal obtained by taking the exclusive OR (EX-OR) 29, 30 of the in-phase components or the quadrature components is passed through the integrator 38 to be used as the control signal of the variable amplitude circuit.

In addition, a signal obtained by taking the exclusive OR (EX-OR) 31 and the exclusive inversion OR (EX-NOR) 32 of the in-phase component and the quadrature component or the quadrature component and the in-phase component is passed through the integrator 37 to change the variable phase. Used as a circuit control signal.

(Problems to be Solved by the Invention) As described above, in the conventional interference compensation circuit, a quadrature phase detector for detecting an interference signal is required as an external additional circuit, resulting in a large circuit scale. I had a problem.

An object of the present invention is to realize a simple interference compensation circuit by using a phase detector instead of a quadrature phase detector for detecting an interference signal, because the external additional circuit can be simplified.

(Means for Solving the Problems) The features of the present invention for achieving the above-mentioned object are a main antenna for receiving a main signal, an interference signal receiving means, and a phase and an amplitude of an output of the interference signal receiving means. An adjusting circuit for adjusting the relative relationship with the output of the main antenna, a combining circuit for combining the outputs of the main antenna and the interference signal receiving means adjusted by the circuit, and a reference reproduced from the output of the combining circuit and the main signal. A quadrature-phase synchronous detector that receives a carrier wave as an input and decomposes it into an in-phase component and a quadrature component, two error signal generating circuits that respectively receive the in-phase component and the quadrature component, and a signal from the circuit that is coupled to the adjusting circuit. On the other hand, a phase detector that performs phase detection using the same reference carrier as that of the quadrature-phase synchronous detector, the output of the phase detector, and the correlation of the outputs of the two error signal generation circuits are provided independently of each other. Controlling the amplitude adjustment of the adjusting circuit by the output of one of the integrators, which is associated with the in-phase component, having two multipliers and two integrators each connected to the output of the multiplier, An interference compensating circuit that controls the phase adjustment of the adjusting circuit by the output of the other integrator, which is associated with the quadrature component.

(Example) An example of the present invention is shown in FIG. Hereinafter, FIG. 1 will be described in detail. The main signal received from the main antenna 1 is S /
In order to improve N, if necessary, after passing through the band pass filter 2, it is converted into an IF band by the frequency converter 3. On the other hand, the interference signal received from the auxiliary antenna 4 for receiving the source signal of the interference component included in the main signal improves the S / N,
After passing through the band pass filter 5 if necessary, the local oscillator 7 common to the main signal side is used, and the IF
Converted to obi. The interference component in the main signal can be eliminated by adjusting the phase and amplitude of the IF signal and adding 11 with the same amplitude and opposite phase as the interference component in the main signal.

Hereinafter, it will be described quantitatively. It is assumed that the main signal is a 16QAM signal and the interference signal is an amplitude-modulated wave. The main signal converted to the IF band can be expressed by the following equation.

Here, ak, hk = {± 1, ± 3}, γ (t) is the impulse response of the entire system, T is the clock period, and ω ₁ is the carrier angular frequency of the main signal. f (t) is the amplitude component of the interference component,
Since polar coordinates are displayed, f (t)> 0. ω ₂ represents the angular frequency of the interference component, and θ represents the phase. On the other hand, when the other input signal of the adder 11 is normally controlled, it is expressed by the following equation.

However, Δγ and Δθ may be considered to be sufficiently small values. The result of adding equations (1) and (2) is the main signal demodulator 10
Quadrature phase synchronous detection (12,13) at 0 and harmonic elimination filter
After passing through 14 and 15, the in-phase and quadrature components are expressed by the following equation.

Here, Δω represents the difference between ω ₁ and ω ₂ .

These four-valued demodulated signals are input to error signal generation circuits 102 and 103 that detect residual interference components. An A / D converter having an output of 3 bits or more is usually used as the error signal generating circuit. As shown in FIG. 5, when a 4-level signal is input, the upper 2 bits of the output indicate the identification result. The upper 3rd bit represents the deviation direction of the signal point, that is, the error direction. Therefore, the upper 3rd bit or the error signal can be taken out. In-phase and quadrature component error signals are expressed by the following equations.

Ei (t) = − Δγ · cos (Δωt + θ) + f (t) · Δ
θ · sin (Δωt + θ) (5) Eq (t) = − Δγ · sin (Δωt + θ) −f (t) · Δ
θ · cos (Δωt + θ) (6) Further, the interference signal is branched by 8, the phase is detected by the reference carrier wave 20 regenerated by the main signal demodulator by 23, and the detector output after passing through the harmonic elimination filter 25 Is given by

Here, K represents the gain of the variable amplitude circuit, and θ ′ represents the phase.

In order to detect the correlation between the error signal represented by the equations (5) and (6) and the interference signal represented by the equation (7),
i ₂ (t) × Ei (t) and 31 yields i ₂ (t) × Eq (t)
The following equation is obtained by performing the calculation of and passing through the integrating circuits 32 and 33.

i ₂ (t) × Ei (t) → f (t) · Δγ · cos (θ−
θ ′) (8) i ₂ (t) × Eq (t) → f ² (t) · Δθ · cos (θ−
θ ′) (9) Here, θ and θ ′ are initial phases, and the amount of fluctuation thereof need not be considered at all. Therefore, if the initial adjustment is made so that θ = θ ′, the variable amplitude circuit 10 can be calculated from equation (8). Δγ of the variable phase circuit can be controlled by the equation (9).

Next, another embodiment of the present invention is shown in FIG. The difference from FIG. 1 is that the output of the error signal generating circuit and the phase-detected interference signal are binarized and the correlation is detected digitally. For the detection output expressed by the equations (3) and (4),
As a result of identification using the timing signal 22 reproduced by the demodulator, the error signal is expressed by the following equation.

sgn (Ei (mT)) = sgn {-Δγ ・ cos (Δω ・ mT + θ) + f (t) ・ Δθ ・ sin (Δω ・ mT + θ)} (10) sgn (Eq (mT)) = sgn {-Δγ ・ sin (Δω · mT + θ) −f (t) · Δθ · cos (Δω · mT + θ)} (11) On the other hand, when the interference signal represented by the equation (7) is identified using the timing signal 22 reproduced by the main signal demodulator, It is expressed by the following equation.

sgn (i ₂ (mT)) = − sgn {cos (Δωt · θ ′)} (1
2) In order to correlate equations (10) and (11) with equation (12), digital multiplication, that is, exclusive OR 30 and 31,
The following equation is obtained by passing through the integrators 32 and 33.

sgn (i ₂ (mT)) × sgn (Ei (mT)) → −sgn {−Δγ · cos (θ−θ ′) + f (t) · Δθ ·
sin (θ−θ ′)} (13) sgn (i ₂ (mT)) × sgn (Eq (mT)) → sgn {Δγ ・ sin (θ−θ ′) + f (t) ・ Δθ ・ cos
(Θ−θ ′)} (14) Here, if θθ ′ is set as in the previous case, equations (13) and (14)
Is given by

sgn (i ₂ (mT)) × sgn (Ei (mT)) → sgn (Δγ) (1
3) ′ sgn (i ₂ (mT)) × sgn (Eq (mT)) → sgn (Δθ) (1
4) ′ Therefore, the amplitude of the variable amplitude circuit 10 can be controlled by the equation (13) ′, and the phase of the variable phase circuit 8 can be controlled by the equation (14) ′.

In order to apply the equations (8), (9) and (13) ', (14)', both the interference component leaked into the main signal and the interference signal received from the auxiliary antenna are Immediately before the combiner 11 in FIG. 1 or FIG. 2, it is necessary to match the absolute delay times. For that purpose, τ _{1 in} FIGS.
A delay circuit is required.

Further, the correlation circuits 30 and 31 of FIG. 1 or the correlation circuit 3 of FIG.
At the 4,35 input points, it is necessary to match the absolute delay times of the error signal and the interference signal. Therefore, τ ₂ and τ
₃ delay circuits are required.

Up to this point, the 16QAM signal has been described as an example of the main signal.
For PSK, 64QAM, etc.
Others are exactly the same except that the number of output bits of the / D converter is different. Further, although the amplitude modulation circuit has been described as an example of the interference signal, in the case of the frequency modulation signal, the following equation (1) or equation (2) is used. Instead of Or in the case of a phase modulated signal, In the case of CW wave, It can be processed in exactly the same way.

As a modified example of the present invention, the distributor 9 shown in FIG. 1 or FIG.
Can be provided in the subsequent stage of the variable amplitude circuit 10 and the distributor 9 can be provided in the previous stage of the variable phase circuit 8. Even in such a case, the interference compensating circuit can be realized with the same circuit configuration otherwise. Although FIG. 1 or 2 shows a configuration example using a variable amplitude circuit and a variable phase circuit in the IF band, the same applies to the RF band.

In the embodiment of the present invention shown in FIG. 1 or 2, the amplitude and phase of the interference signal received from the auxiliary antenna are adjusted to cancel the interference wave, but the amplitude and phase of the main signal received from the main antenna are adjusted. Needless to say, the interference wave can be canceled in the same manner.

Further, when adjusting the phase, the same effect can be obtained by adjusting the phase of the local oscillator used for the frequency converter instead of directly changing the phase of the signal.

Further, in the embodiment of the present invention, an example in which an auxiliary antenna different from the main antenna is used for reception in order to obtain an interference signal has been shown, but an auxiliary antenna is not always required as long as an interference signal can be obtained.

(Effects of the Invention) An interference compensation circuit based on the principle of the present invention was prototyped and its compensation characteristics were measured. The results are shown in FIG. Here, the main signal is a 16QAM signal, and the interference signal is a Kafuber signal.
The modulated signal was used. The vertical axis of FIG. 3 represents the signal-to-noise power ratio (C / N), and the horizontal axis represents the signal-to-interference power ratio (D / U). The code error rate of the 16QAM signal with or without the compensator = The relationship between C / N and D / U at 10 ^-4 is shown. From FIG. 3, an improvement effect of D / U of about 20 dB is shown, which confirms the effectiveness of the present invention.

As described above, in the interference compensation circuit, only one phase detector is required to detect the interference signal. Therefore, the external circuit can be simplified, which is advantageous for downsizing the interference compensation circuit.

[Brief description of drawings]

1 and 2 are block diagrams showing an embodiment of the present invention, FIG. 3 is a diagram showing the effect of the present invention, FIG. 4 is a block diagram of a conventional interference compensation circuit, and FIG. 5 is a quaternary signal. FIG. 3 is an explanatory diagram of an error signal generation circuit for FIG. 1 ... Main antenna, 2,5 ... Band pass filter, 3,6 ...
Frequency converter, 4 ... Auxiliary antenna, 7 ... Local oscillator, 8 ... Variable phase circuit, 9 ... Distributor, 10 ... Variable amplitude circuit, 11 ... Combiner, 12, 13 ... Phase detector , 14,15 ...
… Low-pass filter, 16,17 …… Identification circuit, 18,19 …… Subtractor, 20 …… Reproduced carrier, 21 …… 90 ° phase shifter, 22 …… Timing signal generation circuit, 23 …… Phase detection Unit, 25 ... Low-pass filter, 26 ... Identification circuit, 30,31 ... Multiplier, 32,
33 …… Integrator, 34,35 …… EX-QR circuit, 100 …… Demodulator, 1
01: control circuit, 102, 103: error signal generation circuit.

Claims (7)

[Claims] 1. A main antenna for receiving a main signal, an interference signal receiving means, an adjusting circuit for adjusting a relative relationship between a phase and an amplitude of an output of the interference signal receiving means and an output of the main antenna, and the circuit. A synthesizing circuit for synthesizing the output of the main antenna and the interference signal receiving means adjusted by the above, and a quadrature phase synchronous detector for decomposing into an in-phase component and a quadrature component with the output of the synthesizing circuit and the reference carrier reproduced from the main signal , Two error signal generating circuits each having the in-phase component and the quadrature component as inputs, and a phase that is coupled to the adjusting circuit and phase-detects a signal from the circuit with the same reference carrier as the quadrature-phase synchronous detector. A detector, two multipliers that independently provide the correlation between the output of the phase detector and the outputs of the two error signal generating circuits, and two multipliers that are respectively connected to the outputs of the multipliers. A divider, which controls the amplitude adjustment of the adjusting circuit by the output of one of the integrators associated with the in-phase component and the phase of the adjusting circuit by the output of the other integrator associated with the quadrature component. An interference compensation circuit, characterized by controlling regulation. 2. The interference compensating circuit according to claim 1, wherein the adjusting circuit comprises a cascade connection of a variable phase circuit and a variable amplitude circuit. 3. The interference compensation circuit according to claim 1, wherein the adjustment circuit is realized by adjusting the output of a local oscillator. 4. The interference compensating circuit according to claim 1, wherein the interference signal receiving means includes an auxiliary antenna for receiving the interference signal. 5. An input according to claim 5, wherein an input of the phase detector is provided from an output of the cascade circuit.
The interference compensation circuit according to the item. 6. The second aspect of the present invention, wherein the input of the phase detector is provided from the input of the cascade circuit.
The interference compensation circuit according to the item. 7. The interference compensation circuit according to claim 2, wherein an input of the phase detector is provided from an output of the variable phase circuit.