JPH06105982B2 - Color signal processor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color signal processing device for a video tape recorder, and more particularly to a color signal processing device for frequency converting a color signal reproduced from a magnetic tape.

[Conventional technology]

Conventionally, in a video tape recorder (hereinafter referred to as VTR) that records and reproduces a color video signal, the color video signal is composed of a frequency-modulated luminance signal and a low-frequency converted color signal, that is, a low-frequency conversion color signal. It is converted into a mixed signal and recorded. Therefore, during reproduction, the low-frequency conversion color signal is frequency-converted into the color signal of the original frequency. In this case, the low-frequency conversion color signal includes the time-axis fluctuation caused by the head / tape system. From that,
PLL for color signal processing device that frequency-converts low-frequency converted color signals
(Phase Locked Loop) is formed, and the above-mentioned time base fluctuation is removed at the same time when the low frequency conversion color signal is frequency-converted into the color signal of the original frequency.

By the way, in this PLL, a burst signal of a frequency-converted color signal is used. Therefore, the PLL operates only during the burst signal period and operates intermittently. Therefore, the PLL is controlled at a frequency other than the originally intended frequency, and a phenomenon called so-called false lock may occur.

In order to prevent this, for example, see "Home VTR Primer" edited by the Television Society, published by Corona Publishing Co., Ltd. P.170, Figure 14.34 (a).
As explained in, the frequency discriminator is provided, and the frequency of the reference signal such as the horizontal synchronizing signal reproduced from the magnetic tape and the output signal of the voltage-controlled oscillator (hereinafter referred to as VCO) in the PLL. And the VCO is controlled by the error signal, so that the PLL is controlled at the target frequency.

The color signal processing device will be described below with reference to FIG. In the figure, 1 is a frequency converter and 2 is a BPF.
(Band pass filter), 3 for VCO, 4 for phase comparator,
5 is a frequency discriminator, 6 is a reference oscillator, 7 is an adder, 8 and 9
Is an input terminal and 10 is an output terminal.

Frequency converter 1, BPF2, phase comparator 4, reference oscillator 6, VCO3
The LL is configured, and the low frequency conversion color signal reproduced from the magnetic tape is input to the input terminal 8 and the horizontal synchronizing signal reproduced from the magnetic tape is input to the input terminal 9.

The low-frequency conversion color signal C _L input to the input terminal 8 is frequency-converted by the frequency converter 1 by the output signal F _V of VCO3,
Unnecessary components are removed by BPF2 to obtain a color signal C in the specified band whose color subcarrier frequency is f _SC . This color signal C is supplied to the phase comparator 4 together with the output signal F _S of the reference oscillator 6 that oscillates at the color subcarrier frequency f _SC , and the phase detection is performed only during the burst signal period of the color signal C and the phase error signal E between them is detected. _P is output. On the other hand, VCO3 converts the signal F _V into the low-frequency conversion color signal C _L
Of which occurred as a carrier for the frequency conversion, the frequency discriminator 5, to the carrier F _V and compares the frequency of the horizontal synchronizing signal HS from input terminal 9, a constant frequency with these two signal relationships If not, the frequency error signal F _f between them is output. The phase error signal E _P and the frequency error signal E _f are added by the adder 7 to become the VCO control signal E. The VCO 3 is controlled by the VCO control signal E, whereby the time base fluctuation is removed when the low-pass conversion color signal C _L is frequency-converted, and the color subcarrier frequency is accurately set to f _SC from BPF 2. A smoothed color signal C is obtained.

[Problems to be solved by the invention]

By the way, in the VTR, a plurality of video heads are used, and these are switched in order to reproduce and scan the magnetic tape. When the video heads are sequentially switched in this manner, the reproduction signal becomes discontinuous at the time of switching the heads. For this, the horizontal synchronizing signal becomes discontinuous included in the reproduced signal, a frequency discriminator 5 is by connexion malfunction this discontinuity of the horizontal synchronizing signal, greatly disturbed the frequency of carrier F _V output from the VCO 3, which is It will last for a period of time.
As a result, the color subcarrier frequency of the color signal C output from the BPF2 also largely deviates from f _SC for a certain period from the head switching time, and a color flickering appears at the upper part of the reproduction screen and the color reproducibility becomes unstable. Become.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a color signal processing device which solves such a problem and can prevent color disorder on a reproduction screen due to head switching.

[Means for solving problems]

In order to achieve the above object, the present invention is provided with means for detecting a head switch time point, and prohibits the output of the frequency error signal from the frequency discriminator for a predetermined period from the head switch time point.

[Work]

The above means outputs a stop signal of a predetermined time width from the head switching time point, whereby the frequency discriminator stops outputting the frequency error signal. The frequency of the input signal of the frequency discriminator (reproduction horizontal synchronizing signal, etc.) is disturbed by head switching, but the time width of the stop signal is set to be longer than the period length in which the frequency of the input signal is disturbed. Therefore, the frequency error signal is not affected by head switching, and a color signal with a stable color subcarrier frequency can be obtained.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a color signal processing apparatus according to the present invention, in which 11 is a rotary cylinder, 12 and 13 are video heads, 14 is an LPF (low pass filter), 15 is a comb filter and 16 is a Reproduction amplifier, 17 is a frequency divider, 18 is a frequency converter, 19 is a head switching detector, 20 is an input terminal,
The same reference numerals are attached to the portions corresponding to FIG.

In the figure, a magnetic tape (not shown) is a rotating cylinder 11
The video heads 12 and 13 mounted on the head are alternately reproduced and scanned. The signal reproduced by this is mainly
It is composed of an FM-modulated luminance signal and a low-frequency conversion color signal, and this low-frequency conversion color signal is separated by the LPF 14. Since the processing of the luminance signal is not relevant here, the description thereof will be omitted below.

The low-frequency conversion color signal C _L separated by the LPF 14 is also frequency-converted by the carrier F _C output from the frequency converter 18 in the frequency converter 1, and unnecessary components are removed by the BPF 2 to eliminate the color subcarrier frequency f _SC . The color signal C is obtained. The color signal C is supplied to the comb filter 15 to remove the crosstalk component from the adjacent track on the magnetic tape, amplified by the reproducing amplifier 16 and output from the output terminal 10.

The chrominance signal C output from the comb filter 15 is also supplied to the phase comparator 4 and phased only during the burst signal period of the output signal F _S of the reference oscillator 6 oscillating at the color subcarrier frequency f _SC and the chrominance signal C. The phase error signal E corresponding to the phase difference between the burst signal and the output signal F _S of the reference oscillator 6 is compared.
_P is formed. On the other hand, the horizontal synchronizing signal HS input to the input terminal 9 is supplied to the frequency discriminator 5 and the frequency 160 f
VCO3 that oscillates at _H (however, f _H is the horizontal sync signal frequency)
And the frequency is compared, and when the frequency relationship between the two is deviated from a predetermined relationship, a frequency error signal E _f corresponding to the deviation amount is formed. The frequency error signal E _f and the phase error signal E _P from the phase comparator 4 are added by the adder 7 to generate the VCO control signal E, which controls VCO3.

As described above, since the VCO3 is controlled by the phase error signal E _P , the output signal of the VCO3 includes the same time axis fluctuation as the low frequency conversion color signal from the LPF14, and the VCO3 has the frequency error signal E _P. By being controlled by _f , the output signal of VCO3 is prevented from being largely deviated from the frequency of 160f _H and stabilized, that is, erroneous locking is prevented.

The output signal of VCO3 is also divided by 4 by the 4 divider 17.
Therefore, the frequency of the output signal of the divide-by-four frequency divider 17 is 40 f _H , which is the low-frequency conversion color signal C output from the LPF 14.
Equal to the _L color subcarrier frequency. The output signal of the divide-by-four frequency divider 17 is supplied to the frequency converter 18 and is frequency-converted by the output signal F _S of the reference oscillator 6 to form a carrier F _C of the sum or difference frequency of both signals. This carrier F _C is supplied to the frequency converter 1 and the low frequency conversion color signal C is supplied.
_The frequency conversion of _L is performed, whereby the color signal C having the color subcarrier frequency f _SC and the time base fluctuation removed is obtained from the BPF 2.

On the other hand, the input terminal 20 receives a head switching signal SW for switching the video heads 12 and 13 alternately. This head switching signal SW is a signal that inverts the level from the high level to the low level and from the low level to the high level at each switching time point of the video heads 12 and 13, and the head switching detection circuit 19 inverts the level of the head switching signal SW. Is detected and a pulse P representing the head switching time is output. When this pulse P is supplied, the frequency discriminator 5 stops the output of the frequency error signal E _f from this pulse P for a predetermined period. Although the VCO3 is controlled only by the phase error signal E _P from the phase comparator 4 during this period, the oscillation frequency of the VCO3 does not change rapidly even if the control by the frequency error signal E _f is stopped, and the frequency error signal E _P does not change. E
_{When the} control by _f is restarted, it is not in the lock state.

Therefore, the color signal C output from the BPF2 is not affected by the discontinuity of the horizontal synchronizing signal HS that accompanies head switching, and the color subcarrier frequency is stable at f _SC. Color is stable and color reproducibility is improved throughout.

FIG. 2 is a block diagram showing a specific example of the frequency discriminator 5 and the head switching detection circuit 19 in FIG. 1, in which 21 is a detection unit, 22 is a switch, and 23 is an SR type flip-flop circuit (hereinafter referred to as FF). ), 24-29 are inverters, 30, 31 are AND gates, 32 is an OR circuit, and the same reference numerals are given to the parts corresponding to FIG.

The operation of this specific example will be described below with reference to FIG.

In FIG. 2, the frequency discriminator 5 includes a detector 21, a switch 2
2, consists of FF23 Prefecture, and a horizontal synchronizing signal HS supplied from the output signal F _V and the input terminal 9 of the VCO 3. The detection unit 21 has a seventh
As shown in the figure, the frequency divider 21a that divides the horizontal synchronization signal HS
And a counter 21b for counting the output signal F _{V of} VCO3
And a comparator 21c that compares the count value N _{C of the} counter 21b with the reference value N _S , a decoder 21d, a read pulse generation circuit 21e, and the like. The counter 21b outputs the output pulse of the frequency divider 21a (third The output signal F _{V of} VCO3 is reset by resetting according to FIG. The output pulse A of the frequency divider 21a is generated every one to several pulses of the horizontal synchronizing signal HS.
The counter 21b sets one cycle of the output pulse A of the frequency divider 21a as one cycle, and outputs the output signal F _{V of} VCO3 for each cycle.
Immediately before being reset by the output pulse A, the count value of one cycle is output by the read pulse generated by the read pulse generation circuit 21e. This count value is compared with the reference value N _S by the comparator 21c to form data ΔN corresponding to the difference. This data ΔN is output from the detector 21.

The output pulse A of the frequency divider 21a in the detector 21 is also supplied to the FF 23 as a set pulse. The output pulse P of the head switch detection circuit 19 is used as the reset pulse of FF23. Therefore, FF23 is a head switching detection circuit 19
Output pulse P resets its Q output to a low level, and is reset by the first reset pulse A after this output pulse P to set its Q output to a high level. The switch 22 is controlled by this Q output, and is closed when the Q output is high level and is opened when the Q output is low level. Here, the output time of the data .DELTA.N of the detector 21 is slightly ahead of the output time of the set pulse A, and therefore, from the time of the output pulse P of the head switch detection circuit 19 (that is, the head switch time) to the next. The data .DELTA.N output from the detection unit 21 is removed by the switch 22 during the period up to the time of the set pulse A. The data ΔN to be removed Te This switch 22 Niyotsu are those based on the count value N _C of the counter 21b in the cycle including head switching time, the count value N _C is by the discontinuous horizontal synchronizing signal connexion It is significantly different from the count values of other cycles.

The reference value N _S set by the detector 21 is the output signal F _{V of} VCO3.
1 of the counter 21b when the frequency of is exactly 160f _H
Equal to the cycle count value. Therefore, the data Δ
N has a value corresponding to the amount of deviation of the frequency of this output signal F _V from 160 f _H. In this case, the data ΔN may be digital data, or may be a pulse whose amplitude changes by being decoded by the decoder 21d as shown in FIG. In any case, the data ΔN passed through the switch 22 forms the frequency error signal E _f by a well-known means, which is omitted in FIG.

On the other hand, the head switch detection circuit 19 is composed of inverters 24 to 29, AND gates 30 and 31, and an OR circuit 32. Here, the inverters 24 to 29 level-invert the input signal and also have a delay function.

Head switch signal SW from input terminal 20 is AND gate 30
Is supplied to the AND gate 31 after being level-inverted by the inverter 24. Further, the output signal ▲ ′ of the inverter 24 is supplied to the AND gate 30 via the inverters 25 to 28. Output signal of this inverter 28 ▲
▼ ″ is delayed by the total delay amount of the inverters 24 to 28 with respect to the head switching signal SW by the five (odd) inverters 24 to 28, and the level is inverted. A pulse P ₁ having a time width equal to the total delay amount of the inverters 24 to 28 is obtained from the rising edge of the head switching signal SW from 30. Further, the output signal ▲ ▼ ″ of the inverter 28 is further output by the inverter 29. The level is inverted and supplied to the AND gate 31. Here, the output signal SW of the inverter 29 is delayed with respect to the output signal {circle around (1)} of the inverter 24 by the total delay amount of the inverters 25 to 29, and the level is inverted. Therefore,
From the AND gate 31, a pulse P _{2 on the} time axis which rises at the falling edge of the head switching signal SW and is equal to the total delay amount of the inverters 25 to 29 is obtained. These pulses P ₁ and P ₂ are supplied to the OR circuit 32 to form the pulse P.

FIG. 4 is a block diagram showing another specific example of the frequency discriminator 5 in FIG. 1, in which 33 is a frequency divider, and parts corresponding to those in FIG. Is omitted.

In the specific example described with reference to FIG. 2, as is apparent from FIG. 3, only the data .DELTA.N of the cycle including the head switch point is excluded. This is because the output times of the data ΔN and the set pulse A are restricted only by the horizontal cycle signal HS, and when the data ΔN is output, the set pulse A is always output immediately after that. However, if there is a head switch, then the frequency of the horizontal sync signal HS may become unstable over a long period of time, that is, over one cycle that is one to several times the cycle of the horizontal sync signal HS. In such a case, the concrete example shown in FIG.
It is not possible to remove the effect of the unstable frequency of the horizontal synchronizing signal HS. The concrete example shown in FIG. 4 is also designed to solve this problem.

In the figure, the preceding pulse A output from the detector 21 is divided by a frequency divider 33, and its output pulse A'is supplied to the FF 23 as a set pulse. The output pulse P of the head switch detection circuit 19 becomes a reset pulse of the FF 23 in the frequency discriminator 5 and is also used as a clear pulse of the frequency divider 33. As a result, the frequency divider 33 is cleared every time the head is switched, and the frequency division operation is newly started from there.

The detection unit 21 outputs the data ΔN and the pulse A at the same timing as the detection unit 21 shown in FIG. Now, assuming that the frequency division ratio of the frequency divider 33 is 3, as shown in FIG. 5, the frequency divider 33 extracts the pulse A every third pulse from the third pulse after the head switching time. It becomes the set pulse A '. Therefore, when the FF23 is reset by the pulse P, it is set by the first pulse of the set pulse A ', so that the data .DELTA.N is set to 3 after the head switching by the switch 22.
Cycles are removed. If the horizontal synchronizing signal HS is stable within these cycle periods, the color signal C will not become unstable due to head switching.

According to this specific example, the data ΔN does not have to be a pulse, but may be a continuous analog signal.

Although one embodiment of the present invention has been described above, the present invention is not limited to this embodiment. For example,
The PLL may have a configuration other than that shown in FIG. V
The output frequency of CO3 is the color signal C whose color subcarrier frequency is f _SC.
The configuration shown in FIG. 6 may be used if the above is set. Further, in FIG. 1, the input signal of the frequency discriminator 5 is a horizontal synchronizing signal, but it may be another reference signal recorded / reproduced in a video head such as a pilot signal used for a tracking servo. . Further, the head switching detection circuit 19 may have another circuit configuration such as a differentiating circuit as long as the head switching time point can be detected.

〔The invention's effect〕

As described above, according to the present invention, it is possible to prevent the frequency discriminator from malfunctioning due to head switching.
The VCO can be stabilized and the color on the playback screen is stable and the color reproducibility is greatly improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a color signal processing apparatus according to the present invention, FIG. 2 is a block diagram showing a concrete example of a frequency discriminator and a head switching detection circuit in FIG. 1, and FIG. FIG. 4 is a block diagram showing another specific example of the frequency discriminator in FIG. 1, FIG. 5 is an operation explanatory diagram thereof, and FIG. 6 is a block diagram showing an example of a conventional color signal processing device. FIG. 7 is a block diagram showing a specific example of the detection section in FIGS. 2 and 4. 1 ... Frequency converter, 3 ... Voltage-controlled oscillator, 4 ...
Phase comparator, 5 ... Frequency discriminator, 6 ... Reference oscillator,
7 ... Adder, 19 ... Head switching detection circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-58-92189 (JP, A) JP-A-63-56083 (JP, A) JP-A-59-219089 (JP, A)

Claims (1)

[Claims] 1. A low frequency conversion color signal reproduced from a magnetic tape by a plurality of rotary video heads as an input signal, and at least a frequency converter for frequency converting the low frequency conversion color signal, a voltage controlled oscillator and a burst signal. A phase locked loop is formed with a phase comparator that detects a phase fluctuation, and a frequency discriminator detects a frequency fluctuation of the output signal of the voltage controlled oscillator and controls the voltage controlled oscillator by the detected signal. In the color signal processing device adapted to convert the low-pass conversion color signal into a color signal in a prescribed band, a head switching detection for detecting rising and falling edges of a head switching signal for sequentially switching the rotary video heads. A circuit is provided, wherein the frequency discriminator is a horizontal equalizer separated from a luminance signal reproduced from the magnetic tape by the rotary video head. A frequency divider that divides the signal by N (where N> 1), and is reset by the output signal of the frequency divider, counts the output signal of the voltage-controlled oscillator, and counts the timing immediately before the reset timing. A counter that outputs a count value, a comparator that compares the output count value of the counter with a reference value, and outputs the difference data between these counters, and a reset by the output signal of the head switching detection circuit. A flip-flop circuit that is set by a signal that is M times as long as the output signal (where M is an integer of 1 or more) and that is phase-synchronized with the output signal of the frequency divider; and controlled by the output signal of the flip-flop circuit. And a switch that shuts off the output signal of the comparator when the flip-flop circuit is in the reset state. Is used as the detection signal of the frequency discriminator.