JPH0611044B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0611044B2 JPH0611044B2 JP62111821A JP11182187A JPH0611044B2 JP H0611044 B2 JPH0611044 B2 JP H0611044B2 JP 62111821 A JP62111821 A JP 62111821A JP 11182187 A JP11182187 A JP 11182187A JP H0611044 B2 JPH0611044 B2 JP H0611044B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- insulating film
- aluminum
- window
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 30
- 238000004519 manufacturing process Methods 0.000 title description 4
- 238000000034 method Methods 0.000 title description 4
- 239000000758 substrate Substances 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 238000004544 sputter deposition Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 description 30
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 30
- 229910052581 Si3N4 Inorganic materials 0.000 description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 12
- 238000009792 diffusion process Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000009413 insulation Methods 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- -1 argon ions Chemical class 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device.
半導体装置の高集積下の一つとして多層配線技術は欠か
せないものとなっている。The multi-layer wiring technology is indispensable as one of the highly integrated semiconductor devices.
第３図は従来の半導体装置の第１の例を説明するための
半導体チップの断面図である。FIG. 3 is a sectional view of a semiconductor chip for explaining the first example of the conventional semiconductor device.
第３図に示すように、一導電型の半導体基板１の上に逆
導電型の拡散領域２を設ける。次に、全面にシリコン酸
化膜３を形成して選択的にエッチングし、拡散領域２の
上に配線接続用窓を設ける。次に、前記窓を含む全面に
アルミニウム膜を堆積して選択的にエッチングし、前記
窓の拡散領域２と接続するアルミニウム配線６を形成す
る。次に、全面にシリコン酸化膜４を形成する。As shown in FIG. 3, a diffusion region 2 of opposite conductivity type is provided on a semiconductor substrate 1 of one conductivity type. Next, a silicon oxide film 3 is formed on the entire surface and selectively etched to form a wiring connection window on the diffusion region 2. Next, an aluminum film is deposited on the entire surface including the window and selectively etched to form an aluminum wiring 6 connected to the diffusion region 2 of the window. Next, the silicon oxide film 4 is formed on the entire surface.
アルミニウム配線６はその後の熱処理等でシリコン窒化
膜４の応力を受けてアルミニウム配線６に亀裂９を生ず
ることがある。The aluminum wiring 6 may receive a stress of the silicon nitride film 4 due to subsequent heat treatment or the like, and a crack 9 may be generated in the aluminum wiring 6.
第４図は従来の半導体装置の第２の例を説明するための
半導体チップの断面図である。FIG. 4 is a sectional view of a semiconductor chip for explaining a second example of the conventional semiconductor device.
第４図に示すように、第１の例と同様にして設けた配線
接続用窓を有するシリコン酸化膜３を含んで全面にアル
ミニウム膜を堆積して選択的にエッチングし、前記窓の
拡散領域２と接続するアルミニウム配線６およびアルミ
ニウム配線６と近接したアルミニウム配線１０が設けら
れ、アルミニウム配線６，１０を含んで全面にシリコン
窒化膜４が設けられる。次に、アルミニウム配線６の上
のシリコン窒化膜４に開口部が設けられ、該開口部を含
む全面にアルミニウム膜を堆積して選択的にエッチング
され、アルミニウム配線１１が設けられる。As shown in FIG. 4, an aluminum film is deposited on the entire surface including the silicon oxide film 3 having a window for wiring connection provided in the same manner as in the first example and selectively etched to form a diffusion region of the window. Aluminum wiring 6 connected to 2 and aluminum wiring 10 adjacent to aluminum wiring 6 are provided, and silicon nitride film 4 is provided on the entire surface including aluminum wirings 6 and 10. Next, an opening is provided in the silicon nitride film 4 on the aluminum wiring 6, and an aluminum film is deposited on the entire surface including the opening and selectively etched to provide an aluminum wiring 11.
ここで、アルミニウム配線１１はアルミニウム配線６お
よび１０の間に生じたシリコン窒化膜４の表面の凹部１
２にアルミニウム膜が均一に堆積されていないことが原
因となって断線を生ずることがある。Here, the aluminum wiring 11 is the concave portion 1 formed on the surface of the silicon nitride film 4 between the aluminum wirings 6 and 10.
The disconnection may occur due to the fact that the aluminum film is not uniformly deposited on 2.
上述した従来の半導体装置の製造方法は、金属配線を被
覆している絶縁膜に発生する歪のために金属配線が応力
を受けて亀裂を生じ、断線するという問題点がある。The above-described conventional method for manufacturing a semiconductor device has a problem in that the metal wiring receives a stress due to a strain generated in the insulating film covering the metal wiring to generate a crack, which causes disconnection.
また、金属配線を被覆する絶縁膜の表面は凹部や段差が
多く該絶縁膜上に形成する上層配線の断線を発生させる
という問題点がある。Further, there is a problem in that the surface of the insulating film covering the metal wiring has many recesses and steps, which causes disconnection of the upper layer wiring formed on the insulating film.
本発明の半導体装置の製造方法は、半導体素子領域を有
する半導体基板上に前記半導体素子領域の配線接続用窓
を有する下層絶縁膜を設け前記窓を含む前記下層絶縁膜
上に第１の絶縁膜を設ける工程と、前記窓の上の前記第
１の絶縁膜を選択的にエッチングして配線形成用溝部を
設ける工程と、前記半導体基板に負の電圧を印加した状
態でスパッタリング法により前記溝部内にのみ選択的に
金属層を堆積して上面が前記第１の絶縁膜表面とほぼ同
一面になるように埋込んだ配線を形成する工程と、前記
配線を含む前記第１の絶縁膜上に第２の絶縁膜を形成す
る工程とを含んで構成される。A method of manufacturing a semiconductor device according to the present invention includes providing a lower insulating film having a wiring connection window of the semiconductor element region on a semiconductor substrate having a semiconductor element region, and forming a first insulating film on the lower insulating film including the window. A step of providing a wiring forming groove by selectively etching the first insulating film on the window, and a step of sputtering in the groove while a negative voltage is applied to the semiconductor substrate. Forming a wiring in which a metal layer is selectively deposited only on the first insulation film and the upper surface thereof is substantially flush with the surface of the first insulation film; and on the first insulation film including the wiring. And a step of forming a second insulating film.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｄ）は、本発明の第１の実施例を説明
するための工程順に示した半導体チップの断面図であ
る。1A to 1D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention.
まず、第１図に示すように、一導電型の半導体基板１の
上に逆導電型の拡散領域２を設ける。次に、全面にシリ
コン酸化膜３を形成して選択的にエッチングし拡散領域
２の上に配線接続用窓を設け、該窓を含む全面にプラズ
マＣＶＤ法によりシリコン窒化膜４を１μｍの厚さに形
成する。First, as shown in FIG. 1, a diffusion region 2 of opposite conductivity type is provided on a semiconductor substrate 1 of one conductivity type. Next, a silicon oxide film 3 is formed on the entire surface and selectively etched to provide a wiring connection window on the diffusion region 2, and a silicon nitride film 4 having a thickness of 1 μm is formed on the entire surface including the window by plasma CVD. To form.
次に、第１図（ｂ）に示すように、前記窓を含む領域に
シリコン窒化膜４を選択的にエッチングして配線形成用
溝部５を設ける。Next, as shown in FIG. 1B, the silicon nitride film 4 is selectively etched in the region including the window to provide a wiring forming groove 5.
次に、第１図（ｃ）に示すように、半導体基板１に負の
電圧を印加した状態でスパッタリング法によりアルミニ
ウミ層を堆積する。この際シリコン基板１１に印加した
負の電圧のためにアルミニウム分子が被着されると同時
にスパッタガスであるアルゴンイオンによりエッチング
されるためと、アルゴンイオンの入射により半導体基板
１が加熱されて高温となり被着したアルミニウム分子が
移動して、アルミニウム層を溝部５のみに選択的に堆積
することができ、アルミニウム配線６が形成される。Next, as shown in FIG. 1C, an aluminum layer is deposited by a sputtering method with a negative voltage applied to the semiconductor substrate 1. At this time, the aluminum molecules are deposited due to the negative voltage applied to the silicon substrate 11 and are simultaneously etched by the argon ions that are the sputtering gas. The incidence of the argon ions heats the semiconductor substrate 1 to a high temperature. The deposited aluminum molecules move, and the aluminum layer can be selectively deposited only in the groove portion 5, and the aluminum wiring 6 is formed.
次に、第１図（ｄ）に示すように、全面にプラズマＣＶ
Ｄによりシリコン窒化膜７を形成する。Next, as shown in FIG. 1 (d), plasma CV is formed on the entire surface.
A silicon nitride film 7 is formed by D.
第２図（ａ）〜（ｄ）は本発明の第２の実施例を説明す
るための工程順に示した半導体チップの断面図である。2A to 2D are cross-sectional views of the semiconductor chip shown in the order of steps for explaining the second embodiment of the present invention.
第２図（ａ）に示すように、第１の実施例と同様にして
一導電型の半導体基板１の上に逆導電型の拡散領域２を
設け、全面にシリコン酸化膜３を形成し選択的にエッチ
ングして拡散領域２の上に配線接続用窓を設ける。次
に、全面にプラズマＣＶＤでシリコン窒化膜４を１μｍ
の厚さに形成して選択的にエッチングし、前記窓を含む
領域に配線形成用溝部５を設ける。As shown in FIG. 2A, similar to the first embodiment, a diffusion region 2 of the opposite conductivity type is provided on a semiconductor substrate 1 of the one conductivity type, and a silicon oxide film 3 is formed on the entire surface. By etching, a wiring connection window is provided on the diffusion region 2. Next, a silicon nitride film 4 is formed on the entire surface by plasma CVD to a thickness of 1 μm.
To a thickness of 10 mm and selectively etched to form a wiring forming groove 5 in a region including the window.
次に、第２図（ｂ）に示すように、スパッタリング法に
より溝部５を含む全面にアルミニウム層８を１μｍの膜
厚に堆積する。Next, as shown in FIG. 2B, an aluminum layer 8 is deposited to a thickness of 1 μm on the entire surface including the groove 5 by a sputtering method.
次に、第２図（ｃ）に示すように、全面にレーザービー
ムを１〜５０Ｊ／cm2のパワーで１×１０-6〜１×１０
-4秒照射してアルミニウム膜８の表面を溶かし、溝部５
にアルミニウム膜５を埋め込んで、アルミニウム５の表
面を平坦にする。Next, as shown in FIG. 2 (c), a laser beam is applied to the entire surface at a power of 1 to 50 J / cm 2 at 1 × 10 −6 to 1 × 10.
-It is irradiated for 4 seconds to melt the surface of the aluminum film 8 and the groove 5
The aluminum film 5 is buried in the aluminum to flatten the surface of the aluminum 5.
次に、第２図（ｄ）に示すように、異方性エッチング法
によりちょうどシリコン窒化膜４の表面が露出するよう
に全面を均一にエッチングして除去し、溝部５のみにア
ルミニウム層８を残してアルミニウム配線６を形成す
る。次に全面にプラズマＣＶＤによりシリコン窒化膜７
を形成する。Next, as shown in FIG. 2D, the entire surface is uniformly etched and removed by an anisotropic etching method so that the surface of the silicon nitride film 4 is just exposed, and the aluminum layer 8 is formed only on the groove portion 5. The aluminum wiring 6 is formed by leaving. Next, a silicon nitride film 7 is formed on the entire surface by plasma CVD.
To form.
同様の手順を繰返すことにより表面の平坦な多層配線が
複数層形成できる。By repeating the same procedure, it is possible to form a plurality of layers of multilayer wiring having a flat surface.
以上説明したように本発明は、半導体基板上に設けた絶
縁膜上にあらかじめ、配線層の膜厚に相当する第１に絶
縁膜を堆積し、これを選択的にエッチングして配線形成
用溝を設け、該溝内にのみ埋込み上面が第１の絶縁膜の
表面とほぼ同一面になるように金属層を形成して配線を
形成し、全面に第２の絶縁膜を形成することにより、金
属層に局部的に応力が加わることがなく、断線事故を防
止する効果がある。As described above, according to the present invention, the first insulating film corresponding to the film thickness of the wiring layer is previously deposited on the insulating film provided on the semiconductor substrate, and the first insulating film is selectively etched to form the wiring forming groove. Is formed, a metal layer is formed only in the groove so that the upper surface is substantially flush with the surface of the first insulating film, wiring is formed, and the second insulating film is formed on the entire surface. There is no local stress applied to the metal layer, which has the effect of preventing disconnection accidents.
また、配線を被覆する絶縁膜の表面が常に平坦であるた
め、複数層の配線を形成しても段差による断線を生ずる
ことがないと云う効果がある。Further, since the surface of the insulating film that covers the wiring is always flat, there is an effect that even if a plurality of layers of wiring are formed, disconnection due to a step does not occur.
また、本発明では第１の絶縁膜に形成した配線形成用溝
部内にのみ選択的に金属層を堆積して充填させることに
より、第１の絶縁膜の表面とほぼ同一面の配線を形成す
ることができ、溝部内に金属層を埋込み且つ平坦化する
ための犠牲層の塗布やエッチバック等の工程を省略して
工程の簡略化を実現できるという効果を有する。Further, in the present invention, the metal layer is selectively deposited and filled only in the wiring forming groove formed in the first insulating film to form a wiring substantially flush with the surface of the first insulating film. Therefore, there is an effect that the steps such as application of a sacrifice layer for flattening and flattening the metal layer in the groove and flattening the step can be omitted and the steps can be simplified.
第１図および第２図は本発明の第１および第２の実施例
を説明するための工程順に示した半導体チップの断面
図、第３図および第４図は従来の半導体装置の第１およ
び第２の例を説明するための半導体チップの断面図であ
る。 １…半導体基板、２…拡散領域、３…シリコン酸化膜、
４…シリコン窒化膜、５…溝部、６…アルミニウムの配
線、７…シリコン窒化膜、８…アルミニウム層、９…亀
裂、１０，１１…アルミニウム配線、１２…凹部。1 and 2 are cross-sectional views of a semiconductor chip, which are shown in the order of steps for explaining the first and second embodiments of the present invention, and FIGS. 3 and 4 are first and second embodiments of a conventional semiconductor device. It is a sectional view of a semiconductor chip for explaining the 2nd example. 1 ... Semiconductor substrate, 2 ... Diffusion region, 3 ... Silicon oxide film,
4 ... Silicon nitride film, 5 ... Groove portion, 6 ... Aluminum wiring, 7 ... Silicon nitride film, 8 ... Aluminum layer, 9 ... Crack, 10, 11 ... Aluminum wiring, 12 ... Recessed portion.
Claims (1)
記半導体素子領域の配線接続用窓を有する下層絶縁膜を
設け前記窓を含む前記下層絶縁膜上に第１の絶縁膜を設
ける工程と、前記窓の上の前記第１の絶縁膜を選択的に
エッチングして配線形成用溝部を設ける工程と、前記半
導体基板に負の電圧を印加した状態でスパッタリング法
により前記溝部内にのみ選択的に金属層を堆積して上面
が前記第１の絶縁膜表面とほぼ同一面になるように埋込
んだ配線を形成する工程と、前記配線を含む前記第１の
絶縁膜上に第２の絶縁膜を形成する工程とを含むことを
特徴とする半導体装置の製造方法。1. A step of providing a lower insulating film having a window for wiring connection of the semiconductor element region on a semiconductor substrate having a semiconductor element region, and providing a first insulating film on the lower insulating film including the window, A step of selectively etching the first insulating film on the window to provide a groove portion for wiring formation; and a step of selectively applying a negative voltage to the semiconductor substrate only in the groove portion by a sputtering method. A step of depositing a metal layer to form a buried wiring such that an upper surface thereof is substantially flush with the surface of the first insulating film; and a second insulating film on the first insulating film including the wiring. And a step of forming a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62111821A JPH0611044B2 (en) | 1987-05-07 | 1987-05-07 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62111821A JPH0611044B2 (en) | 1987-05-07 | 1987-05-07 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63275142A JPS63275142A (en) | 1988-11-11 |
| JPH0611044B2 true JPH0611044B2 (en) | 1994-02-09 |
Family
ID=14571002
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62111821A Expired - Lifetime JPH0611044B2 (en) | 1987-05-07 | 1987-05-07 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0611044B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ATE150585T1 (en) * | 1990-05-31 | 1997-04-15 | Canon Kk | METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE HAVING A HIGH DENSITY WIRING STRUCTURE |
| JPH09153545A (en) * | 1995-09-29 | 1997-06-10 | Toshiba Corp | Semiconductor device and manufacturing method thereof |
| JP2005175252A (en) * | 2003-12-12 | 2005-06-30 | Ricoh Co Ltd | Semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62290148A (en) * | 1986-06-09 | 1987-12-17 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1987
- 1987-05-07 JP JP62111821A patent/JPH0611044B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63275142A (en) | 1988-11-11 |
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