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JPH0611049B2 - Method for manufacturing semiconductor device - Google Patents
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JPH0611049B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JPH0611049B2
JPH0611049B2 JP62071286A JP7128687A JPH0611049B2 JP H0611049 B2 JPH0611049 B2 JP H0611049B2 JP 62071286 A JP62071286 A JP 62071286A JP 7128687 A JP7128687 A JP 7128687A JP H0611049 B2 JPH0611049 B2 JP H0611049B2
Authority
JP
Japan
Prior art keywords
film
polycrystalline silicon
insulating film
diffusion region
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62071286A
Other languages
Japanese (ja)
Other versions
JPS63236347A (en
Inventor
秀市 大屋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP62071286A priority Critical patent/JPH0611049B2/en
Publication of JPS63236347A publication Critical patent/JPS63236347A/en
Publication of JPH0611049B2 publication Critical patent/JPH0611049B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device.

〔従来の技術〕[Conventional technology]

半導体装置の素子領域と配線とのコンタクトを得る手段
として素子領域と配線が直接コンタクトできる多結晶シ
リコン膜が用いられている。
As a means for obtaining contact between an element region and a wiring of a semiconductor device, a polycrystalline silicon film which can directly contact the element region and the wiring is used.

第2図(a),(b)は従来の半導体装置の製造方法を
説明するための工程順に示した半導体チップの断面図で
ある。
FIGS. 2A and 2B are cross-sectional views of a semiconductor chip showing the order of steps for explaining a conventional method for manufacturing a semiconductor device.

第2図(a)に示すように、P型シリコン基板1の表面
に素子形成領域を区画する素子分離用フィールド絶縁膜
2を形成し、前記素子形成領域を含む表面に絶縁膜3を
形成する。次に、前記素子形成領域内にイオン注入法で
N型拡散領域5を選択的に形成し、N型拡散領域5の上
の絶縁膜3の一部を選択的に開口してコンタクト用窓を
形成する。
As shown in FIG. 2A, an element isolation field insulating film 2 for partitioning an element forming region is formed on the surface of a P-type silicon substrate 1, and an insulating film 3 is formed on the surface including the element forming region. . Next, an N-type diffusion region 5 is selectively formed in the element formation region by an ion implantation method, and a part of the insulating film 3 on the N-type diffusion region 5 is selectively opened to form a contact window. Form.

次に、第2図(b)に示すように、前記窓に露出するN
型拡散領域5の一部を覆い、且つ絶縁膜3の上に延在し
てN型不純物を含む多結晶シリコン膜4を選択的に形成
し、熱処理により多結晶シリコン膜4とN型拡散領域と
のコンタクトを得る。
Next, as shown in FIG. 2B, the N exposed to the window is
A polycrystalline silicon film 4 which covers a part of the type diffusion region 5 and extends on the insulating film 3 and selectively contains an N type impurity is formed, and the polycrystalline silicon film 4 and the N type diffusion region are heat-treated. Get in touch with.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

上述した従来の半導体装置の製造方法は拡散領域のコン
タクト抵抗の増大を抑える為にコンタクト接触面積を小
さくすることができない。即ち拡散領域と多結晶シリコ
ン膜間の重なり部分の面積が装置の平面的な縮小の障害
となる。
In the above-described conventional semiconductor device manufacturing method, the contact contact area cannot be reduced in order to suppress an increase in contact resistance in the diffusion region. That is, the area of the overlapping portion between the diffusion region and the polycrystalline silicon film becomes an obstacle to the planar reduction of the device.

また、配線の抵抗を低くする為には、多結晶シリコン膜
に高濃度の不純物を添加する必要があるが、拡散領域と
多結晶シリコン膜が直接接触している為に、多結晶シリ
コン膜への不純物拡散時、或は、その後の製造工程上の
熱処理によって不純物がシリコン基板中に拡散しシリコ
ン基板表面の拡散領域の深さを増大させる。この拡散領
域深さの増大は、他の拡散領域との間の実効的な分離距
離を縮めて絶縁特性を悪化させる。それゆえに、拡散領
域間の絶縁性を確保する為フィールド絶縁膜の幅を広げ
て最小の分離間隔を大きくせねばならず、半導体素子微
細化の障害となる問題点がある。
Further, in order to reduce the resistance of the wiring, it is necessary to add a high concentration of impurities to the polycrystalline silicon film. However, since the diffusion region and the polycrystalline silicon film are in direct contact, When the impurities are diffused, or by the heat treatment in the subsequent manufacturing process, the impurities diffuse into the silicon substrate and increase the depth of the diffusion region on the surface of the silicon substrate. This increase in the diffusion region depth shortens the effective separation distance from other diffusion regions and deteriorates the insulation characteristics. Therefore, in order to ensure the insulation between the diffusion regions, the width of the field insulating film must be widened to increase the minimum separation distance, which is a problem for miniaturization of semiconductor elements.

本発明の目的は、半導体素子の微細化を可能とする半導
体装置の製造方法を提供することにある。
An object of the present invention is to provide a method for manufacturing a semiconductor device that enables miniaturization of semiconductor elements.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置の製造方法は、一導電型の半導体基
板の一主面に素子形成領域を区画する素子分離用のフィ
ールド絶縁膜を形成する工程と、前記素子形成領域を含
む表面に絶縁膜を形成し前記絶縁膜上に多結晶シリコン
膜を選択的に形成する工程と、前記多結晶シリコン膜お
よび前記フィールド絶縁膜をマスクとして不純物をイオ
ン注入し前記素子形成領域に逆導電型の拡散領域を形成
する工程と、前記多結晶シリコン膜をマスクとして前記
拡散領域上の前記絶縁膜を選択的に除去してコンタクト
用窓を形成する工程と、前記絶縁膜上の前記多結晶シリ
コン膜および前記コンタクト用窓に露出した前記拡散領
域を含む表面に高融点金属膜を形成する工程と、不活性
ガス雰囲気中で熱処理し前記高融点金属膜と接触してい
る前記多結晶シリコン膜および前記拡散領域表面を反応
させて高融点金属硅化物膜を形成する工程と、未反応の
前記高融点金属膜を除去して前記高融点金属硅化物膜に
より前記拡散領域とコンタクトする配線を形成する工程
とを含んで構成される。
A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a field insulating film for element isolation for partitioning an element forming region on one main surface of a semiconductor substrate of one conductivity type, and an insulating film on a surface including the element forming region. And selectively forming a polycrystalline silicon film on the insulating film, and by using the polycrystalline silicon film and the field insulating film as a mask, impurities are ion-implanted to form a reverse conductivity type diffusion region in the element formation region. A step of forming a contact window by selectively removing the insulating film on the diffusion region using the polycrystalline silicon film as a mask, the polycrystalline silicon film on the insulating film, and A step of forming a refractory metal film on the surface including the diffusion region exposed in the contact window; and a step of heat-treating in an inert gas atmosphere to contact the polycrystalline silicon film in contact with the refractory metal film. Forming a refractory metal silicide film by reacting the surface of the diffusion film and the surface of the diffusion region, and wiring for removing the unreacted refractory metal film and contacting the diffusion region with the refractory metal silicide film And a step of forming.

〔実施例〕 次に、本発明の実施例について図面を参照して説明す
る。
[Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings.

第1図(a)〜(e)は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図である。
1A to 1E are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

第1図(a)に示すように、P型シリコン基板1の表面
に素子形成領域を区画する素子分離用フィールド絶縁膜
2を形成し、前記素子形成領域を含む表面に膜厚200
Åの絶縁膜3を形成する。次に、絶縁膜3の上に一部が
前記素子形成領域と重なるようにリンを添加した膜厚0.
4μmの多結晶シリコン膜4を選択的に形成する。
As shown in FIG. 1A, an element isolation field insulating film 2 for partitioning an element forming region is formed on the surface of a P-type silicon substrate 1, and a film thickness of 200 is formed on the surface including the element forming region.
The insulating film 3 of Å is formed. Next, a film thickness of phosphorous was added on the insulating film 3 so that a part thereof overlaps the element forming region.
A polycrystalline silicon film 4 of 4 μm is selectively formed.

次に、第1図(b)に示すように、多結晶シリコン膜4
およびフィールド絶縁膜2をマスクとしてヒ素をイオン
注入し、前記素子形成領域内にN型拡散領域5を形成す
る。次に、多結晶シリコン膜4をマスクとしてN型拡散
領域上の絶縁膜3を選択的に除去してコンタクト用窓を
形成する。
Next, as shown in FIG. 1B, the polycrystalline silicon film 4
Arsenic is ion-implanted using the field insulating film 2 as a mask to form an N-type diffusion region 5 in the element forming region. Next, the insulating film 3 on the N-type diffusion region is selectively removed using the polycrystalline silicon film 4 as a mask to form a contact window.

次に、第1図(c)に示すように、前記窓の露出したN
型拡散領域5を含む表面に膜厚500Åのチタニウム膜
6を堆積させる。
Next, as shown in FIG. 1 (c), the exposed N of the window is
A titanium film 6 having a film thickness of 500 Å is deposited on the surface including the mold diffusion region 5.

次に、第1図(d)に示すように、600℃の窒素雰囲
気中で60分間の処理を行い、絶縁膜3上の多結晶シリ
コン膜4およびN型拡散領域5と接触しているチタニウ
ム膜6を反応させて厚さ約0.1μmの硅化チタニウム
膜7を形成する。このとき、絶縁膜3の側壁部のチタニ
ウム膜6は上部の多結晶シリコン膜4および下部のN型
拡散領域表面から供給されるシリコンと反応して硅化チ
タニウム膜が形成され、硅化チタニウム膜7はN型拡散
領域とコンタクトし絶縁膜3上まで連続した状態で形成
される。
Next, as shown in FIG. 1 (d), a treatment is performed for 60 minutes in a nitrogen atmosphere at 600 ° C., and titanium which is in contact with the polycrystalline silicon film 4 on the insulating film 3 and the N-type diffusion region 5 is processed. The film 6 is reacted to form a titanium silicate film 7 having a thickness of about 0.1 μm. At this time, the titanium film 6 on the side wall of the insulating film 3 reacts with the silicon supplied from the upper polycrystalline silicon film 4 and the surface of the lower N-type diffusion region to form a titanium silicide film, and the titanium silicide film 7 is formed. It is formed in contact with the N-type diffusion region and continuously up to the insulating film 3.

次に、第1図(e)に示すように、アニモニアと過酸化
水素の混合溶液により未反応のチタニウム膜6を除去
し、N型拡散領域とコンタクトし絶縁膜3上に延在する
配線を得る。
Next, as shown in FIG. 1 (e), the unreacted titanium film 6 is removed by a mixed solution of animonia and hydrogen peroxide, and a wiring which contacts the N-type diffusion region and extends on the insulating film 3 is formed. obtain.

なお、高融点金属としてはチタニウム以外に例えばタン
グステン,モリブデン等も使用できる。
In addition to titanium, for example, tungsten, molybdenum, or the like can be used as the refractory metal.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明は、素子領域内の拡散領域表
面とコンタクトし絶縁膜上の多結晶シリコン膜上に延在
する高融点金属硅化物膜を形成することにより、拡散領
域表面に不純物を添加した多結晶シリコン膜を直接接触
させることがなく低抵抗のコンタクトが形成できるた
め、拡散領域と多結晶シリコン膜の重なり面積を小さく
でき、拡散領域の深さの増大を抑制して他の拡散領域と
の実効的な分離距離を縮める要因を取除き、半導体素子
の微細化を可能にする効果がある。
As described above, the present invention forms a refractory metal silicide film that contacts the surface of the diffusion region in the element region and extends on the polycrystalline silicon film on the insulating film, thereby removing impurities from the surface of the diffusion region. Since a low resistance contact can be formed without directly contacting the added polycrystalline silicon film, the overlapping area of the diffusion region and the polycrystalline silicon film can be made small, and the increase of the depth of the diffusion region can be suppressed to prevent other diffusion. There is an effect that it is possible to miniaturize the semiconductor element by removing the factor that shortens the effective separation distance from the region.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)〜(e)は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図、第2図
(a),(b)は従来の半導体装置の製造方法を説明す
るための工程順に示した半導体チップの断面図である。 1……P型シリコン基板、2……フィールド絶縁膜、3
……絶縁膜、4……多結晶シリコン膜、5……N型拡散
領域、6……チタニウム膜、7……硅化チタニウム膜。
1 (a) to 1 (e) are sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention, and FIGS. 2 (a) and 2 (b) are conventional semiconductor device manufacturing methods. FIG. 6 is a cross-sectional view of the semiconductor chip in the order of steps for explaining. 1 ... P-type silicon substrate, 2 ... field insulating film, 3
...... Insulating film, 4 ... Polycrystalline silicon film, 5 ... N type diffusion region, 6 ... Titanium film, 7 ... Titanium silicide film.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】一導電型の半導体基板の一主面に素子形成
領域を区画する素子分離用のフィールド絶縁膜を形成す
る工程と、前記素子形成領域を含む表面に絶縁膜を形成
し前記絶縁膜上に多結晶シリコン膜を選択的に形成する
工程と、前記多結晶シリコン膜および前記フィールド絶
縁膜をマスクとして不純物をイオン注入し前記素子形成
領域に逆導電型の拡散領域を形成する工程と、前記多結
晶シリコン膜をマスクとして前記拡散領域上の前記絶縁
膜を選択的に除去してコンタクト用窓を形成する工程
と、前記絶縁膜上の前記多結晶シリコン膜および前記コ
ンタクト用窓に露出した前記拡散領域を含む表面に高融
点金属膜を形成する工程と、不活性ガス雰囲気中で熱処
理し前記高融点金属膜と接触している前記多結晶シリコ
ン膜および前記拡散領域表面を反応させて高融点金属硅
化物膜を形成する工程と、未反応の前記高融点金属膜を
除去して前記高融点金属硅化物膜により前記拡散領域と
コンタクトする配線を形成する工程とを含むことを特徴
とする半導体装置の製造方法。
1. A step of forming a field insulating film for element isolation for partitioning an element forming area on one main surface of a semiconductor substrate of one conductivity type, and an insulating film is formed on a surface including the element forming area to perform the insulation. A step of selectively forming a polycrystalline silicon film on the film; a step of implanting impurities with the polycrystalline silicon film and the field insulating film as a mask to form a diffusion region of opposite conductivity type in the element forming region A step of selectively removing the insulating film on the diffusion region using the polycrystalline silicon film as a mask to form a contact window, and exposing the polycrystalline silicon film on the insulating film and the contact window A step of forming a refractory metal film on the surface including the diffusion region, the polycrystalline silicon film which is heat-treated in an inert gas atmosphere and is in contact with the refractory metal film, and the diffusion. A step of reacting the surface of the region to form a refractory metal silicide film; a step of removing the unreacted refractory metal film and forming a wiring contacting the diffusion region by the refractory metal silicide film. A method of manufacturing a semiconductor device, comprising:
JP62071286A 1987-03-24 1987-03-24 Method for manufacturing semiconductor device Expired - Lifetime JPH0611049B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62071286A JPH0611049B2 (en) 1987-03-24 1987-03-24 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62071286A JPH0611049B2 (en) 1987-03-24 1987-03-24 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS63236347A JPS63236347A (en) 1988-10-03
JPH0611049B2 true JPH0611049B2 (en) 1994-02-09

Family

ID=13456304

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62071286A Expired - Lifetime JPH0611049B2 (en) 1987-03-24 1987-03-24 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0611049B2 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6037774A (en) * 1983-08-10 1985-02-27 Mitsubishi Electric Corp Manufacture of semiconductor device
JPH0611051B2 (en) * 1984-06-14 1994-02-09 三菱電機株式会社 Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
JPS63236347A (en) 1988-10-03

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