JPH0611052B2 - Transistor - Google Patents
TransistorInfo
- Publication number
- JPH0611052B2 JPH0611052B2 JP59149919A JP14991984A JPH0611052B2 JP H0611052 B2 JPH0611052 B2 JP H0611052B2 JP 59149919 A JP59149919 A JP 59149919A JP 14991984 A JP14991984 A JP 14991984A JP H0611052 B2 JPH0611052 B2 JP H0611052B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- base
- emitter
- electrode
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000015556 catabolic process Effects 0.000 description 7
- 230000002093 peripheral effect Effects 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 239000010410 layer Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000000605 extraction Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
- H10D62/126—Top-view geometrical layouts of the regions or the junctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/133—Emitter regions of BJTs
- H10D62/135—Non-interconnected multi-emitter structures
Landscapes
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】 (イ)産業上の利用分野 本発明はトランジスタ、特に高周波高電流容量化を図っ
たトランジスタの改良に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to an improvement of a transistor, particularly a transistor having a high frequency and a high current capacity.
(ロ)従来の技術 従来よりトランジスタの電流容量の増大を図る構造とし
てはエミッタの有効面積を増大させることが知られてい
る。この構造としては第2図に示すメッシュベース構造
あるいは島状エミッタ構造がある。第2図において、
(1)は半導体基板より成るコレクタ領域、(2)はベース領
域、(3)は島状エミッタ領域であり、点線で示す(4)はベ
ース領域(2)にオーミック接触したベース電極、(5)は各
島状エミッタ領域(3)…(3)にオーミック接触したエミッ
タ電極である。(B) Conventional Technology As a structure for increasing the current capacity of a transistor, it has been known to increase the effective area of the emitter. As this structure, there is a mesh base structure or an island-shaped emitter structure shown in FIG. In FIG.
(1) is a collector region made of a semiconductor substrate, (2) is a base region, (3) is an island-shaped emitter region, (4) shown by a dotted line is a base electrode in ohmic contact with the base region (2), (5) ) Is an emitter electrode in ohmic contact with each of the island-shaped emitter regions (3) ... (3).
斯上の構造では多数の島状エミッタ領域(3)…(3)により
ベースエミッタ接合の周辺長を増大でき高電流容量化を
容易に達成できる。しかしながら第2図からも明らかな
様に島状エミッタ領域(3)…(3)の面積の増加とともにメ
ッシュ状のベース領域(2)の面積も増加して、チップ面
積の増加となる。ところがベース電極にはコレクタ電流
の1/hFEの電流しか流れないので、ベース領域(2)
の増加はトランジスタの高電流容量化にほとんど寄与し
ない。In the above structure, the peripheral length of the base-emitter junction can be increased by the large number of island-shaped emitter regions (3) ... (3), and high current capacity can be easily achieved. However, as is clear from FIG. 2, as the area of the island-shaped emitter regions (3) ... (3) increases, the area of the mesh-shaped base region (2) also increases and the chip area increases. However, since only 1 / h FE of collector current flows through the base electrode, the base region (2)
The increase of 1 does not contribute to the increase in current capacity of the transistor.
そこで第3図に示す様にメッシュエミッタ構造のトラン
ジスタが考えられた。第3図に於いて、(10)は半導体基
板より成るコレクタ領域、(11)はベース領域、(12)はメ
ッシュ状のエミッタ領域であり、点線で示す(13)はエミ
ッタ領域(12)にオーミック接触したエミッタ電極、(14)
は点在するベース領域(11)にオーミック接触したベース
電極である。Therefore, a transistor having a mesh emitter structure as shown in FIG. 3 was considered. In FIG. 3, (10) is a collector region made of a semiconductor substrate, (11) is a base region, (12) is a mesh-shaped emitter region, and (13) shown by a dotted line is an emitter region (12). Ohmic contacted emitter electrode, (14)
Is a base electrode in ohmic contact with the scattered base regions (11).
斯上の構造ではメッシュ状エミッタ領域(12)によりエミ
ッタ面積の増大のみを図ることができるので、チップ面
積の増大防止にはかなり有効である。しかしながら第3
図からも明らかな様にエミッタ電極(13)とベース電極(1
4)を櫛歯状に形成するためにエミッタ電極(13)はメッシ
ュ状エミッタ領域(12)の約半分の面積としかオーミック
接触を行なえず、エミッタ領域(12)の面積の増大は実現
されるがエミッタ電極(13)の面積の増大は図れないので
ある。従ってメッシュ状エミッタ領域(12)を十分に活用
できず結局メッシュ状エミッタ領域(12)は電流容量の増
加の上では十分に働いていないのである。In the above structure, only the area of the emitter can be increased by the mesh-shaped emitter region (12), which is quite effective in preventing the increase of the chip area. However, the third
As is clear from the figure, the emitter electrode (13) and the base electrode (1
In order to form 4) in the shape of a comb, the emitter electrode (13) can make ohmic contact with only about half the area of the mesh-shaped emitter region (12), and the increase of the area of the emitter region (12) is realized. However, the area of the emitter electrode (13) cannot be increased. Therefore, the mesh-shaped emitter region (12) cannot be fully utilized, and the mesh-shaped emitter region (12) does not work sufficiently to increase the current capacity.
そこで更に改良を重ね、第4図(イ)(ロ)に示す様に多層電
極構造のメッシュエミッタを有するトランジスタを考え
た。斯るトランジスタはシリコン半導体基板より成るコ
レクタ領域(20)と、ベース領域(21)と、メッシュ状のエ
ミッタ領域(22)とを備え、エミッタ領域(22)はベース領
域(21)のほぼ全表面に配置され、ベース領域(21)のコン
タクト領域(23)…(23)は多数島状にエミッタ領域(22)内
にエミッタ領域(22)に完全に囲まれて配置されている。
基板(20)表面のシリコン酸化膜(24)上には点線で示す一
層目の第1ベース電極(25)と第1エミッタ電極(26)が形
成され、第1ベース電極(25)はベース領域(21)の各コン
タクト領域(23)…(23)にオーミックコンタクトし多数の
島状をなし、第1エミッタ電極(26)はエミッタ領域(22)
のほぼ全表面とオーミックコンタクトしてメッシュ状を
なしている。第1ベース電極(25)および第1エミッタ電
極(26)はポリイミド等の層間絶縁膜(27)で被覆され、層
間絶縁膜(27)上には一点破線で示す二層目の第2ベース
電極(28)および第2エミッタ電極(29)が形成される。第
2ベース電極(28)は島状に散在した多数の第1ベース電
極(25)…(25)に夫々オーミックコンタクトし、櫛歯状に
一方向に延在されて形成される。第2エミッタ電極(29)
はメッシュ状の第1エミッタ電極(26)の斜線で示す外周
部でオーミックコンタクトし、ボンディングパッドまで
延在されている。Therefore, after further improvement, a transistor having a mesh emitter having a multilayer electrode structure as shown in FIGS. 4 (a) and 4 (b) was considered. Such a transistor comprises a collector region (20) made of a silicon semiconductor substrate, a base region (21), and a mesh-shaped emitter region (22), and the emitter region (22) is almost the entire surface of the base region (21). The contact regions (23) ... (23) of the base region (21) are arranged in a multi-island shape within the emitter region (22) so as to be completely surrounded by the emitter region (22).
A first base electrode (25) and a first emitter electrode (26) of a first layer shown by a dotted line are formed on the silicon oxide film (24) on the surface of the substrate (20), and the first base electrode (25) is a base region. Each of the contact regions (23) of (21) is ohmic-contacted with each other to form a number of islands, and the first emitter electrode (26) is an emitter region (22).
Has a mesh-like shape with ohmic contact with almost the entire surface. The first base electrode (25) and the first emitter electrode (26) are covered with an interlayer insulating film (27) of polyimide or the like, and the second base electrode of the second layer indicated by a dashed line is formed on the interlayer insulating film (27). (28) and the second emitter electrode (29) are formed. The second base electrodes 28 are formed in ohmic contact with a large number of island-shaped first base electrodes 25, ..., 25, respectively, and extend in one direction like comb teeth. Second emitter electrode (29)
Makes ohmic contact at the outer peripheral portion of the mesh-shaped first emitter electrode (26) indicated by the diagonal lines and extends to the bonding pad.
(ハ)発明が解決しようとする問題点 斯上の構造に依ればメッシュ状エミッタ領域(22)のほぼ
全面に第1エミッタ電極(26)を配置できるので、メッシ
ュ状エミッタ領域(22)を効率よく動作させることができ
電流容量の増大を図れる。(C) Problems to be Solved by the Invention According to the above structure, the first emitter electrode (26) can be arranged on almost the entire surface of the mesh-shaped emitter region (22). It can be operated efficiently and the current capacity can be increased.
しかしながら高周波化を図るにはメッシュ状エミッタ領
域(22)の巾を小さくしてパターンを微細化する必要があ
る。第4図(イ)に示すパターンをそのまま微細化すると
ベース領域(21)の各コンタクト領域(23)…(23)も縮小さ
れて微細パターンとなる。この結果ベース領域(21)の各
コンタクト領域(23)…(23)と第1ベース電極(25)…(25)
のコンタクト面積も小さくなるためベース取出し抵抗の
増加を招く。特に高電流化を要求されるパワートランジ
スタではベース電流の増大も要求され斯るパターンでは
この要求を満足できない欠点がある。更に静電破壊耐量
についてもベース領域側に集中するので、斯るパターン
ではあまり高くならない欠点がある。However, in order to increase the frequency, it is necessary to reduce the width of the mesh-shaped emitter region (22) and miniaturize the pattern. When the pattern shown in FIG. 4 (a) is miniaturized as it is, each contact region (23) ... (23) of the base region (21) is also reduced to be a fine pattern. As a result, each contact region (23) ... (23) of the base region (21) and the first base electrode (25) ... (25)
Since the contact area of is also small, the resistance for taking out the base increases. In particular, a power transistor, which is required to have a high current, is also required to increase the base current, and this pattern has a drawback that this requirement cannot be satisfied. Further, since the electrostatic breakdown resistance is also concentrated on the base region side, there is a drawback that such a pattern does not increase much.
(ニ)問題点を解決するための手段 本発明は斯上した欠点に鑑みてなされ、ベース領域の島
状の各コンタクト領域を長方形状に形成することにより
従来の欠点を完全に除去したトランジスタを提供するも
のである。(D) Means for Solving the Problems The present invention has been made in view of the above drawbacks, and a transistor in which the conventional drawbacks are completely eliminated by forming each of the island-shaped contact regions of the base region in a rectangular shape is provided. It is provided.
(ホ)作用 本発明ではベース領域の各コンタクト領域を長方形状と
することにより、ベース電極とのコンタクト面積の増大
を図る一方、メッシュ状エミッタ領域の面積を減少させ
ることなくベース電流の増大を実現している。(E) Function In the present invention, by making each contact region of the base region rectangular, the contact area with the base electrode is increased, while the base current is increased without reducing the area of the mesh-shaped emitter region. is doing.
(ヘ)実施例 本発明に依るトランジスタの一実施例を第1図(イ)(ロ)を
参照して説明する。第1図(イ)は本発明に依るトランジ
スタの上面図であり、第1図(ロ)は第1図(イ)のI−I線
断面図である。(F) Embodiment An embodiment of the transistor according to the present invention will be described with reference to FIGS. FIG. 1 (a) is a top view of a transistor according to the present invention, and FIG. 1 (b) is a sectional view taken along line I--I of FIG. 1 (a).
本発明に依るトランジスタはシリコン半導体基板より成
るコレクタ領域(30)と、ベース領域(31)と、メッシュ状
のエミッタ領域(32)とを備え、エミッタ領域(32)はベー
ス領域(31)のほぼ全面に配置され、ベース領域(31)のコ
ンタクト領域(33)…(33)は多数島状にエミッタ領域(32)
内にエミッタ領域(32)に完全に囲まれて配置されてい
る。基板(30)表面のシリコン酸化膜(34)上には点線で示
す一層目の第1ベース電極(35)と第1エミッタ電極(36)
が形成され、第1ベース電極(35)はベース領域(31)の各
コンタクト領域(33)…(33)にオーミックコンタクトし多
数の島状をなし、第1エミッタ電極(36)はエミッタ領域
(32)のほぼ全表面とオーミックコンタクトしてメッシュ
状をなしている。第1ベース電極(35)および第1エミッ
タ電極(36)はポリイミド等の層間絶縁膜(37)で被覆さ
れ、層間絶縁膜(37)上には一点破線で示す二層目の第2
ベース電極(38)および第2エミッタ電極(39)が形成され
る。第2ベース電極(38)は島状に散在した多数の第1ベ
ース電極(35)…(35)に夫々オーミックコンタクトし、櫛
歯状に一方向に延在されて形成される。第2エミッタ電
極(39)はメッシュ状の第1エミッタ電極(36)と帯状にオ
ーミックコンタクトして櫛歯状にボンディングパッドま
で延在されている。The transistor according to the present invention comprises a collector region (30) made of a silicon semiconductor substrate, a base region (31), and a mesh-shaped emitter region (32), and the emitter region (32) is almost the same as the base region (31). The contact regions (33) ... (33) of the base region (31) are arranged on the entire surface, and the emitter regions (32) are formed in a multi-island shape.
It is located within and completely surrounded by the emitter region (32). On the silicon oxide film (34) on the surface of the substrate (30), the first base electrode (35) and the first emitter electrode (36) of the first layer shown by the dotted line
, The first base electrode (35) is ohmic-contacted with each contact region (33) ... (33) of the base region (31) to form a large number of islands, and the first emitter electrode (36) is an emitter region.
It has a mesh shape with ohmic contact with almost the entire surface of (32). The first base electrode (35) and the first emitter electrode (36) are covered with an interlayer insulating film (37) made of polyimide or the like, and on the interlayer insulating film (37), the second layer of the second layer shown by a dashed line is drawn.
A base electrode (38) and a second emitter electrode (39) are formed. The second base electrodes 38 are formed in ohmic contact with a large number of island-shaped first base electrodes 35, ... 35, respectively, and extend in one direction like comb teeth. The second emitter electrode (39) is in ohmic contact with the mesh-shaped first emitter electrode (36) in a strip shape and extends to the bonding pad in a comb shape.
本発明の特徴は斯上したベース領域(31)の各コンタクト
領域(33)…(33)を長方形状に形成することにある。本発
明のコンタクト領域(33)は従来の第4図(イ)で示す正方
形状のコンタクト領域を2個あるいは3個連結して作ら
れるものである。この構造であればベース領域(31)の各
コンタクト領域(33)…(33)とメッシュ状エミッタ領域(3
2)との面積比を第4図(イ)に示す従来のものと同一に保
持したままで実現することが明らかであり、電流容量は
従来のものと同一に維持できる。一方各コンタクト領域
(33)…(33)は第1ベース電極(35)とのコンタクト孔を長
方形状とできるのでコンタクト面積を大巾に増加でき
る。具体的に2個連結したものは従来の約2倍のコンタ
クト面積を実現できる。この結果ベース領域(31)の取り
出し抵抗は大巾に低減でき、ベース電流の増加を容易に
図れる。またベース領域(31)の各コンタクト領域(33)…
(33)を長方形状とするのでセル1個当りの周辺長を従来
のものより増大でき、具体的に2個連結したものは従来
の1.5倍の周辺長を実現できる。この結果静電破壊耐量
も各コンタクト領域(33)…(33)の周辺長の増加に伴い電
界を分散でき、第1ベース電極(35)の破壊を防止でき
る。The feature of the present invention resides in that each contact region (33) ... (33) of the base region (31) is formed in a rectangular shape. The contact region (33) of the present invention is formed by connecting two or three square contact regions shown in FIG. 4 (A) in the related art. With this structure, each contact region (33) ... (33) of the base region (31) and the mesh-shaped emitter region (3
It is clear that this can be realized while keeping the area ratio with 2) the same as the conventional one shown in FIG. 4 (a), and the current capacity can be kept the same as the conventional one. While each contact area
Since the contact holes (33) ... (33) with the first base electrode (35) can be rectangular, the contact area can be greatly increased. Specifically, the connection of two can realize a contact area about twice as large as the conventional one. As a result, the extraction resistance of the base region (31) can be greatly reduced, and the base current can be easily increased. Also, each contact area (33) of the base area (31) ...
Since (33) has a rectangular shape, the peripheral length per cell can be increased as compared with the conventional one, and specifically, the two connected cells can realize the peripheral length 1.5 times that of the conventional one. As a result, with respect to electrostatic breakdown resistance, the electric field can be dispersed as the peripheral length of each contact region (33) ... (33) increases, and breakdown of the first base electrode (35) can be prevented.
本発明の実効を第5図乃至第7図を参照して説明する。
第5図はベース取り出し抵抗γ′bbの特性を示し、aは
一個のベース領域(31)のコンタクト領域(33)の横巾で、
bは縦巾を意味している。従来の構造(a/b=1)で
はγ′bbは約1Ωであったのが、a/b=2の本発明の
形状にするとγ′bbを約0.7Ωに改善できる。これは第
1ベース電極(31)のコンタクト領域(33)へのコンタクト
面積の増大によるものである。The effect of the present invention will be described with reference to FIGS.
FIG. 5 shows the characteristics of the base extraction resistance γ′bb, where a is the width of the contact region (33) of one base region (31),
b means the vertical width. In the conventional structure (a / b = 1), γ'bb was about 1Ω, but when the shape of the present invention with a / b = 2, γ'bb can be improved to about 0.7Ω. This is because the contact area of the first base electrode (31) to the contact region (33) is increased.
第6図は静電破壊耐量の特性を示している。この特性は
ベース電極に予じめ充電したコンデンサをベース電極に
接続して放電してトランジスタの破壊強度を求めるもの
である。第6図から本発明の構造(例えばa/b=2)
では従来より大巾に破壊強度が増大している。これは第
1ベース電極(35)を従来より大きく形成できるので、第
1ベース電極(35)での電界の集中による破壊を大巾に緩
和できたことによる。FIG. 6 shows the characteristics of electrostatic breakdown withstand capability. This characteristic is to obtain a breakdown strength of a transistor by connecting a capacitor charged in advance to the base electrode to the base electrode and discharging the capacitor. From FIG. 6, the structure of the present invention (for example, a / b = 2)
In, the breaking strength is greatly increased compared to the conventional one. This is because the first base electrode (35) can be formed larger than in the conventional case, so that the breakdown due to the concentration of the electric field in the first base electrode (35) can be greatly relaxed.
第7図はスイッチング時間tf(フォールタイム)の特
性を示す。tfも本発明の構造では従来より改善でき
る。これはベース領域(31)の各コンタクト領域(33)…(3
3)のストライプ化に伴いベース領域を強くできるので、
更にメッシュ状エミッタ領域(32)のパターンの微細化が
実現できることによるのである。FIG. 7 shows the characteristic of the switching time tf (fall time). With the structure of the present invention, tf can be improved as compared with the conventional case. This is for each contact area (33) of the base area (31)… (3
Since the base area can be strengthened with the stripe formation in 3),
Further, it is possible to realize a finer pattern of the mesh-shaped emitter region (32).
(ト)発明の効果 本発明の第1の効果はベース領域(31)の各コンタクト領
域(33)…(33)のストライプ化によりエミッタ面積とベー
ス面積との比を維持したままでベース電極のコンタクト
面積を増大できるので、ベース取り出し抵抗γ′bbを大
巾に低減できベース電流容量を増加できる。これにより
高電流高周波のパワートランジスタを実現できる。(G) Effect of the Invention The first effect of the present invention is to stripe the contact regions (33) ... (33) of the base region (31) while maintaining the ratio of the emitter area to the base area of the base electrode. Since the contact area can be increased, the base extraction resistance γ′bb can be greatly reduced and the base current capacity can be increased. This makes it possible to realize a high-current, high-frequency power transistor.
本発明の第2の効果はベース領域(31)の各コンタクト領
域(33)…(33)の周辺長を増大できるので、静電破壊耐量
を大きくできる。The second effect of the present invention is that the peripheral length of each contact region (33) ... (33) of the base region (31) can be increased, so that the electrostatic breakdown resistance can be increased.
第1図(イ)(ロ)は本発明に依るトランジスタを説明する上
面図およびI−I線断面図、第2図は従来のメッシュベ
ース構造のトランジスタを説明する上面図、第3図は従
来のメッシュエミッタ構造のトランジスタを説明する上
面図、第4図(イ)(ロ)は従来のメッシュエミッタ構造の改
良されたトランジスタを説明する上面図およびIV−IV線
断面図、第5図乃至第7図は本発明の各特性を説明する
特性図である。 主な図番の説明 (30)はコレクタ領域、(31)はベース領域、(32)はメッシ
ュ状エミッタ領域、(33)…(33)はベースコンタクト領
域、(35)は第1ベース電極、(36)は第1エミッタ電極、
(38)は第2ベース電極、(39)は第2エミッタ電極であ
る。1A and 1B are a top view and a cross-sectional view taken along the line I-I of a transistor according to the present invention, FIG. 2 is a top view of a conventional mesh-based structure transistor, and FIG. 3 is a conventional view. 4B is a top view for explaining a transistor having a mesh emitter structure of FIG. 4, FIGS. 4A and 4B are top views for explaining an improved transistor of a conventional mesh emitter structure and cross-sectional views taken along line IV-IV, FIGS. FIG. 7 is a characteristic diagram for explaining each characteristic of the present invention. Description of main drawing numbers (30) is collector region, (31) is base region, (32) is mesh emitter region, (33) ... (33) is base contact region, (35) is first base electrode, (36) is the first emitter electrode,
(38) is a second base electrode, and (39) is a second emitter electrode.
Claims (1)
領域を備え、該エミッタ領域を前記ベース領域のほぼ全
面に設け、前記ベース領域のコンタクト領域を前記エミ
ッタ領域内に多数の島状に配置し、前記エミッタ領域の
ほぼ全面にオーミック接触する格子状の第1層のエミッ
タ電極を設け、前記ベース領域のコンタクト領域にオー
ミック接触する島状の第1層のベース電極を設け、前記
第1層のエミッタ電極および前記第1層のベース電極と
絶縁膜を介して絶縁され、且つ前記第1層のエミッタ電
極とオーミック接触し前記島状の第1層のベース電極列
間に延在された第2層のエミッタ電極および前記島状の
第1層のベース電極列を連結し前記第2層のエミッタ電
極間に延在された第2層のベース電極とを備えたトラン
ジスタに於て、 前記ベース領域のコンタクト領域を長方形とし前記第2
層のベース電極の延在方向と直行した方向に前記長方形
の長手方向を設け、長辺と短辺とをおよそ2:1から
3:1としたことを特徴としたトランジスタ。1. A collector region, a base region and an emitter region are provided, the emitter region is provided on substantially the entire surface of the base region, and the contact regions of the base region are arranged in a large number of islands in the emitter region. A lattice-shaped first-layer emitter electrode that makes ohmic contact is provided on almost the entire surface of the emitter region, and an island-shaped first-layer base electrode that makes ohmic contact is provided in the contact region of the base region. And a second layer which is insulated from the base electrode of the first layer through an insulating film and which makes ohmic contact with the emitter electrode of the first layer and extends between the base electrode rows of the island-shaped first layer. A transistor comprising: an emitter electrode and a base electrode row of the island-shaped first layer, the base electrode of the second layer extending between the emitter electrodes of the second layer; The contact region of the base region is rectangular, and the second
A transistor characterized in that the longitudinal direction of the rectangle is provided in a direction orthogonal to the extending direction of the base electrode of the layer, and the long side and the short side are approximately 2: 1 to 3: 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59149919A JPH0611052B2 (en) | 1984-07-18 | 1984-07-18 | Transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59149919A JPH0611052B2 (en) | 1984-07-18 | 1984-07-18 | Transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6129173A JPS6129173A (en) | 1986-02-10 |
| JPH0611052B2 true JPH0611052B2 (en) | 1994-02-09 |
Family
ID=15485450
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59149919A Expired - Lifetime JPH0611052B2 (en) | 1984-07-18 | 1984-07-18 | Transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0611052B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62298172A (en) * | 1986-06-17 | 1987-12-25 | Sanyo Electric Co Ltd | Transistor |
| US5554880A (en) * | 1994-08-08 | 1996-09-10 | Semicoa Semiconductors | Uniform current density and high current gain bipolar transistor |
| US5932922A (en) * | 1994-08-08 | 1999-08-03 | Semicoa Semiconductors | Uniform current density and high current gain bipolar transistor |
| DE10004111A1 (en) * | 2000-01-31 | 2001-08-09 | Infineon Technologies Ag | Bipolar transistor |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5056177A (en) * | 1973-09-14 | 1975-05-16 | ||
| JPS6236305Y2 (en) * | 1979-04-26 | 1987-09-16 | ||
| JPS57181160A (en) * | 1981-04-30 | 1982-11-08 | Sanyo Electric Co Ltd | Transistor |
-
1984
- 1984-07-18 JP JP59149919A patent/JPH0611052B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6129173A (en) | 1986-02-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |