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JPH0611645B2 - Method for forming amorphous thin film - Google Patents
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JPH0611645B2 - Method for forming amorphous thin film - Google Patents

Method for forming amorphous thin film

Info

Publication number
JPH0611645B2
JPH0611645B2 JP61179149A JP17914986A JPH0611645B2 JP H0611645 B2 JPH0611645 B2 JP H0611645B2 JP 61179149 A JP61179149 A JP 61179149A JP 17914986 A JP17914986 A JP 17914986A JP H0611645 B2 JPH0611645 B2 JP H0611645B2
Authority
JP
Japan
Prior art keywords
substrate
layer
thin film
amorphous thin
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61179149A
Other languages
Japanese (ja)
Other versions
JPS6336522A (en
Inventor
圭弘 浜川
博明 岡本
章二 森田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Heavy Industries Ltd
Original Assignee
Mitsubishi Heavy Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Heavy Industries Ltd filed Critical Mitsubishi Heavy Industries Ltd
Priority to JP61179149A priority Critical patent/JPH0611645B2/en
Publication of JPS6336522A publication Critical patent/JPS6336522A/en
Publication of JPH0611645B2 publication Critical patent/JPH0611645B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

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  • Silicon Compounds (AREA)
  • Physical Or Chemical Processes And Apparatus (AREA)
  • Chemical Vapour Deposition (AREA)
  • Photovoltaic Devices (AREA)

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、非晶質薄膜の形成方法に関し、特に太陽電
池、薄膜半導体、電子感光体や光センサ等の各種電子デ
バイスに使用される非晶質薄膜の形成方法に係わる。
Description: TECHNICAL FIELD The present invention relates to a method for forming an amorphous thin film, and in particular, it is used for various electronic devices such as solar cells, thin film semiconductors, electrophotosensitive members, and optical sensors. The present invention relates to a method for forming a crystalline thin film.

[従来の技術] アモルファスシリコンに代表される非晶質薄膜の形成に
は、グロー放電プラズマを用いる、いわゆるプラズマC
VDによる方法が数多く提案されている。
[Prior Art] A glow discharge plasma is used to form an amorphous thin film typified by amorphous silicon, so-called plasma C
Many methods based on VD have been proposed.

例えば、アモルファス太陽電池は通常、第2図に示す構
造になっている。即ち、図中の1はガラス等からなる基
板であり、この基板1上には透明な伝導膜2が被覆され
ている。この伝導膜2は、酸化インジウムと酸化スズの
混合物からなるITOと呼ばれる層とSnOとで構成
され、スパッタリングや熱CVD等により堆積される。
前記伝導膜2上には、p層3、i層4、n層5の3つの
層からなるアモルファスシリコンが後述するプラズマC
VD装置等により夫々堆積されている。前記n層5上に
は、アルミニウムや銀等からなる薄膜電極6が真空蒸着
等により堆積されている。
For example, an amorphous solar cell usually has the structure shown in FIG. That is, reference numeral 1 in the drawing is a substrate made of glass or the like, and a transparent conductive film 2 is coated on the substrate 1. The conductive film 2 is composed of a layer called ITO made of a mixture of indium oxide and tin oxide and SnO 2, and is deposited by sputtering, thermal CVD or the like.
Amorphous silicon composed of three layers of a p-layer 3, an i-layer 4 and an n-layer 5 is formed on the conductive film 2 by plasma C described later.
Each is deposited by a VD device or the like. A thin film electrode 6 made of aluminum, silver or the like is deposited on the n layer 5 by vacuum vapor deposition or the like.

前記アモルファスシリコンを堆積するためのプラズマC
VD装置は、第3図に示す構造になっている。図中の1
1は、反応容器であり、この容器11には一対の電極1
2、13が対向して取付けられている。前記一方の電極
12は、高周波電源14に接続されている。また、図中
の15は前記反応容器11内を排気する真空ポンプ、1
6は前記基板1を載せる支持台、17は基板1を加熱す
るヒータ、18は層形成用の原料ガスの導入管である。
このようなCVD装置により前記p層3を形成するに
は、まず、支持台16上に基板1を載置し、真空ポンプ
15を作動して反応容器11内を排気しながらシランガ
ス(SiH)と不純物とてのジボラン(B)や
カーバイトとするためのメタン(CH)等を導入管1
8を通して反応容器11に導入した後、ヒータ17によ
り基板1を加熱しながら高周波電源14により電極1
2、13間に例えば13.5MHzの高周波電圧を印加
し、グロー放電プラズマを発生させる。この時、シラン
ガス等は電極12、13間のグロー放電空間で分解され
中性ラジカルが発生して基板1上のp層3が形成され
る。また、i層4を形成するにはシランガスのみを導入
し、n層5を形成するにはシランガスとフォスフィン
(PH)を導入する。なお、p層の形成にはガス濃度
によるが大体1分間程度必要とし、i層の形成には1時
間程度、n層の形成には3分間程度必要である。
Plasma C for depositing the amorphous silicon
The VD device has the structure shown in FIG. 1 in the figure
Reference numeral 1 denotes a reaction container, and a container 11 has a pair of electrodes 1
2 and 13 are attached to face each other. The one electrode 12 is connected to a high frequency power supply 14. Reference numeral 15 in the figure is a vacuum pump for exhausting the inside of the reaction vessel 11,
Reference numeral 6 is a support table on which the substrate 1 is placed, 17 is a heater for heating the substrate 1, and 18 is an introduction pipe of a raw material gas for forming a layer.
In order to form the p-layer 3 using such a CVD apparatus, first, the substrate 1 is placed on the support 16 and the vacuum pump 15 is operated to exhaust the inside of the reaction vessel 11 and silane gas (SiH 4 ). And diborane (B 2 H 6 ) as an impurity, methane (CH 4 ) for forming a carbide, etc.
After being introduced into the reaction vessel 11 through 8, the substrate 1 is heated by the heater 17 and the electrode 1 is fed by the high frequency power source 14.
A high-frequency voltage of, for example, 13.5 MHz is applied between 2 and 13 to generate glow discharge plasma. At this time, the silane gas or the like is decomposed in the glow discharge space between the electrodes 12 and 13 to generate neutral radicals, and the p-layer 3 on the substrate 1 is formed. Further, only silane gas is introduced to form the i layer 4, and silane gas and phosphine (PH 3 ) are introduced to form the n layer 5. It should be noted that it takes about 1 minute to form the p layer, depending on the gas concentration, about 1 hour to form the i layer, and about 3 minutes to form the n layer.

[発明が解決しようとする問題点] 上述した従来の装置では、グロー放電プラズマにより中
性ラジカルの他に、HやSiHの陽イオンが発生す
る。これらの陽イオンは、高周波電界によって加速さ
れ、膜表面を直撃する。その結果、膜内の欠陥準位が増
加する。
[Problems to be Solved by the Invention] In the conventional device described above, H + and SiH + cations are generated in addition to neutral radicals by glow discharge plasma. These cations are accelerated by the high frequency electric field and hit the film surface directly. As a result, the defect level in the film increases.

また、グロー放電により発生するプラズマは、過渡状態
を経た後に定常状態に移行する。即ち、放電開始直後に
SiHラジカル濃度に急激な立ち上がりが生じた後に定
常状態になるので、形成され膜にゆらぎが生じることに
なる。
Further, the plasma generated by glow discharge transits to a steady state after passing through a transient state. That is, since the SiH radical concentration rises sharply immediately after the start of discharge and then enters a steady state, fluctuations occur in the formed film.

このような現象は、非晶質薄膜をプラズマCVDにより
形成する時の大きな問題になるが、特にアモルファスシ
リコン太陽電池においては伝導膜とp層又はp層とi層
の界面付近の欠陥が素子特性の劣化につながる。
Such a phenomenon becomes a big problem when an amorphous thin film is formed by plasma CVD. In particular, in an amorphous silicon solar cell, a defect near the interface between the conductive film and the p layer or the p layer and the i layer is a device characteristic. Will lead to deterioration.

本発明は、上記従来の問題点を解決するためになされた
もので、膜形成時の陽イオンの衝撃を緩和すると共にS
iHラジカル等の濃度の急激な立上がりを防止し得る非
晶質薄膜の形成方法を提供しようとするものである。
The present invention has been made in order to solve the above-mentioned conventional problems, and alleviates the impact of cations at the time of film formation and S
An object of the present invention is to provide a method for forming an amorphous thin film capable of preventing a sharp rise in the concentration of iH radicals and the like.

[問題点を解決するための手段] 本発明は、グロー放電プラズマを用いて基板上へ非晶質
薄膜を形成する方法において、グロー放電開始時から少
なくとも30秒間前記基板を正の電荷に帯電させること
を特徴とする非晶質薄膜の形成方法である。
[Means for Solving the Problems] The present invention relates to a method of forming an amorphous thin film on a substrate by using glow discharge plasma, wherein the substrate is charged with a positive charge for at least 30 seconds after the start of glow discharge. And a method for forming an amorphous thin film.

[作用] 本発明では、非晶質薄膜の形成に際してグロー放電開始
時から少なくとも30秒間基板を正の電荷に帯電させる
ので、膜形成初期の段階において陽イオンが基板の電界
により押し戻される形となり、非晶質薄膜形成界面での
陽イオンの衝撃が緩和される。また、基板側を正に帯電
させることによりSiHラジカル濃度が下がり、代わっ
てSiH濃度が上昇するので、放電初期のSiHラジ
カル濃度の急激な立ち上がりが防止される。
[Operation] In the present invention, since the substrate is charged with a positive charge for at least 30 seconds from the start of glow discharge in forming the amorphous thin film, cations are pushed back by the electric field of the substrate in the initial stage of film formation, The impact of cations at the amorphous thin film forming interface is relaxed. In addition, since the SiH radical concentration is decreased by positively charging the substrate side and the SiH 2 concentration is increased instead, the abrupt rise of the SiH radical concentration at the initial stage of discharge is prevented.

[発明の実施例] 以下、本発明の実施例を第1図のプラズマCVD装置を
参照して説明する。なお、第1図において前述した第3
図と同様な部材は同符号を付して説明を省略する。
[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the plasma CVD apparatus shown in FIG. In addition, the above-mentioned third in FIG.
The same members as those shown in the figure are designated by the same reference numerals and the description thereof will be omitted.

図中の19は、支持台16上に載置される基板1に正の
電荷を帯電させるための直流電源であり、この電源19
のプラス側は金属製の支持台16に接続され、マイナス
側はガス入口付近の所定の箇所に接続されている。
Reference numeral 19 in the figure denotes a DC power supply for charging the substrate 1 mounted on the support 16 with positive charges.
The plus side is connected to the metal support 16 and the minus side is connected to a predetermined location near the gas inlet.

次に、基板上にi層を形成する方法を同第1図図示の装
置を参照して説明する。
Next, a method of forming the i layer on the substrate will be described with reference to the apparatus shown in FIG.

まず、基板1を支柱台16上に載置し、真空ポンプ15
を作動して反応容器11内を排気しながらシランガス
(SiH)を導入管18を通して反応容器11に導入
した後、ヒータ17により基板1を加熱しながら高周波
電源14により電極12、13間に例えば13.5MHz
の高周波電圧を印加し、グロー放電プラズマを発生させ
た。この放電開始と同時に直流電源19により基板1に
+150Vの電圧を加え、10秒後、又は20秒後と1
0秒間きざみで電源19からの電圧供給を停止して基板
上にi層を形成した。
First, the substrate 1 is placed on the support stand 16, and the vacuum pump 15
Silane gas (SiH 4 ) is introduced into the reaction vessel 11 through the introduction pipe 18 while activating the inside of the reaction vessel 11 while evacuating the inside of the reaction vessel 11, and then the substrate 1 is heated by the heater 17 while the substrate 1 is heated by the high frequency power source 14 between the electrodes 12 and 13. 13.5 MHz
Was applied to generate glow discharge plasma. Simultaneously with the start of this discharge, a voltage of +150 V is applied to the substrate 1 by the DC power supply 19 and after 10 seconds or 20 seconds, 1
The voltage supply from the power supply 19 was stopped at intervals of 0 second to form an i-layer on the substrate.

しかして、堆積されたi層における基板への正の電荷を
帯電する時間とダメージ発生等の関係を調べたところ、
放電開始時から30秒間より早い時期に基板への正の帯
電を停止した場合には陽イオンの直撃によるi層のダメ
ージ及びSiHラジカル濃度の急激な立ち上がりの影響
を防止することができなかった。これに対し、放電開始
時から30秒間以上の間基板に正の電荷を帯電させた場
合には、陽イオンの直撃によるi層のダメージ及びSi
Hラジカル濃度の急激な立ち上がりの影響を防止するこ
とができた。但し、基板への正の電荷の帯電が放電開始
時から3分間を越えると、性能の向上はない。このた
め、生産性の問題又は不純物の熱拡散による素子劣化を
考慮すると、放電開始時から3分間が経過する前に基板
への正の帯電を停止し、SiHラジカル濃度を上昇させ
て膜形成スピードを早めた方がよいと思われる。
Then, when the relationship between the time for charging positive charges to the substrate in the deposited i layer and the occurrence of damage, etc. was investigated,
When the positive charging of the substrate was stopped earlier than 30 seconds after the start of discharge, it was not possible to prevent the damage of the i layer and the rapid rise of the SiH radical concentration due to the direct impact of cations. On the other hand, when the substrate is charged with a positive charge for 30 seconds or more after the start of discharge, damage to the i layer due to direct impact of cations and Si
It was possible to prevent the effect of a sharp rise in the H radical concentration. However, if the positive charge on the substrate exceeds 3 minutes after the start of discharge, there is no improvement in performance. Therefore, considering the problem of productivity or element deterioration due to thermal diffusion of impurities, positive charging of the substrate is stopped before 3 minutes have elapsed from the start of discharge, the SiH radical concentration is increased, and the film formation speed is increased. I think it is better to speed up.

また、放電開始時から30秒間以上の間基板に正の電荷
を帯電させる条件にてガラス基板の伝導膜上にp層、i
層、n層を形成することにより得たアモルファスシリコ
ン太陽電池では、従来法で形成した同太陽電池に比べて
短絡電流及び曲線因子を増大でき、光電変換効率が3乃
至4%改善された。
Further, under the condition that the substrate is positively charged for 30 seconds or more after the start of discharge, the p layer, i
In the amorphous silicon solar cell obtained by forming the layer and the n-layer, the short-circuit current and the fill factor can be increased, and the photoelectric conversion efficiency is improved by 3 to 4%, as compared with the solar cell formed by the conventional method.

[発明の効果] 以上詳述した如く、本発明によれば膜形成時の陽イオン
の衝撃を緩和すると共にSiHラジカル等の濃度の急激
な立上がりを防止でき、ひいては太陽電池、薄膜半導
体、電子写真感光体や光センサ等の各種の電子デバイス
に好適な非晶質薄膜の形成方法を提供できる。
[Effects of the Invention] As described in detail above, according to the present invention, it is possible to mitigate the impact of cations during film formation and prevent a sharp rise in the concentration of SiH radicals, etc., and thus a solar cell, a thin film semiconductor, and an electrophotography. A method for forming an amorphous thin film suitable for various electronic devices such as a photoconductor and an optical sensor can be provided.

【図面の簡単な説明】 第1図は本発明の実施例に使用されるプラズマCVD装
置の一形態を示す概略図、第2図は一般的なアモルファ
スシリコン太陽電池を示す概略図、第3図は従来のプラ
ズマCVD装置を示す概略図である。 1……基板、3……p層、4……i層、5……n層、1
1……反応容器、12、13……電極、14……高周波
電源、16……支持台、19……直流電源。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing one form of a plasma CVD apparatus used in an embodiment of the present invention, FIG. 2 is a schematic view showing a general amorphous silicon solar cell, and FIG. FIG. 3 is a schematic diagram showing a conventional plasma CVD apparatus. 1 ... Substrate, 3 ... p layer, 4 ... i layer, 5 ... n layer, 1
1 ... Reaction vessel, 12, 13 ... Electrode, 14 ... High frequency power source, 16 ... Supporting base, 19 ... DC power source.

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭62−81021(JP,A) 特開 昭59−39713(JP,A) ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP 62-81021 (JP, A) JP 59-39713 (JP, A)

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】グロー放電プラズマを用いて基板上へ非晶
質薄膜を形成する方法において、グロー放電開始時から
30秒間以上、3分間以内の間、前記基板を正の電荷に
帯電させることを特徴とする非晶質薄膜の形成方法。
1. A method of forming an amorphous thin film on a substrate using glow discharge plasma, comprising charging the substrate to a positive charge for 30 seconds or more and 3 minutes or less from the start of glow discharge. A method for forming a characteristic amorphous thin film.
JP61179149A 1986-07-30 1986-07-30 Method for forming amorphous thin film Expired - Lifetime JPH0611645B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61179149A JPH0611645B2 (en) 1986-07-30 1986-07-30 Method for forming amorphous thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61179149A JPH0611645B2 (en) 1986-07-30 1986-07-30 Method for forming amorphous thin film

Publications (2)

Publication Number Publication Date
JPS6336522A JPS6336522A (en) 1988-02-17
JPH0611645B2 true JPH0611645B2 (en) 1994-02-16

Family

ID=16060820

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61179149A Expired - Lifetime JPH0611645B2 (en) 1986-07-30 1986-07-30 Method for forming amorphous thin film

Country Status (1)

Country Link
JP (1) JPH0611645B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63312852A (en) * 1987-06-16 1988-12-21 Brother Ind Ltd Piezoelectric element drive type impact print head

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5939713A (en) * 1982-08-29 1984-03-05 Agency Of Ind Science & Technol Thin silicon film containing crystallite and its manufacture
JPS6281021A (en) * 1985-10-04 1987-04-14 Fuji Electric Co Ltd Apparatus for manufacturing thin film semiconductor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63312852A (en) * 1987-06-16 1988-12-21 Brother Ind Ltd Piezoelectric element drive type impact print head

Also Published As

Publication number Publication date
JPS6336522A (en) 1988-02-17

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