JPH061190B2 - Pulse signal photocurrent extraction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to a semiconductor position detecting element (Position Sensitive Decoder).
The present invention relates to a pulse signal photocurrent extraction circuit used in a distance detection circuit using a tector.

(Prior art) Distance detection is performed by irradiating an object to be measured with infrared light in the form of pulsed light from a light source, detecting reflected light using a semiconductor position detection element PSD, and measuring the distance to the object to be measured by the principle of triangulation. The device is known.

FIG. 2 is a schematic diagram showing an optical system of a distance detecting device using a PSD.

The pulsed light emitted from the LED for projecting light is projected by the projecting lens L.
The reflected light is projected onto the object to be measured Ob in front by ₁ , and the reflected light enters the PSD through the light receiving lens L ₂ .

The PSD converts the background light or the extraneous light and the pulsed light into a current including the level of the background light or the extraneous light and the incident position information of the pulsed light, and outputs the current.

Therefore, it is necessary to extract only the necessary pulse signal current superimposed on the current caused by the background light or the extraneous light (hereinafter, extraneous photocurrent) from the PSD and execute the distance calculation.

FIG. 3 is a block diagram of a signal processing circuit of the distance detecting device.

The output terminals of the PSD are connected to pulse signal sampling circuits I and II having the same structure.

The pulse photocurrents are logarithmically compressed and extracted by the pulse signal extraction circuits I and II, and the distance information is extracted by the differential circuit.

FIG. 4 is a circuit diagram showing an embodiment of a conventional pulse signal photocurrent extracting circuit.

A PSD and a constant current source are connected to the collector of the NPN transistor 11, and the emitter is grounded.

The collector of the transistor 11 is the NPN transistor 12
Connected to the base of.

A steady current flows into the NPN transistor 11 and a signal current flows into the NPN transistor 12, and this current enters the mirror circuit composed of the PNP transistors 13, 14, 15, 16, 23 connected to the collector of the NPN transistor 12. The output is logarithmically compressed by the two-stage diodes 17 and 18. This output is the voltage follower 19
And is compared with Vref in the comparator 20 through the capacitor 33, and the output of the comparator 20 is the transistor 21.
Through this, the NPN transistor 11 is controlled to draw a steady current.

The memory capacitor 32 stores the base voltage and extracts the signal current.

(Problems to be Solved by the Invention) In a steady state, when a current having a high frequency component other than a signal current such as a fluorescent lamp light is input, consider a state in which the external light current suddenly decreases.

At this time, the base voltage of the transistor 11 is the capacitor 3
Since it cannot change suddenly due to the large capacity of 2, the current collector current is to be maintained. for that reason,
The base current of the transistor 12 is pulled out by the transistor 11, and the mirror circuits 13 and 1
No current flows through 4, 15, 16, and 23.

Therefore, the outputs of the two-stage diodes 17 and 18 are lowered, and the voltage follower 19 and the comparator 20 try to keep them at a constant value. However, since the comparator 20 has no operating current, the capacitor 32 is connected through the transistor 21. Since the electric potential of the diode cannot be controlled, the output of the two-stage diode will remain lowered.

An object of the present invention is to provide a pulse signal light current extraction circuit that can quickly eliminate the above-mentioned abnormal state.

(Means for Solving the Problems) In order to achieve the above-mentioned object, a pulse signal photocurrent extraction circuit according to the present invention is a first signal amplification circuit in which a base is connected to a PSD and a current source and an emitter is grounded. NPN
A transistor, a second NPN transistor for extracting a DC component whose collector is connected to the base of the first NPN transistor and whose emitter is grounded via a resistor, and to the collector of the first NPN transistor Formed by a plurality of PNP transistors, one output of the mirror circuit and the second N
A memory capacitor connected to the base of a PN transistor, a third NPN transistor connected to the base of the second NPN transistor for absorbing a carrier current, and a two-stage diode connected to the output end of the mirror circuit. And a current source, a voltage follower having the output of the diode as an input, a sample and hold capacitor connected to the output of the voltage follower, and a bias current supplied from the mirror circuit to supply a voltage and a reference voltage to the capacitor. In comparison, the third NPN
The signal current is extracted when a high-frequency signal component is superposed by a direct current or low-frequency current, which consists of a comparator circuit that controls the diode output of two stages to a value equal to the reference voltage by controlling the base voltage of the transistor. In the signal pulsed photocurrent extraction circuit, the second NP
The collector of a fourth NPN transistor whose emitter is grounded is connected to the base of the N-transistor, and the voltage of the diode in the second stage and the reference voltage formed by the diode in the first stage are compared by another comparator, When the voltage of the two-stage diode becomes low, the fourth NPN transistor is turned on to discharge the electric charge of the memory capacitor.

(Example) The present invention will be described in more detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a pulsed photocurrent extraction circuit according to the present invention.

The output terminal of the PSD and the constant current source are connected to the collector of the NPN transistor 11. The emitter of this transistor is grounded via a resistor 39.

The collector of the NPN transistor 11 is connected to the base of the NPN transistor, and the collector of the NPN transistor 12 is connected to the collector of the PNP transistor 14.

The PNP transistors 13, 14, 15 and 16 are the PN
A mirror circuit is formed with the P-transistor 14.

PNP transistor 15 and NPN in this mirror circuit
The collector of the transistor 21 is connected.

A memory capacitor 32 is connected to the collector of the base of the NPN transistor 11.

On the other hand, the collector of the PNP transistor 16 is connected to a logarithmic compression circuit including diodes 17 and 18, and a current source 22.

The output of the logarithmic compression circuit including the diodes 17 and 18 is connected to the sample hold capacitor 33 via the voltage follower 19.

The output terminal of the sample hold capacitor 33 is the comparator 2
0 connected to Vref voltage and its output is NP
It is connected to the base of the N-transistor 21.

The transistors 27, 28, 29, 30, 31 form a differential amplifier.

The outputs of the logarithmic compression diodes 17 and 18 are connected to the base of the PNP transistor 29. Also PNP
To the base of the transistor 28, a one-stage diode level (reference voltage) corresponding to the bias current generated by the resistor 38 is given from the diode 26.

In such a circuit, the operation when the external photocurrent decreases with a high frequency component is as follows.

That is, when the outputs of the two-stage diodes 17 and 18 decrease in the same manner as described above, the base voltage level of the PNP transistor 29 shifts from "H" to "L".

When the level becomes "L", the level becomes lower than the level of the diode 26, so that a current flows through the NPN transistor 24, and the mirror circuit (transistors 23, 24) draws the level of the memory capacitor through the NPN transistor 23.

If the emitter area ratio of the transistor 23 and the transistor 24 is 1: 3 or 1: 4, the extraction time is shortened by that amount, and as a result, the noise level is lowered.

(Effects of the Invention) As described in detail above, the circuit according to the present invention is configured to assist recovery when an abnormal pulse having a timing different from the signal current is input or when output is reduced due to electrical noise. Therefore, it is possible to completely prevent the inconvenience caused by the incidence of fluorescent lamp noise similar to the signal light pulse.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a signal pulse photocurrent extracting circuit according to the present invention. FIG. 2 is a schematic diagram showing an optical system of a distance detecting device using a PSD. FIG. 3 is a block diagram of a signal processing circuit of the distance detecting device. FIG. 4 is a circuit diagram showing an embodiment of a conventional pulse signal photocurrent extracting circuit. PSD ... Semiconductor position detecting element 11 ... Second NPN transistor 12 ... First NPN transistor 13-16 ... PNP transistor (mirror circuit) 17, 18 ... Logarithmic compression diode 19 ... Voltage follower 20 ... Comparator 21 ... Third NPN transistor 22, 40 ... Constant current source 23 ... Fourth NPN transistor 27-31 ... PNP transistor (comparator) 32 ... Memory capacitor 33 ... Sample-hold capacitor 38, 39 ... Resistor

Front Page Continuation (72) Takamichi Takehana Inventor Taka 21 21-17 Takashima, Suwa City, Nagano Chinon Co., Ltd. (56) Reference JP 59-142412 (JP, A) JP 59-151013 ( JP, A) JP 62-14076 (JP, A) JP 58-95210 (JP, A) JP 62-145111 (JP, A)

Claims (1)

[Claims] 1. A first NPN transistor for signal amplification whose base is connected to a PSD and a current source and whose emitter is grounded; and a collector which is connected to the base of said first NPN transistor and whose emitter is a resistor. A second NPN transistor for extracting a direct current component that is grounded via a mirror circuit formed by a plurality of PNP transistors connected to the collector of the first NPN transistor; and one output of the mirror circuit. The second NPN
A memory capacitor connected to the base of the transistor, a third NPN transistor connected to the base of the second NPN transistor to absorb a carrier current, a two-stage diode connected to the output end of the mirror circuit, and A current source, a voltage follower receiving the output of the diode as an input, a sample and hold capacitor connected to the output of the voltage follower, and a bias current supplied from the mirror circuit to compare the voltage of the capacitor with a reference voltage. Then, the third NPN
The signal current is extracted when a high-frequency signal component is superposed by a direct current or low-frequency current, which consists of a comparator circuit that controls the diode output of two stages to a value equal to the reference voltage by controlling the base voltage of the transistor. In the signal pulsed photocurrent extraction circuit, the second NP
The collector of a fourth NPN transistor whose emitter is grounded is connected to the base of the N-transistor, and the voltage of the diode in the second stage and the reference voltage formed by the diode in the first stage are compared by another comparator, A pulse signal photocurrent extracting circuit, characterized in that, when the voltage of the two-stage diode becomes low, the fourth NPN transistor is made conductive to discharge the electric charge of the memory capacitor.