JPH0612615B2 - Multi-dimensional access memory - Google Patents

Description

DETAILED DESCRIPTION [Overview] A high-capacity semiconductor memory is divided into blocks, the outputs of multi-dimensional selection in each block are latched, and multi-dimensional selection is performed outside the block to achieve high-dimensional. Make it easy to access.

[Industrial application field]

The present invention relates to a multi-dimensional access memory, and is intended to enable higher-dimensional access by performing multi-dimensional access in multiple stages.

[Conventional technology]

In image data processing and the like, it is desired to read out desired plural bits simultaneously from the memory in view of the nature of the processing and speed-up, and for this purpose, the present inventor has developed a multidimensional access memory as shown in FIG. did.

In the figure, reference numeral 10 denotes a cell array of a semiconductor memory, which has a large number of word lines WL and bit lines BL, and a memory cell MC (not shown) arranged at each intersection thereof. In this example, the memory is a DRAM and is a folded type, so each bit line pair BL, ▲ ▼ is a sense amplifier group 1
2 extend parallel to each other on one side. 256 word lines,
The number of bit line pairs is also 256, so that there are 65536 memory cell lines and 256 sense amplifiers SA.
A row decoder 14 receives 8-bit addresses A _{0 to} A ₇ and selects one of 256 word lines. Word line 1
When one is selected, the storage data of 256 memory cells belonging to the word line appears on each bit line. The sense amplifier group 12 amplifies this and outputs it to the data bus 20 through the multidimensional selection circuit 16.

In this example, the number of data buses 20 is 16, and the selection circuit 16
Is a designated dimension, selects 16 outputs (bits) from the outputs of 256 sense amplifiers, and outputs 16 data buses 2
Output to 0. x, y, and s are dimension control signals, where x indicates an X direction selection, y indicates a Y direction selection, and s indicates a surface selection. That is, this FIG. 16 assumes the logical plane of FIG. 17 as word line data, and 16 × 16 =
256 bits are written to the memory cell on one word line. In this case, memory cells on one word line are numbered from the beginning to be 0, 1, 2, ...
To 15 have 16 bits 0 to 15 in the X direction of Y = 0, and 16 to 31 have 16 bits 0 to 15 in the X direction of Y = 1.
…… It is supposed to be written. B _{0 to} B ₃ are addresses within the 16-bit segment (16 bits × 16 bits in FIG. 5). As is clear from FIG. 17, X direction 1
There are 16 6-bits, 16 16-bits in the Y direction, and 4 × 4 = 16 S-planes with 4 × 4 = 16 bits.
4 bits (B ₀
~ B ₃ ) It is sufficient. The x, y, s dimensional control signals are input to the predecoder 18, and the decoded output is added to the multidimensional selecting circuit 16 to select 16 bits in the designated dimension. 22 is a latch, and 16-bit data of the data bus 20 is output to the outside through the latch 22.

A specific example of the multidimensional selection circuit 16 is shown in FIG. WLi
Is the i-th word line, BL72, ▲ ▼ is the 72nd bit line pair, SA ₇₂ is its sense amplifier, BL73, ▲
▼ is the 73rd bit line pair, and SA ₇₃ is its sense amplifier. 20 is a data bus, which has 2 bytes. 1
Reference numeral 6 denotes the multi-dimensional selection circuit which outputs the output of each sense amplifier to the designated dimension (x, y, s) and segment address (B ₀
.About.B ₃ ) to selectively lead to the data bus 20. The selection circuit 16 is composed of decoders (x, y, s decoders) of respective dimensions arranged for the respective sense amplifiers, each commonly receives the segment addresses B ₀ to B ₃ , and individually the dimension control signal x. , Y, s is activated when the corresponding control signal is received.

To explain the multi-dimensional selection procedure in FIG. 18, one word line has 256 bits, and if these are arranged as described above, the 72nd sense amplifier SA ₇₂ has a fourth group (Y = 4) in the X direction. ) And the 73rd sense amplifier SA ₇₃ outputs the 9th bit. Therefore, when B _{0 to} B ₃ indicate the fourth group (fourth segment), the x decoder X
72 outputs the output of SA ₇₂ to the data bus DB8, ▲
To ▼, and the output of SA ₇₃ is sent to DB9,
In the same manner as in (4), the 16th bit in the X direction of the fourth group can be simultaneously output to the data bus 20. The output bits of SA ₇₂ are the eighth group (X
= 8), that of SA ₇₃ is the fourth bit of the ninth group, so when B _{0 to} B ₃ indicate the eighth group, the y decoder Y72 guides the output of SA ₇₂ to DB4 and DB4 , When B _{0 to} B ₃ represent the ninth group, y decoder Y7
If the output of SA ₇₃ is also led to DB4, (3) according to 3, and the same is true for the other, 16 bits in the Y direction of each group can be sequentially output to the data bus (simultaneously within the group). The same applies to the S surface.

An example of the x decoder is shown in FIG. Q _{1 to} Q ₆ , Q
₁₆ p-channel _{transistors, Q 7} ~Q _12, Q ₁₅
Is an n-channel transistor. When x is H (high), Q _{16 is} off, Q _{15 is} on, and node N1 is L (low), so that Q _{12 is} off, Q _{6 is} on, and Q ₁ ~
In a state where the output of the decoder portion of Q _{4, Q} 7 _{to Q 10} is removed, _(if B 3 .about.B ₀ fourth group selected in 0100) if the address _B 0 _{~ 3} selects this decoder node N3 is L, therefore _{Q 5 on, Q 11} turns off, the node N2 is H, the transfer gate _{Q 13, Q 14} is turned on, the data bus DB8 output of _{SA 72,} ▲
Go to ▼.

Another example of the multidimensional selection circuit 16 is shown in FIG. The predecoders 18 are three for x, y, s 18x, 18y, 18
s, each of which has a common segment address B ₀ to
₃ and individually receives one of the dimension control signals x, y, s to become active, and supplies the decoded output to the multidimensional selection circuit 16. 30x, 30y and 30s are 16 exclusive select lines supplied with this decode output, 7
Reference numerals 2x, 72y and 72s are transfer gates connected to one of the selection lines and sending the output of the sense amplifier turned on / off to the data bus 20. Since there is one transfer gate for each sense amplifier for each dimension, there are 256 × 3 transfer gates in this example. x, y, s predecoder 1
8x, 18y, 18s are activated by only one of the signals x, y, s, and each predecoder brings 1 out of 16 outputs to H, so only 1 out of 16 of these 16 × 3 = 48 Select line turns on 16 pairs of transfer gates and guides the output of the sense amplifier to the data bus 20.

FIG. 21 shows the correspondence between each 16 bits in the segment and the sense amplifier. The data allocation to each memory cell on the word line is as described above. No. 0 when accessing in the X direction
Group (B = 0, which is 16 bits in X direction at Y = 0), first group (B = 1, which is 1 in X direction at Y = 1)
16 bits each of 6 bits), ... Sense amplifier SA0
~ SA15, SA16 ~ SA31, ...
It is selected by the selection circuit and sent to the data buses DB0 to DBF.

When accessing in the Y direction, the 0th group (B = 0, which is X = 0
16 bits in the Y direction), the first group (B = 1, which is 16 bits in the Y direction at X = 1), ..., 16 bits for each of the sense amplifiers SA0, SA16 ,.
Output from SA1, SA17, ... SA241, .. These are selected by the selection circuit and are output to the data bus DB.
0 to DBF.

For S-plane access, the 0th group (B = 0, which is 4 × 4 bits with X = Y = 0 in the upper left corner), the first group (B = 1, which has X = 4, Y = 0 in the upper left corner). 4 x 4 bits), ..., each 1
6 bits are sense amplifiers SA0-SA3 and SA16-S
A19, SA32 to SA35, SA48 to SA51 (this group is the 0th group, the next is the 1st group), SA4 to SA7 ...
Is output from the data bus D and is selected by the selection circuit.
It is sent to B0 to DBF.

As shown in FIG. 21 (d), the sense amplifiers SA0 to SA255 have data bits 0, 1, 2, ... 1 on the word line.
5, 16, ... 31, 32 ...

[Problems to be solved by the invention]

In these multi-dimensional access memories, when the dimension is increased and it is desired to expand the segment logical array, the area of the decoders 16 and 18 is remarkably increased. This not only lowers the degree of integration, but also lowers the electrical characteristics (current, access time, noise resistance), and also causes an overall cost increase.

The present invention can improve such points, suppress the increase in area with respect to higher dimensionality of multidimensional access and expansion of segment space, and realize increase in layout flexibility and cost reduction without impairing electrical characteristics. It is intended to provide memory.

[Means for solving problems]

The multi-dimensional access memory of the present invention comprises a plurality of cell arrays (10a, 10a) to which word addresses are commonly applied.
b, ...), the data bit read from each cell array by word line selection based on the common word address applied to each cell array, and the first small area of a predetermined dimension in the logical space. A plurality of first cell provided corresponding to each cell array, each of which receives as input the one dimension designation signal (x, y, s) and fetches a plurality of bits corresponding to the designated first small area from the input data bits. Multidimensional selection circuit (16a, 16b ...
...) and a plurality of bits respectively output from the plurality of first multidimensional selection circuits and a second of a predetermined dimension within a first small region of a predetermined dimension designated on the logical space. A second dimension designating signal (x ₂ , y ₂ , s ₂ ) complementing the first dimension designating signal for designating a small area is input, and a _second dimension designated from the input plurality of bits is input. Takes out multiple bits corresponding to a small area, data bus (20A)
The second multi-dimensional selection circuit (16A, 16B, ...
...) is provided.

[Action]

In this memory, it is possible to realize higher dimensionality of multidimensional access, expansion of segment space, complexity of structure and increase of area, secure flexibility of electrical characteristics and layout, and realize at low cost, which is very effective. Is.

〔Example〕

An embodiment of the present invention is shown in FIG. Cell array 10a, 1
There are 16 0b, ..., Each of which has a capacity of 256 × 256 bits (although the number of bits, the number of cell arrays, etc. can be appropriately increased or decreased). After all, Folded bit line DRAM
And the sense amplifier groups 12a, 12b, ...
Are arranged on one side of the cell array, and the multidimensional selection circuit 1
6a, 16b, ... Are arranged. It is assumed that the 16-bit × 16-bit (1 segment) data is stored on one word line of each cell array in the above-described manner (16 bits in the X direction are sequentially arranged), and the same word address is supplied to each cell array. It is assumed that the corresponding word lines are selected all at once. Therefore, word addresses A _{0 to} A ₇ , segment addresses B _{0 to} B ₃ , and dimension control signals x, y, s
(Any one of them) is read out, the corresponding 16 bits are taken out to the data bus 20 (not shown in FIG. 1), and the second multidimensional selection circuit 16 also serving as the latch 22.
Incorporated into A, 16B, .... Since there are also 16 second multi-dimensional selection circuits 16A, 16B, ..., The number of bits of data taken in by the circuits is 16 × 16 = 256,
It is equal to the number of data bits read by selecting one word line. Therefore, 16 bits can be multi-dimensionally selected for these circuits 16A, 16B, ... In the same manner as the first multi-dimensional selection circuits 16a, 16b ,. It is taken out through the data bus 20A and the output buffer 22A.

Since multidimensional (x, y, s) is selected on the 16 × 16-bit logical plane in the first multidimensional selection, the number of 16 bits × 16 on the second multidimensional selection circuits 16A and 16B is further increased. When the dimension is selected, it means that the high-dimensional (three-dimensional) selection is performed on the 16 × 16 × 16-bit logical space, which is effective for the processing of stereoscopic data.

The relationship between the latch of the second multidimensional selection circuit 16A and the circuit is shown in FIG. 2, a specific example of the selection circuit itself is shown in FIG. 3, and a specific example of the latch is shown in FIG. As shown, the configuration of the selection circuit is the same as that of the first multidimensional selection circuit.

With this two-stage multi-dimensional selection, the 16 × 16 bit logical plane is set to 1
The six types of access shown in the following table are possible in a logical 16 × 16 × 16 bit logical space in which six sheets are arranged.

In this table, ~ is the X vector of Fig. 4, that is,
Y vector, XY4 ² scare, Z vector, YZ
4 ² Scare shows XZ4 ² Scare. Where XY4 ²
Scare refers to the S surface which is a small area of 4 dots × 4 dots on the XY two-dimensional plane. YZ4 ² Scare is the same for ^{4 2} Scare the X. If the first number of selected dimensions is 3 and the second number of selected dimensions is 3, it is 3 in two-stage multidimensional selection.
There can be × 3 = 9 kinds of accesses, but as shown in Table 1, xy ₂ and yy ₂ and sy ₂ are both Z vectors, and xy ₂ and sy ₂ are both XY 4 ² scares, so if these are excluded, There are 6 types. In this way, the reduction in the effective number of selection targets in multidimensional selection due to duplication is called degeneracy.

When the first multidimensional selection is performed by x, each data of 16A, 16B ... constitutes the XZ plane as a whole (that in the figure is an example),
When the first multidimensional selection is performed in y, a YZ plane (which is an example in the figure) is formed, and when performed in s, a prism having a 4 × 4 cross section in the XY plane and extending in the Z direction is formed. These are called intermediate segments. An X vector can be obtained by selecting x on the intermediate segment XZ plane, and a Z vector can be obtained by selecting y. Others are the same.

In this way, the segment (16x16 bit XY plane) is Z
Within the logical space of 16 × 16 × 16 parent segments in which 16 sheets are lined up in the direction, 6-dimensional access can be made meaningful as shown in FIGS. The middle segment is not fixed in this space. Each segment is composed of 8 bits of inner addresses B _{0 to} B ₃ and B _{4 to} B ₇ . The first and second multidimensional selection circuits are not independent in order to have regularity with each other. For example, it is possible to give a degree of freedom to the physical arrangement of the sense amplifiers by the first multidimensional selection circuits 16a, 16b, ..., At that time, the second multidimensional selection circuit is constrained to the position of each data latch. To be done. The reverse is also true.

Considering all combinations of dimensions of the first and second multi-dimensional selection circuits, nine types shown in Table 1 occur. Of course, if the arrangement of the second multi-dimensional selection circuit is changed with another meaning, a result other than the first result will occur, but in any case, degeneracy as shown in Table 1 occurs. The degeneracy is always 3, and only 9-3 = 6 types of access dimensions can be obtained.

In Table 1, for example, the Z vector is (x, y ₂ ), (y, y
₂ ), (s, y ₂ ). These are the same Z vector, but the addresses in the parent segment differ depending on B _{0 to} B ₇ . Therefore, for the purpose of obtaining multidimensional access, degenerate ones are regarded as redundant, and x, y, s, x ₂ , y ₂ , s ₂ are previously set to avoid confusion in addressing.
It is advisable to perform pre-decoding in the chip so that all combinations of the three-dimensional signals are generated. The following table shows an example, and one degenerated one is discarded, and the combination of the dimensional signals is not considered.

V ₁ , V ₂ , and V _{3 in} Table 2 are dimension designating bits given from outside the chip. There are various methods of converting Table 2 into a circuit, but one of them is a ROM having 3 inputs and 6 outputs. Table 2
In x, _y, s, if 1 to columns x _2, y _{2, s 2} is not set 1 Tsumo, it is possible to omit the selection circuit for that dimension. For example, if is unnecessary, s ₂ is unnecessary and the second multidimensional selection circuit becomes simple. If is unnecessary, s becomes unnecessary and the first multidimensional selection circuit becomes simple.

That is, the first and second multi-dimensional selection circuits need not have the same scale, but may have different scales depending on the required number of dimensions or the size of the desired parent segment. In this case, the small segment (16x16 bit XY plane), the middle segment is the same 16x16, and the parent segment is 16x16x16.
However, this is for convenience of description, and the number of bits can be appropriately increased or decreased.

The circuit of FIG. 5 mainly shows DL0 of FIG. 2, but other DL1, ... Have the same structure. In FIG. 5, Q _{1 to} Q ₁₉
Is a MOS transistor, and those marked with a circle are p-channel type, and those without a mark are n-channel type. BSR is a reset signal for data bus DB0, ▲ ▼, SBE
Is a data latch enable signal, and R / W is a read / write signal.

When BSR becomes H (high), Q _{1 to} Q ₃ are turned on,
DB0 and DB0 are short-circuited and reset. When SBE is H NA1 power potential NA2 becomes the ground _potential, the latch circuit of the Q 4 to Q ₇ is activated. For example, when DB0 is H and ▲ ▼ is L, Q ₄ , Q _{7 are} on, Q ₅ , Q _{6 are} off, and the H and L are maintained. When the R / W is a _Q 12 _{to Q 15} on by H (read), DB0 through these switches, ▲ ▼ of H, L is BS0, it sent ▲ as ▼ to a second multi-dimensional selection circuit. At this time, Q ₈ and Q ₉ are off, and Q ₈
The circuit of ~ Q ₁₁ has no effect. The chain line frame circuit is BS
R, SBE, R / W to BSR, NA1, NA2, W
E, RE (= ▲ ▼) is made and is shared by each latch or a plurality of latches.

Since the same multidimensional selection is simultaneously performed in the adjacent blocks (10a and 10b, etc.) in FIG. 1, both multidimensional selection circuits can be shared. An example is shown in FIG. DBl is a data bus for the left block (for example, 10b), and DBr is a data bus for the right block (for example, 10a). x, y, s
The predecoder is a multidimensional selection circuit, and these and their exclusive selection lines CL are shared by both.

The data bus and the like can be operated in a time-division manner to reduce the number of elements and simplify the configuration. FIG. 7 shows an example thereof. In this example, one cell array is 512 WL × 256 B
L and twice the size of FIG. 1, halving the number,
The bus 20A and the like are operated in a time division manner. That is, as shown in FIG. 8, when the ▲ ▼ (row address strobe bar) signal is set to L and reading is started, WLi is selected and BL, ▲.
The cell data is output to ▼, SBE is set to H, and the data is latched, for example, by 16A. Then WL
_{i + 1} is selected, cell data is output to BL and ▲ ▼, SBE 'is set to H and the data is latched.
Let B take it in. The same applies to each cell array, so WL
16 times for latches 16A to 16P by selecting twice
6-bit data is captured. The rest is the same as the above example. Thus (in the RAS cycle, the same operation as that shown in FIG. 1 can be performed (however, the required time is a little long).

The data bus latch of each cell array can also be halved by time division operation. FIG. 9 shows an example thereof, and FIG. 10 shows a concrete example of the 2-to-1 selector SLT. Selector S
LT is a switch for switching and connecting two adjacent pairs of data buses to one latch DL00 or the like. A and B are control signals for controlling the selector SLT and controlling the data acquisition to the latches a ₀ , a ₁ , ... B ₀ , b ₁ , ... Of the second multidimensional selecting circuit. FIG. 11 shows operation waveforms.

Sharing and time sharing can be implemented in combination. In FIG. 12, the first multi-dimensional selection circuit is shared as shown in FIG. 6, and the data bus of the cell array is set to 8 bits for time division operation.

FIG. 13 shows an example of a shared data bus and a shared multidimensional selection circuit. The time division control signals A and B determine which of the left and right blocks is output to the shared data bus. FIG. 14 shows operation waveforms in this case. This is different from FIG. 11 in that all the data buses operate twice in a time division manner.

FIG. 15 shows that the number of bits of the second data bus 20A is halved.
16-bit I / O buffer 2
2A shows an example of a circuit that causes data to be latched in 2A via a 1-to-2 selector SLT and 8-bit latches 22A1 and 22A2.

〔The invention's effect〕

As described above, according to the present invention, higher dimensionality of multidimensional access, expansion of segment space, suppression of complication of structure and increase of area, and freedom of electrical characteristics and layout are secured,
It can be realized at low cost and is very effective.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a basic embodiment of the present invention, FIG. 2 is a detailed explanatory diagram of a part of FIG. 1, FIG. 3 is a circuit diagram of a part of FIG. 2, and FIG. FIG. 5 is an explanatory diagram of memory data, FIG. 5 is a circuit diagram of a data bus latch, FIG. 6 is a circuit diagram showing a common point of the first multidimensional selection circuit, and FIG. 7 is an explanatory diagram of a time division operation of a cell array. 8 is an operation waveform diagram of FIG. 7, FIG. 9 is an explanatory diagram of a time division operation data latch, FIG. 10 is a specific example circuit diagram of FIG. 9, and FIG. 11 is an operation waveform of FIG. FIGS. 12, 13, and 15 are block diagrams and circuit diagrams showing examples of combinations of sharing and time division, FIG. 14 is an operation waveform diagram of FIG. 13, and FIG. 16 is description of a proposed memory. FIG. 17, FIG. 17 is an explanatory diagram of multidimensional data, FIGS. 18 and 20 are diagrams showing details of the multidimensional selection circuit, and FIG. 19 is a part of FIG. FIG. 21 and FIG. 21 are explanatory diagrams showing correspondence between each segment and a sense amplifier or the like. In FIG. 1, 10a, 10b, ... Are cell arrays, 12a,
12b is a sense amplifier row, 16a, 16b, ... Are the first
, 16A, 16B, ... Is a second multidimensional selection circuit, and 20A is a second data bus.

Claims (5)

[Claims] 1. A plurality of cell arrays (10a, 10b, ...) To which a word address is commonly applied, and word lines selected based on the common word address applied to each cell array are read from each cell array. Corresponding data bit and the first dimension designation signal (x, y, s) designating the first small area of a predetermined dimension in the logical space, and corresponding to the designated first small area. A plurality of first multidimensional selection circuits (16a, 16b ...) Provided corresponding to each cell array for extracting a plurality of bits from input data bits.
...) and a plurality of bits respectively output from the plurality of first multidimensional selection circuits and a second of a predetermined dimension within a first small region of a predetermined dimension designated on the logical space. A second dimension designating signal (x ₂ , y ₂ , s ₂ ) complementing the first dimension designating signal for designating a small area is input, and a _second dimension designated from the input plurality of bits is input. Takes out multiple bits corresponding to a small area, data bus (20A)
The second multi-dimensional selection circuit (16A, 16B, ...
A multi-dimensional access memory comprising: 2. The first device provided along each cell array.
The multidimensional access memory according to claim 1, wherein the multidimensional selection circuit is shared by two adjacent cell arrays. 3. The word line of each cell array is selected a plurality of times in one cycle, and the entire read data of each time is selected as a selection target of the second multidimensional selection circuit. The multidimensional access memory according to item 1. 4. A circuit (DL0, DL1, ... 20a, 20b, ...) For transmitting the output of the first multidimensional selection circuit,
The multidimensional access memory according to claim 1, wherein the multidimensional access memory operates in a time division manner. 5. The multidimensional access memory according to claim 1, wherein the circuit (20A) for transmitting the output of the second multidimensional selection circuit operates in a time division manner.