JPH0612627B2 - Precharge signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a static RAM (random access memory) of MOS memories. In particular, the present invention relates to a precharge signal generation circuit suitable for constant voltage operation with a power supply voltage of about 1V.

(Conventional technology) According to conventional technology. Constant voltage static CMOS / RAM
The circuit configuration of (hereinafter abbreviated as LVSC / RAM) third
Shown in the figure. The timing is shown in FIG. LVSC /
In RAM, in order to prevent malfunctions by switching to word lines as in normal RAM. The bit line is precharged every time the word line is switched. This operation will be described with reference to FIGS. 3 and 4. Of the four memory cells M00, M10, M01, M11 in FIG. 3, the cell M00 is the first. Next, suppose cell M10 is selected. Only the read operation is considered at the timing shown in FIG. Ie. First, cell cell M00 is selected and its contents are read. Next, cell M10
Is selected and the reading is performed again. The memory contents of cells M00 and M10 are. It is assumed that they are 0 and 1, respectively. Since the precharge signal φc is L in the period T1, the precharge transistors Q1 and Q2 are turned on and the word line 1 and the word line 2 are set to L to close all the transfer gates TG of the memory cells M00 to M11. The bit line B0 and both become high level. The address changed within this precharge period. In this example, the word line 1 becomes H and at the same time the word line 2 becomes L at the timing when the precharge is completed. That is, the word line 1 is selected in the period T2. Therefore, in the T2 period, the cell M00
Because the contents of are read. Bit line B0 changes from H to L. Remains at H level. Address is switched to select cell M10 in period T3. The bit line precharge is performed as in the T1 period. Therefore, B0 changed to L in the T2 cycle. H in T3 period
Will be precharged. Since the cell M10 is selected in the period T4, the bit line B0 remains H and the bit line changes from H to L.

From the above description, in the normal LVSC / RAM, the bit line is precharged at the timing of address change.
It can be seen that all bit lines are set to H or L. It is assumed that the precharge is omitted during the period T3 in the timing chart of FIG. Since the data is read from the cell Moo during the period T2 and the bit line B0 is at the level L, the bit line B0 is at the level L and the bit line is at the level H during the period T3. In the T4 period, cell M10 is selected. The content of the cell M10 and the level of the bit line are opposite. A memory cell usually has a small pattern size, and the drive capability of the transistors constituting the cell is small. On the other hand, many memory cells are commonly connected to the bit line, and the bit line capacitances CB0 and BB0 are large. Therefore, when the cell M10 is selected, the contents of the bit line are written in the cell M10. That is, the contents of M10 are rewritten. If the bit line is precharged, the contents of the memory cell cannot be rewritten because both bit lines B0 and B0 are at the same potential level.

Also. The LVSC / RAM shown in FIG. 3 operates normally with a power supply voltage of about 2V. If it is operated with a power supply voltage of about 1 V, it will malfunction. Next, this malfunction mode will be described. The timing of the precharge signal φc and the word line signal of FIG. 3 is shown in FIG. In the same manner as in FIG. 4, the cell M00 in FIG. It is assumed that the cell M10 is selected in the period T4. The signal φc is a transistor Q for precharging.
Directly connected to the gate of 1, Q2. It is connected to the input of the word line address decoder WD. Therefore, when the signal φc changes from L → H at time t1. The precharge transistors Q1 and Q2 are turned off immediately. On the other hand, since the word line 1 has a gate delay in the word line decoder WD, it slightly rises from t1 and rises from L to H at t2.

Thus, the cell M00 is selected. Next, when moving to the selection of the cell M10. The signal φc changes from H to L at time t3. The bit line precharge is started. On the other hand, regarding the word line 1, the word line is closed at t4, which is slightly delayed from t3. In the above series of operations for selecting the cell M00, t
If you look directly at the time between 3 and t4. During this period, the transfer gates G of the cells M00 and M01 are open because the precharging transistors Q1 and Q2 are on and the word line 1 is H and the word line 1'is L. FIG. 6 shows the cell M00 and the precharging transistors Q1 and Q2. In the period from t3 to t4, Q1, Q2, Q9, Q in FIG.
All the transistors of Q10, Q11 and Q12 are on.
Assuming that the memory content of the cell M00 is 0, when the transfer gate composed of the transistors Q9, Q10, Q11 and Q12 is closed, the node 1 is at approximately 0V and the node 2 is at approximately + 1V (power supply voltage). In the period from t3 to t4, the potential of the node 1 is pulled by the transistor Q1 and rises. In the low voltage operation of about 1V, Vthp (Vth of the P-channel transistor) is about -0.3V to -0.8V. V
thn (Vth of n-channel transistor) is + 0.3V
It is set to about + 0.8V. The malfunction is that Vthp is -0.
At 3V. It occurs when the combination of Vthn is + 0.8V.
in this case. P-channel transistor | V-Vth |
Is 0.7V. That of an n-channel transistor is 0.2V. In this way, when the gate voltage is near Vth, the change in drain current with respect to the change in | VG-Vth | is large. The gm of the P-channel transistor in FIG. 6 is several tens of times that of the n-channel transistor.

The transfer gate G consisting of transistors Q9 and Q11 and Q10 and Q12 in FIG. 6 is composed of a pair of P-channel transistor and n-channel transistor.
In Vth of this example, the P-channel transistor is. It operates mainly because gm is large. The n-channel transistor of Q7 works to lower the potential of the node 1, but the potential of the n-channel transistor of Q7 rises to near VDD because the gm of the transistors Q1 and Q9 is large. That is, P that tries to raise the potential to VDD
Since the gm of the channel transistor is large, the potential of both the node 1 and the node 2 rises to approximately VDD during the period of t3 to t4, overcoming the small gm n-channel transistor that tries to reduce the potential to the ground potential. At this time, after the transfer gate TG is closed at time t4, it becomes uncertain whether the contents of the memory cell formed by the transistors Q5, Q6, Q7, and Q8 will return to 0 or 1. That is, the content of the memory cell changes. Ie VDD
Is about 1V, the conventional circuit of FIG. 3 has a drawback that the operation becomes unstable.

(Problems to be Solved by the Invention) This was done in view of the instability of operation in the conventional technology. LVSC even when the power supply voltage is low
It is an object of the present invention to provide a precharge signal generation circuit capable of stably operating / RAM.

[Structure of the Invention] (Means and Actions for Solving Problems) In order to achieve the above-mentioned object, the present invention. In static type RAM of low voltage operation. A pseudo delay circuit including a pseudo decoder and a pseudo memory cell. The bit line precharge signal is input to one input through the pseudo delay circuit, the bit line precharge signal is directly input to the other input, and the output is precharged while the word line is closed. And a two-input NOR gate for outputting an internal precharge signal to be executed. By precharging while the word line is closed. Avoid overlapping the period when the transfer gate of the memory cell is open and the period when the precharge transistor is on. Even when the power supply voltage is as low as about 1 V, the operation is stable.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.

The target timing of the present invention is shown in FIG. Precharge is released at time t1 at the timing shown in FIG. Thereafter, the operation of activating the word line at time t2 can be realized by the circuit shown in FIG. That is, since the precharge signal is directly input to the gates of the precharging transistors Q1 and Q2 and also input to the address decoder WD, the word line is opened by the address recorder WD.
After the gate delay time at. On the other hand, at times t3 and t4, the word line is closed at t3 and then precharged at t4. This is not realized with the circuit of FIG. In order to realize this, it is necessary to detect the timing when the word line is closed and then activate the precharge transistor. That is, the precharge signal φc
Changes from L to H (precharge release timing)
First, release the precharge as shown in Fig. 3. At the timing when the precharge signal φc is H → L (precharge execution), a circuit for precharging after the word line is closed is required.

An example of a circuit that can generate the timing shown in FIG. 7 is shown in FIG. However, FIG. 8 is not for the purpose of the present invention but for the purpose of explaining the present invention. 8 is different from FIG. 3 in that a precharge signal delay circuit PD is provided. The internal precharge signal φc ′ is delayed with respect to the signal φc. In this delay circuit PD, the delay time when the signal φc changes from L → H is tφL
Let H be the time when the signal φc changes from H → L to tφHL. Further, the delay time when the signal φc changes from L to H in the decoder WD is tDLH, and the delay time when the signal φc changes from H to L is tDHL. At this time, the desired timing shown in FIG. 7 can be satisfied if there is a relationship of tDLH> tφLH and tφHL> tDHL as shown in the timing of FIG. However, in this way, there is a different delay time for the rising and falling edges of the input signal, and the delay amount of the decoder advances. The precharge signal delay circuit PD having a delay is very difficult in design. To obtain the timing shown in FIG. When the signal φc changes from H to L, the internal precharge signal φc 'detects that the word line is closed. Then, a circuit to which the signal φc 'responds is required. Furthermore, this circuit must be stable and operate reliably. In this embodiment, a circuit composed of a pseudo decoder and a pseudo memory cell is used to detect the closing of the word line, and the signal is delayed by this pseudo delay circuit at the timing when the signal φc is H → L. For L → H of the signal φc ,. The feature is that the precharge is released before passing through this circuit and opening the word line.

A circuit for generating the internal precharge signal .phi.c 'according to the present invention is shown in FIG. Figure 1 shows. Pseudo decoder DD fixed to VDD (H) except for precharge signal φc in the same circuit as word line decoder WD except for precharge signal φc. An example of pseudo memory cells DM and. It is composed of several gates G. In the pseudo memory cell DM, only the transfer gate TG is connected to the word line and the bit lines B0,
It is not connected to B1. The timing of the circuit of FIG. 1 is shown in FIG. In FIG. 2, the precharge signal φc is L →
When the signal changes to H, the signal φc is input to the NOR gate G1. The change of the signal φc is transmitted through this path. The internal precharge number φc 'changes from L to H. At this time, the word line driving the memory cell DM is. Decoder DD
Because there is a delay time in. Also, it does not become active and becomes active a little later. Next, when the signal φc changes from H to L, the 2-input NOR gate G to which the signal φc is directly input becomes active. Internal precharge signal φ
c'does not change immediately and enters the other input waiting state. That is, the internal precharge signal .phi.c 'changes from H to L after the signal passed through the pseudo decoder DD is input to the NOR gate. That is, the internal precharge signal changes after the word line changes from H to L. The timing relationship between these two
Shown in the figure. By using the circuit of FIG. 1, it becomes possible to surely perform the precharge while the word line is closed. The number of elements will increase if this circuit is added. For example, in a 16-bit x 32-word (512-bit) RAM. One word for the pseudo memory cell DM. One decoder as the pseudo decoder DD. Only a few gates have been added to this. The increase in the number of elements can be made negligibly small.

As above. LVSC / RAM with power supply voltage of about 1V
Then. In the conventional circuit. If precharged while the word line is active. In particular, there is a problem that the contents of the memory cell become unstable when the Vth of the P-channel transistor and the n-channel transistor vary between the two electrodes. In order to solve this problem, we considered a new circuit system that ensures precharge when the word line is inactive. Since this circuit uses the same decoder and memory cells as the on-chip memory, the operation is reliable, the design is easy, and the area increase can be ignored. Therefore, this circuit is suitable for a low voltage RAM.

still. This circuit was used for a display pager (T5848) and its normal operation has been confirmed.

[Effects of the Invention] According to the present invention as described above. By precharging while the word line is closed. Avoid overlapping the period when the transfer gate of the memory cell is open and the period when the precharge transistor is on. LVSC even when the power supply voltage is as low as 1V
It is possible to provide a precharge signal generation circuit capable of stably operating / RAM.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an embodiment of the present invention. Figure 2 shows the first
Operation timing diagram of figure. Figure 3 shows the conventional LVSC / RA
Circuit diagram showing M. FIG. 4 is an operation timing chart of FIG.
FIG. 5 is an explanatory diagram of a timing problematic in the conventional circuit. FIG. 6 is a circuit diagram showing a circuit related to malfunction in the conventional circuit.
FIG. 7 is a timing diagram necessary for normal operation of the present invention. 8th
The figure is a circuit diagram showing an example of a circuit that can realize the normal operation timing of FIG. FIG. 9 is a timing chart for explaining that the circuit of FIG. 8 is very difficult to realize. DD ... Pseudo decoder. DM: Pseudo memory cell. G ...
…Gate. φc ... Precharge signal. φc '... Internal precharge signal.

Claims (1)

[Claims] 1. In a static RAM of low voltage operation, a pseudo delay circuit comprising a pseudo decoder and a pseudo memory cell, and a bit line precharge signal is inputted to one input through said pseudo delay circuit and the other is inputted. A two-input NOR gate for directly inputting a bit line precharge signal to the input and outputting an internal precharge signal for precharging while the word line is closed. Charge signal generation circuit.