JPH0612787B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, and more particularly to a fuse element capable of being blown by laser light irradiation for element relief or adjustment of circuit constants. The present invention relates to a fuse position alignment mark in a semiconductor device.

(Prior Art) For example, when manufacturing a memory integrated circuit, a redundant circuit for relieving a defective memory cell is mounted, and a fuse element is blown by irradiating a laser beam to relieve the element (hereinafter referred to as laser The so-called melting method) is used. In this case, the metal layer formed at the same time when the metal wiring layer is formed is used as the fuse alignment mark. That is, as shown in FIG. 2, the surface of the semiconductor substrate 23 is irradiated with the laser light 24 from the laser light source 21 through the optical system 22, and
The vicinity of the fuse alignment mark 25 formed on the substrate is scanned by the laser light 24, and the reflected light 26 is received by the processing unit 28 via the beam splitter 27 to obtain the reflected wide intensity distribution, and based on this distribution The position of the mark 25 is confirmed, and the position of the fuse element to be blown is determined based on this result. The reflected light intensity distribution is as shown in the schematic diagram of FIG. 3, and the beam waist of the laser light is substantially equal to the width of the mark 25 and is close to the normal distribution. Therefore, the position of the mark 25 can be determined by selecting the maximum portion of the reflected light intensity. Since the mark 25 and the fuse element are positioned with respect to each other in the photo-etching process, if the position of the mark 25 is known, it is possible to perform alignment for selecting the fuse element to be blown.

By the way, in a semiconductor device using a multilayer metal wiring layer, conventionally, a metal layer made of the same layer as the uppermost metal wiring layer has been used as a fuse alignment mark. However, in this case, since the surface of the underlying insulating film of the mark lacks smoothness due to the presence of irregularities, the mark surface may be rough. Then, when the vicinity of the mark is scanned with the laser beam, the base insulating film is not melted in the previous step,
Laser light is scattered by the unevenness of the surface. As a result, the intensity of the reflected light at the mark portion is greatly reduced and its variation is increased, so that the mark cannot be accurately confirmed and the fuse element to be blown cannot be aligned. In order to avoid this problem, the surface of the base insulating film may be smoothed, but metal wiring (aluminum alloy wiring or the like) in the uppermost layer is often present on the surface, which is difficult to realize. . Also, when removing the protective film on the uppermost wiring layer during the process of the semiconductor integrated circuit,
The mark surface may be roughened because it comes into contact with the etching liquid or the etching gas, which disturbs the reflected light intensity distribution and makes it difficult to accurately confirm the mark position.

(Problems to be Solved by the Invention) The present invention has been made to solve the problem that it is difficult to confirm the fuse alignment mark as described above, and position detection by laser light scanning can be favorably performed. An object of the present invention is to provide a semiconductor device having a fuse alignment mark and capable of improving the workability of fuse blowing and the product yield.

[Structure of the Invention] (Means for Solving the Problems) A semiconductor device according to the present invention is also a semiconductor device having a multilayer wiring layer and a fuse element capable of being blown by a laser beam. The fuse alignment mark is formed by the same metal layer as the lowermost metal wiring layer.

(Operation) Usually, since the surface of the underlying insulating film of the lowermost metal wiring layer is smooth, the mark surface is also smooth, and the reflected light with high reflectance and less variation can be obtained from the mark when scanning the laser beam. In addition, the lowermost metal wiring layer does not come into contact with the etching liquid or the etching gas during the process, and the mark surface does not become rough.

Therefore, the position of the mark can be accurately and quickly confirmed, the position of the fuse element to be blown can be accurately and quickly aligned, and the workability and the yield rate can be improved. Become.

Embodiment An embodiment of the present invention will be described in detail below with reference to the drawings.

Figure 1 has a multilayer wiring layer, shows a portion of a semiconductor integrated circuit fusible is fuse element and fuse alignment mark 8 ₃ capable is formed by laser beam irradiation.
That is, 1 is a silicon substrate, 2 is a field oxide film, and 3 is a field oxide film.
Impurity region for source / drain of MOS transistor,
Reference numeral 4 is a gate oxide film, 5 is a gate electrode, and 6 is a first CVD film formed by a chemical vapor deposition (CVD) method at a low temperature. A boron / phosphorus-containing glass film (hereinafter referred to as BPSV) is formed on the CVD film 6.
A film 7) is deposited and melted, and its surface is smooth. On the BPSG film 7, the metal wirings 8 ₁ and 8 ₂ of the first layer and the fuse alignment mark 8 are formed.
₃ is formed in a predetermined pattern, and the material thereof is aluminum-silicon-copper alloy, and a part of the metal wirings 8 ₁ and 8 ₂ is the BPSG film 7 and the first CVD film 6
The drain and source of the MOS transistor are in contact with each other through a contact hole formed in. Further, a second CVD film (eg, plasma CVD film) 9 is formed on the first metal wiring layer, and a second metal wiring layer (made of aluminum / silicon / copper alloy) 10 is formed thereon. _1, 10 ₂ are formed. the second-layer metal wiring 10 _1, 10 _2, the second CVD film 9 the first-layer metal wiring through openings through holes 8 ₁ ，
It is put in contact with 8 _2. Then, a phosphorus-containing glass film (PSG film) 1 is formed as a protective film on the second metal wiring layer.
1 is formed, and an opening portion 11 'for bonding wiring is provided in a part thereof.

According to the above semiconductor integrated circuit, when confirming the position of the fuse alignment mark 8 ₃ as a result of the die sort test, the laser beam 24 is irradiated so as to scan the vicinity of the mark 8 ₃ as shown in FIG. When the reflected light 26 is received and processed, the mark position can be detected accurately and quickly. That is, the surface of the BPSG film 7 as the base insulating film mark 8 ₃ is smooth, which by little scattering of the laser beam, and because mark 8 ₃ has no step to touch the etchant or etching gas, its surface since smooth even with a high laser beam reflectivity, mark 8 ₃ reflected light is sufficiently from, and allows accurate detection of the mark position by stably obtained. Therefore, the position of the fuse element to be blown can be accurately and promptly adjusted based on the detected position, and the workability and the yield of the fuse blow can be improved. In addition, the reflectance of the mark is 80 to 9
It has been confirmed that a high value of about 0% can be obtained, and even if the reflectance of the underlying insulating film is as high as about 30%, it is possible to wait for a higher reflectance than this as a mark. Therefore, there is no hindrance, in other words, the tolerance for process variations increases, and high productivity can be achieved.

[Advantages of the Invention] As described above, according to the semiconductor device of the present invention, the position of the fuse alignment mark can be accurately detected, and the alignment of the fuse element to be blown can be performed accurately and quickly. It is possible to improve the workability of fuse blowing and the product yield.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing an essential part of an embodiment of a semiconductor device of the present invention, FIG. 2 is a view showing a method of detecting the position of a fuse alignment mark of the semiconductor device, and FIG. 3 is a view of FIG. It is a figure which shows the correspondence of the reflected light intensity distribution and a mark in a method. 1 ... Semiconductor substrate, 6,9 ... CVD film, 7 ... BPSG film,
8 _{1, 8 2} ...... first-layer metal wiring, _{8 3} ...... fuse alignment _marks, 10 1, 10 ₂ ...... second-layer metal wiring, 11 ...... PSG film.

Claims (1)

[Claims] 1. A semiconductor device having a multi-layered wiring layer and a fuse element capable of being blown by a laser beam, wherein a fuse position alignment mark is formed by the same metal layer as the lowermost metal wiring layer in the multi-layered wiring layer. A semiconductor device comprising: