JPH0612820B2 - Semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly to a high speed and highly reliable MOSFET.

[Conventional technology]

FIG. 2 (a) shows a surface channel type MOS based on the prior art.
The cross-sectional structure of FET is shown. Here, N channel MOSF
Taking ET as an example, its operation mechanism will be described.

As can be seen from the figure, the source region 4 and the drain region 5 are formed so as to be exposed on one surface of the semiconductor substrate 1, and the surface of the semiconductor substrate 1 exposed between the source region 4 and the drain region 5 is The gate electrode 3 is provided via the gate oxide film 2.

FIG. 2 (b) is an energy band diagram when the gate electrode V _GS reaches the threshold voltage V _th . In the same figure (b), the curve E _c is the conduction band energy level, the curve E _i is the intrinsic semiconductor Fermi level, the curve E _F is the p-type semiconductor Fermi level, and the curve E _V is the valence band upper limit energy level. Shows.

Since the channel of the FET is formed only on the surface of the semiconductor substrate 1, the drain current is concentrated in the depth range of several tens of angstroms from the substrate surface.

A large electric field in the vertical direction (depth direction) is present on the surface of the semiconductor substrate 1 perpendicularly to the direction of the drain current, as can be seen from the bending of the band in FIG. 2 (b). Maximum on the surface. Therefore, the mobility of electrons decreases due to the effect of surface scattering.

As described above, in the conventional MOSFET, the decrease in mobility due to the high vertical electric field on the surface of the semiconductor substrate is an obstacle to obtaining a large drain current.

A second problem with conventional MOSFETs is the degradation of device reliability due to hot carriers.

That is, when the gate is miniaturized, the peak of the electric field concentrated at the drain end under the gate becomes large, so that here, sufficient energy is required for carriers to cross the energy barrier between the silicon and the oxide film. Then, it is taken into the gate oxide film to change the characteristics of the device.

Therefore, in miniaturizing the gate, a means for suppressing the injection of carriers into the gate oxide film is needed.

As one of means for solving these problems, a structure as shown in FIG. 3 has been proposed (see JP-A-60-50960).
The feature of the structure shown here is that the p-type impurity layer 6 and the n-type impurity layer 7 are formed from the surface of the channel region under the gate, and the pn junction is provided at a predetermined depth from the surface of the substrate 1. That is. As is apparent from FIG. 3, the p-type impurity layer 6 is formed on the surface of the semiconductor substrate 1, and the n-type impurity layer 7 is formed below the p-type impurity layer 6.

The operation of the MOSFET of this structure is shown in FIGS. 4 (a) and (b).
Will be explained. FIG. 4 (a) is the same sectional structure diagram as FIG. 3, and FIG. 4 (b) is a diagram showing such an energy band along the line AA ′ in FIG. 4 (a).

First, when no voltage is applied to the gate electrode 3 (V _GS
= 0), by appropriately selecting the concentrations of the p-type impurity layer 6, the n-type impurity layer 7, and the p-type substrate 1, contact between the n-type impurity layer 7 and the p-type impurity layer 6 and the p-type substrate 1 is achieved. Due to the built-in potential difference caused by
The entire area of the type impurity layer 7 can be a depletion layer.

Therefore, in the structure of FIG. 3 or 4 (a), the drain current does not flow when the voltage is not applied to the gate electrode 3.

Next, when a voltage equal to or higher than the threshold voltage V _th is applied to the gate electrode 3, the width of the depletion layer spreading in the n-type impurity layer 7 is reduced, the neutral region is spread in the n-type impurity layer 7, and the channel 7 is formed.
1 is formed. And this channel contributes as a current path.

In the channel 71 in this semiconductor substrate, as shown in the band diagram of FIG. 4 (b), the bending degree of the band is shown in FIG. 2 (b).
It is gentler than in the case of. Therefore, the electric field existing in the depth direction of the substrate is small, and the decrease in mobility is less than in the surface channel type.

In addition, the channel 71 in the semiconductor substrate that serves as a current path is
It is located farther from the gate oxide film than the channel on the surface of the semiconductor substrate. Therefore, even if the carriers are accelerated by the voltage between the source region 4 and the drain region 5 and a large amount of energy is obtained, the probability that the carriers are injected into the gate oxide film is significantly reduced.

Therefore, according to the structure of FIG. 3 or 4 (a), compared with the surface channel MOSFET shown in FIG. 2 (a),
Even when used for a long period of time, the variation in characteristics is small and high reliability can be obtained.

However, the MOS of the structure shown in FIG. 3 or FIG.
In the FET, when the voltage applied to the gate electrode 3 is further increased, the ratio of the current flowing through the inversion layer 61 formed on the surface of the p-type impurity layer 6 increases.

Therefore, the surface channel MOSFET shown in FIG.
In the same manner as described above, there may be a case where carrier mobility lowers or characteristic deterioration due to hot carriers becomes a problem. Therefore, even if a high voltage is applied to the gate, no current flows on the surface of the semiconductor substrate, and it is necessary to take measures so that the photo carriers do not become a problem.

[Problems to be solved by the invention]

In any of the conventional techniques shown in FIGS. 2 to 4, an inversion layer is formed on the surface of the semiconductor substrate, which also serves as a current path. When the voltage applied to the gate electrode is increased, the number of carriers in the inversion layer on the surface is increased,
The ratio of the current flowing through the surface channel in the drain current of the FET increases.

For this reason, it has been impossible to sufficiently suppress deterioration of carrier mobility and deterioration of characteristics due to hot carriers in the related art.

An object of the present invention is to allow current to flow only at a certain depth from the surface of the semiconductor substrate without flowing through the channel on the surface of the semiconductor substrate, thereby sufficiently suppressing deterioration of carrier mobility and deterioration of characteristics due to hot carriers. It is to provide a MOSFET that can do so.

[Means for solving problems]

The above object can be achieved by adopting a structure in which the length of the gate electrode 3 is shorter than the distance between the source region 4 and the drain region 5, as shown in FIG.

[Action]

In a normal MOSFET, the end portions of the source and drain regions (diffusion layers) are aligned with both ends of the gate electrode or are located inside the gate electrodes to some extent. As a result, the source and drain regions of the MOSFET are electrically connected to each other by the inversion layer induced under the gate electrode in the ON state.

In the structure of the present invention shown in FIG. 1, depending on the inversion layer formed on the surface of the semiconductor substrate under the gate electrode, the gate electrode is formed short so that the source and drain regions are not electrically connected. This can prevent current from flowing on the surface of the semiconductor substrate.

〔Example〕

FIG. 1 is a sectional view of an embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 3 represent the same or equivalent parts.

As is clear from the comparison with FIG. 3, in this embodiment, the gate electrode 3 provided in the channel region between the source and drain regions 4 and 5 with the gate oxide film 2 interposed therebetween.
However, the distance between the source region 4 and the drain region 5 is shortened.

FIGS. 5 (a) and 5 (b) are views for explaining the operation of the MOSFET according to the present invention, and FIG. 5 (b) shows the energy band along the line BB 'in FIG. 5 (a). . In addition, the semiconductor substrate 1
The shaded area indicates the part where many carriers are present.
Reference numeral 1 is a surface inversion layer, and diagonal lines 71 are channels formed in the semiconductor substrate.

As clearly shown in FIG. 5A, the surface inversion layer 61 is not formed on the end side of the source region 4 and therefore does not contribute as a current path between the source region 4 and the drain region 5.

Thus, in the MOSFET of the present invention, since there are no carriers flowing near the surface of the semiconductor substrate 1, the probability of hot carriers jumping into the gate oxide film 2 is greatly reduced.
Therefore, deterioration of the characteristics is small even after long-term use, and a highly reliable MOSFET can be realized.

The operation of the MOSFET shown in FIGS. 1 and 5 (a) will be described in detail below. 6 (a) and 6 (b) are diagrams showing the energy band in the ON state of the channel portion of the MOSFET shown in FIG.

FIG. 6 (a) is an energy band taken along the line CC 'in FIG. 1, and FIG. 6 (b) is an energy band taken along the line DD' in FIG. . That is, FIG. 6A shows the energy band of the channel in the p-type impurity layer 6 on the surface of the semiconductor substrate, and FIG. 6B shows the energy band of the channel in the n-type impurity layer 7 therebelow.

On the surface of the p-layer of the semiconductor substrate 1, as shown in FIG. 6 (a), a potential peak occurs in the portion where the gate electrode 3 and the source region 4 do not overlap. Therefore, the electrons emitted from the source cannot reach the drain along this path.

On the other hand, as shown in FIG. 6 (b), in the channel in the semiconductor substrate, the potential continuously decreases from the source to the drain, so that a current can easily flow along this path. .

FIGS. 7 (a) and 7 (b) explain the transition of the MOSFET having the structure shown in FIG. 1 from the off state to the on state by showing how the depletion layer spreads.

FIG. 7 (a) shows the spread of the depletion layer in the off state. Due to the depletion layer extending from the junction between the p-type impurity layer 6 and the n-type impurity layer 7 and the depletion layer extending from between the p-type substrate 1 and the n-type impurity layer 7, the channel 71 indicated by diagonal lines in the semiconductor substrate 1 It is divided and no current flows between the source and drain.

Here, the channel 71 includes the source and drain regions 4,
Electrons overflow from the heavily doped source and drain diffusion regions 4 and 5 at the portions in contact with each other, so that the electron concentration is higher than that in the central portion of the channel and the state is in equilibrium.

Therefore, at both ends of the channel 71, the width of the depletion layer extending from above and below is relatively narrow, and as shown in FIG. 7 (a), the channel is not completely closed in the off state.

FIG. 7 (b) shows the expansion of the depletion layer in the ON state. By applying an appropriate voltage to the gate 3,
Since the width of the depletion layer extending from the junction between the p-type impurity layer 6 and the n-type impurity layer 7 is reduced, the channel 7 in the semiconductor substrate is reduced.
1 is continuous between the source region 4 and the drain region 5,
An electric current flows here.

At the same time, the inversion layer 61 is also formed on the surface of the semiconductor substrate, but since the channel region in contact with the source region 4 is not covered by the gate electrode 3, the inversion layer is not formed in this portion, and the surface inversion layer 61 is formed. Source region 4 and drain region 5
Will not be connected.

Therefore, the current does not flow in the channel near the surface of the semiconductor substrate 1, and the current flows only in the channel formed in the n-type impurity layer 7 inside the semiconductor substrate 1.

Inside the semiconductor substrate 1, the electric field in the vertical direction is smaller than that in the channel formed on the surface of the semiconductor substrate, and the carriers generated in the channel portion 71 are less accelerated in the gate direction. Further, when a current flows inside the semiconductor substrate, the distance to the gate is long, and thus the probability that the generated carriers reach the gate is reduced.

Therefore, according to the present invention, it is difficult for hot carriers to be injected into the gate, and a MOSFET with less characteristic deterioration can be realized.

In addition, since the current flowing inside the semiconductor substrate has no contact with the gate oxide film and the longitudinal electric field is relaxed as compared with the case of the surface channel, carrier mobility is lowered due to scattering with the gate oxide film. Also few. Therefore, according to the present invention, it is possible to realize a MOSFET having a high current driving force and capable of obtaining a large drain current.

FIG. 8 is 1 of the MOSFET manufacturing process flow of FIG.
This is an example. The outline will be described below step by step.

(1) First, using a p-type semiconductor substrate with a sheet resistance of 2 Ωcm,
After forming a LOCOS (selective oxidation) film 8 of 000Å and an oxide film 18 of 3000Å, an acceleration voltage of 150 KV and an implantation amount of 2 ×
Phosphorus is ion-implanted at 10 ¹² cm ^-2 to form the n-type impurity layer 7.

(2) Next, accelerating voltage 45KV, implantation amount 3 × 10 ¹² cm
^{At -2} , BF ₂ is ion-implanted to form the p-type impurity layer 6 on the surface side of the n-type impurity layer 7.

(3) After removing the oxide film 18 as much as possible, once again, 300
A 0Å gate oxide film 2 is formed, and polycrystalline silicon is deposited on its surface to a thickness of 5000Å.

After reducing the resistance by phosphorous treatment, the gate electrode 3 having a desired shape is processed by the photolithography technique.

(4) After depositing a silicon oxide film to a thickness of 5000Å so as to cover the gate oxide film 2 and the gate electrode 3, isotropic etching is performed to form an insulating sidewall 12 around the gate 3.

Then, arsenic is ion-implanted at an acceleration voltage of 80 KV and an implantation amount of 5 × 10 ¹⁵ cm ^-2 by the self-alignment method using the gate 3 and the sidewall 12, and the source 4
And the drain 5 is formed.

(5) After depositing the interlayer insulating film 10 on the gate oxide film 2, the gate electrode 3 and the sidewall 12, contact holes for the source and the drain are formed by the photolithography technique. Aluminum, which is the wiring material, is deposited to a thickness of 8000Å and processed into wiring shape 9 by photolithography technology. Finally, the passivation film 11 is deposited.

Through the above steps, it is possible to form an n-channel MOSFET having a structure in which the length of the gate is shorter than that of the channel region between the source and the drain as shown in FIG.

FIG. 9 (a) is a sectional view of another embodiment of the present invention.

In the off state, the embodiment shown in FIG.
As shown in (a), the channel 71 in the semiconductor substrate is not completely closed near the source and drain regions, and the channel 71 is blocked only near the center.

Therefore, when the gate dimension is further reduced, the channel 71 remains continuous even in the off state, and the current cannot be controlled by the gate voltage.

The embodiment of FIG. 9 (a) improves the short channel characteristics by making the width of the n-type layer 7 wider than that of the p-type layer 6.

As described above, in the n-type impurity layer 7, the source region 4 and the drain region 5 which are high-concentration n-type impurity layers.
Due to the electrons overflowing from the depletion layer, there is a portion where the depletion layer is difficult to spread, and the source and drain are substantially close to each other.

Therefore, in this embodiment, the short channel characteristic is improved by widening the length of the n-type impurity layer 7 and compensating for the length of the overflow of electrons in advance.
FIG. 9 (b) shows this state, but since its details can be easily understood from comparison with FIG. 7 (a), the explanation thereof is omitted here.

In the above, the MOSFET configured on the p-type semiconductor substrate
However, the present invention can also be applied to a substrate having a so-called SOI (Silicon on Insolator) structure in which a single crystal silicon film is arranged on an insulating substrate such as quartz or sapphire. Obviously, needless to say, the SOI substrate may be a silicon oxide film provided on silicon. It can also be applied to a p-channel MOS by changing the conductivity type of impurities.

〔The invention's effect〕

In the MOSFET having the structure according to the present invention, since the current flows only inside the semiconductor substrate, the probability that the generated hot carriers are injected into the gate and the oxide film around the gate is reduced, and the characteristics deteriorate even when used for a long time. There is an effect that can reduce.

Further, unlike the surface, the electric field in the vertical direction is small inside the semiconductor substrate, and the scattering between the inside of the semiconductor substrate and the gate oxide film is small, so that the decrease in carrier mobility is small. Therefore, a large current driving force can be realized and a large drain current can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention, and FIGS. 2 (a) (b).
Is a diagram for explaining the structure and operation of the conventional element, FIG. 3 is a sectional view showing the structure of a conventional example, FIGS. 4 (a) and 4 (b) are diagrams for explaining the operation of the element of FIG. 3, and FIG. (a) (b), FIG. 6, FIG. 7 (a) (b)
Is a diagram for explaining the operation of the device according to the present invention, and FIG.
FIGS. 9 (a) and 9 (b) are sectional views showing another embodiment of the present invention, showing the manufacturing process of the device shown in FIG. 1 ... Semiconductor substrate, 2 ... Gate oxide film, 3 ... Gate electrode, 4 ... Source region, 5 ... Drain region, 6 ...
p-type impurity layer, 7 ... N-type impurity layer, 71 ... Channel

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Masataka Minami, 4026 Kuji Town, Hitachi City, Hitachi, Ibaraki Prefecture, Hitate Works, Ltd., Hitachi Research Laboratory (72) Takahiro Nagano 4026, Kuji Town, Hitachi City, Hitachi, Ibaraki Prefecture, Hitachi Co., Ltd. Within Hitachi Research Laboratory (56) Reference JP-A-60-50960 (JP, A) JP-A-48-101887 (JP, A)

Claims (4)

[Claims] 1. A source / drain region of a first conductivity type, which is disposed on both sides of a channel region so as to face each other, and a gate electrode disposed on the surface of the channel region with a gate insulating film interposed therebetween. In a semiconductor device in which the channel region is composed of a second-conductivity-type region on the front surface side and a first-conductivity-type region immediately below the first-conductivity-type region, even when a gate voltage for forming a desired channel is applied in the first-conductivity-type region. , Second below the gate electrode
The length of the gate electrode in the channel region direction is shorter than the distance between the source and drain regions so that the inversion layer formed on the surface of the conductivity type region does not connect the source region and the drain region. Semiconductor device. 2. The length of the second conductivity type region forming the channel region in the channel region direction is made shorter than that of the first conductivity type region directly below the second conductivity type region. The semiconductor device according to the item. 3. The semiconductor device according to claim 1, wherein the channel region, the source and drain regions are formed on the second conductivity type semiconductor substrate. 4. A semiconductor device according to claim 1, wherein the channel region, the source and drain regions are formed on an insulating substrate.