JPH0612877B2 - Divide pulse transmission circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A circuit that divides an output pulse of an encoder directly connected to an electric motor to 1 / N and sends the output pulse, which is generated when the electric motor is stopped midway and restarted. This circuit has a function of absorbing the timing error of the divide pulse before and after.

[Industrial application field]

The present invention relates to a pattern recognition device, and more particularly to a divide pulse sending circuit that moves a relative position between a detection head and a measured pattern and sends a pulse as a reference for calculating a distance from a rotation amount of an electric motor.

A keyboard used as an input device of various electronic devices is a part that is touched by an unspecified number of people including an operator, and information input is displayed on a key top inserted into a push button switch that constitutes the keyboard. It is done based on letters and symbols. Therefore, the arrangement of key tops, which is the basis for inputting information, is absolutely not allowed. However, the arrangement of the characters and symbols displayed on the keytop differs depending on the keyboard model, and at the same time, the size of the characters and symbols, the font, the line thickness, etc. also differ depending on the keyboard model.

Therefore, in the keyboard manufacturing process, a pattern recognition device is used to inspect the arrangement of characters and symbols for each keyboard, but if a defect is detected during the inspection, it is temporarily stopped and the defect location and defect content are displayed. Then, the next inspection is continued by restarting.

However, the detection stage or the moving stage on which the pattern to be measured is mounted and the electric motor that moves it are connected via a conduction mechanism such as a belt, and the information from the detection head follows the output pulse of the encoder directly connected to the electric motor. Is output. When the electric motor is once stopped in a device having such an electric conduction mechanism, the electric motor rotates in the opposite direction due to the tension of the belt or the like, and even if the electric motor is restarted, the stage cannot move until the tension of the belt or the like is restored. Not done However, a pulse signal is output from the encoder, and when the detection head outputs information by the pulse signal during this period, the dimming for outputting information is deviated.

Therefore, the pattern recognition device having such a power transmission mechanism must have a function of absorbing the timing error of the pulse signal before and after the stop, which occurs when the electric motor is stopped midway and restarted.

[Conventional technology]

FIG. 2 is a circuit diagram showing an example of a divide pulse transmission circuit according to a conventional method, and FIG. 3 is a time chart showing an output signal waveform.

An encoder 2 directly connected to the DC motor 1 in FIG.
The output pulse of is composed of two kinds of signals which are approximate to a sine wave as shown in FIGS. 3 (a) and 3 (b), and the two kinds of signals whose phases are deviated by 90 degrees are inverted in the front-rear direction depending on the rotation direction. When these two types of signals are shaped by the waveform shaping circuit 3 as shown in FIGS. 3 (b) and 3 (e) and are rotated clockwise, for example, a (+) pulse as shown in FIG. 3 (c). If the signal rotates counterclockwise again, as shown in Fig. 3 (f), (-)
2 is input to the counter 5 via the OR circuit 4 as shown in FIG. Since the period of the pulse signal varies depending on the rotation speed of the DC motor 1 and synchronization is difficult,
A divide condition is set in the asynchronous counter 5 used, and the counter 5 outputs a divide pulse according to the set divide condition. For example, if the divide condition N = 3, one divider pulse is output from the counter 5 for three pulse signals input to the counter 5.

[Problems to be solved by the invention]

In the conventional divide pulse sending circuit, the pulse signals output from the encoder are added by the counter regardless of the rotating direction of the DC motor. Therefore, the DC motor that stopped halfway rotates in the opposite direction due to the tension of the belt, etc., and the pulse signal output from the encoder until the tension of the belt, etc. is restored by restarting is also added by the counter and a divide pulse is generated. Is output. That is, there is a problem that an error occurs in the timing of the divide pulse before and after the stop.

[Means for solving problems]

FIG. 1 shows a principle block diagram of a divide pulse transmitting circuit according to the present invention.

The problems described above include a waveform shaping circuit 3 that shapes the output pulse of the encoder 2 that is directly connected to the DC motor 1, an up-down counter 6 that counts the input pulse and outputs a binary code, and a code in which the binary code is preset. If it meets the condition, the decoder 7 that outputs a divide pulse to the external circuit and the reset circuit 8 that has the monostable multi 83 and that uses the divide pulse to reset the up / down counter 6 are provided, and the DC motor 1 is operated in sequence. The output pulse from the waveform shaping circuit 3 when rotating in the forward direction is input to the up terminal 62 of the up / down counter 6, and the output pulse from the waveform shaping circuit 3 when the DC motor 1 rotates in the reverse direction is increased. The divide pulse transmission of the present invention for adding or subtracting the number of pulses by inputting it to the down terminal 63 of the down counter 6. It is solved by road.

[Action]

In FIG. 1, a pulse signal in the (+) direction and a pulse signal in the (-) direction are input to an up / down counter (hereinafter referred to as a counter) 6, and when the pulse signal in the (+) direction is input, the up counter The number of added pulses and the added pulse are output as a binary code. Then, for example, a binary code indicating a divide condition N = 3 is preset in the decoder 7, and when the counter 6 receives three (+) direction pulse signals, the decoder 7 outputs an external signal via the reset circuit 8. The pulse signal is output to the counter 6 and the reset circuit 8 resets the counter 6.

On the other hand, when a pulse signal in the (-) direction is input, it is subtracted from the number of pulses up to that point by a down counter, and the number of subtracted pulses is output as a binary code. The direction of the pulse when it is assumed that 10 input, binary code 8 output from the counter 6 - for example as a counter 6 using counter 2 ⁴ binary, (+) after the direction of the input two pulses () In the meantime, the code does not match the preset binary code indicating N = 3 in the decoder 7, and the pulse signal is not output from the decoder 7. Therefore, the counter 6 is not reset during that time.

When a pulse signal in the (+) direction is input again from such a state, it is added by the up counter, and the number of added pulses is output as a binary code. But the initial value is 8
It is a binary code indicating that the pulse signal is not output from the decoder 7 until 11 pulse signals in the (+) direction are input. That is, after returning to the state before the pulse signal in the (-) direction is input, the addition of the pulse signal in the (+) direction starts again from that point, and the binary code output from the counter 6 is preset in the decoder 7. Has been N
When the binary code indicating = 3 is satisfied, a pulse signal is output from the decoder 7 via the reset circuit 8 to the outside, and the reset circuit 8 resets the counter 6.

Therefore, by using this divide pulse sending circuit, the DC motor stopped halfway rotates in the opposite direction due to the tension of the belt, etc., and a pulse signal is output from the encoder until the tension of the belt, etc. is restored by restarting. Even if it is done, the pulse number is accurately added and subtracted by the counter, and the timing error of the divide pulse before and after the stop can be eliminated.

〔Example〕

 An embodiment of the present invention will be described below with reference to FIG.

In the figure, the output pulse of the encoder 2 directly connected to the DC motor 1 is shaped by the waveform shaping circuit 3 similarly to the divide pulse sending circuit according to the conventional method. For example, when it is rotated clockwise, it is shown in FIG. 3 (c). When the (+) pulse signal is rotated counterclockwise, the (-) pulse signal is directly input to the divide pulse transmission circuit as position information as shown in FIG. 3 (f). Divide pulsing circuit of ^2-4 counter 6 and the decoder 7 and the reset circuit 8
The comprises the output terminal QA of 2 ^quaternary counter 6, QB, QC, input terminal A of each QD decoder 7, B, C, is connected to the D.

For example, when the DC motor 1 rotates clockwise,
If the output pulse from the waveform shaping circuit 3 is a pulse signal in the (+) direction, the output pulse from the waveform shaping circuit 3 when the DC motor 1 rotates in the counterclockwise direction is a pulse signal in the (-) direction. By inputting these into the up terminal 62 or the down terminal 63 of the counter 6, the calculation of the addition and subtraction of the pulse number is performed. When the binary code added and subtracted and output from the counter 6 matches the binary code preset in the decoder 7, the decoder 7 outputs a pulse signal.

It is possible to directly output the pulse signal output from the decoder 7 to the outside and reset the counter 6 with the pulse signal output from the decoder 7. However, in the asynchronous counter, the timing of inputting the reset signal is early. If too much, it may be locked in the reset state and the subsequent counting may be inaccurate.

Therefore, the reset circuit 8 is composed of a monostable multivibrator (hereinafter referred to as a monostable multi) 81 and a NAND circuit 82 in order to obtain the time difference between the output of the pulse signal from the decoder 7 and the input of the reset signal to the counter 6. The NOR circuit 8 includes a pulse signal output section and a reset signal output section including a monostable multi 83 and a NOR circuit 84.
The reset signal output from 4 is input to the reset terminal 61 of the counter 6. When the pulse signal is output from the decoder 7, the output level of the monostable multi 81 is inverted, the pulse signal is output to the outside via the NAND circuit 82, the output level of the monostable multi 83 is inverted, and the counter 6 is The binary code output from the counter is reset and reset to 0.

Therefore, even if a pulse signal is output from the encoder until the DC pulse motor stopped halfway rotates in the opposite direction and is restored by restarting, the divide pulse transmission circuit according to the present invention will generate a divide pulse. The timing error can be eliminated.

〔The invention's effect〕

As described above, according to the present invention, it is possible to provide a pattern recognition device having a function of absorbing the timing error of the pulse signal before and after the stop, which occurs when the electric motor is stopped midway and restarted.

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of a divide pulse transmitting circuit according to the present invention, FIG. 2 is a circuit diagram showing an example of a conventional system, and FIG. 3 is a time chart showing an output signal waveform. In the figure, 1 is a DC motor, 2 is an encoder, 3 is a waveform shaping circuit, 6 is an up / down counter, 7 is a decoder, 8 is a reset circuit, 61 is a reset terminal, 62 is an up terminal, 63 is a down terminal, 81, 83 Is a monostable multi, 82 is a NAND circuit, 84 is a NOR circuit, QA, QB, QC and QD are counter output terminals, and A, B, C and D are decoder input terminals.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-58-146911 (JP, A) JP-A-54-93551 (JP, A) Practical application Sho-58-11340 (JP, U)

Claims (1)

[Claims] 1. An encoder (2) directly connected to a DC motor (1)
Waveform shaping circuit (3) that shapes the output pulse of, an up-down counter (6) that counts the input pulse and outputs a binary code, and if the binary code matches the preset code, the external circuit A decoder (7) that outputs a divide pulse, and a reset circuit (8) that has a monostable multi (83) and that uses the divide pulse to reset the up-down counter (6) are provided. The output pulse from the waveform shaping circuit (3) when (1) rotates in the forward direction
The output pulse from the waveform shaping circuit (3) when the DC motor (1) rotates in the reverse direction is input to the up terminal (62) of the (6), and the down terminal of the up / down counter (6). A divide pulse sending circuit characterized by adding or subtracting the number of pulses by inputting to (63).