JPH0613856A - Comparator circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To increase the speed of a comparator circuit with hysteresis characteristics. A non-inverting input terminal of a _first differential amplifier circuit A ₁ is connected to a _first signal input terminal IN ₁ , and an inverting input terminal thereof is connected to a _second signal input terminal IN ₂ . First differential amplifier circuit A ₁
Is connected to the non-inverting input terminal of the output circuit O _{1, and} the in-phase output terminal is connected to the inverting input terminal of the output circuit O ₁ . The in-phase output terminal of the output circuit O ₁ is connected to the first signal output terminal OUT ₁ and the non-inverting input terminal of the second differential amplifier circuit A ₂ , and the anti-phase output terminal is the second output terminal. The second differential amplifier circuit A connected to OUT ₂
Connect to the inverting input terminal of ₂ . The output amplitude width of the second differential amplifier circuit is set smaller than the output amplitude of the first differential amplifier circuit. The in-phase output terminal of the second differential amplifier circuit A ₂ is connected to the non-inverting input terminal of the output circuit O ₁ , and the anti-phase output terminal is connected to the inverting input terminal of the output circuit O ₁ .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparator circuit for comparing analog voltages, and more particularly to a comparator circuit in which an output voltage changes with a hysteresis characteristic in response to a change in input voltage.

[0002]

2. Description of the Related Art Comparator circuits used in the field of optical communication are required to have both high speed operation and hysteresis.

As shown in FIG. 9A, a conventional comparator circuit with hysteresis used in this type of field has two signal input terminals IN ₁₁ and IN ₁₂ and a signal output terminal OUT. Two differential amplifier circuits A ₁₁ , A ₁₂ and resistor R
11 are arranged. That is, the front stage differential amplifier circuit A
The non-inverting input terminal ₁₁ (+) of the first signal input terminal IN ₁₁
Directly, and the inverting input terminal (-) is connected to the second signal input terminal I
It is connected to N ₁₂ via a resistor R ₁₁ . The in-phase output terminal of the preceding differential amplifier circuit A ₁₁ is connected to the non-inverting input terminal of the following differential amplifier circuit A ₁₂ , and the anti-phase output terminal is connected to the inverting input terminal of the following differential amplifier circuit A ₁₂ . . The in-phase output terminal of the post-stage differential amplifier circuit A ₁₂ is connected to the signal output terminal OUT, and a signal indicating the comparison result is output terminal OU.
Obtained by T.

The negative phase output terminal of the rear differential amplifier circuit A ₁₂ is connected to the inverting input terminal of the front differential amplifier circuit A ₁₁ ,
As a result, the hysteresis operation is performed. That is, the hysteresis width ΔV is R11 × (output current amplitude of the post-stage differential amplifier circuit A ₁₂ ).

Specifically, such a conventional comparator circuit has a circuit configuration as shown in FIG. 9B, for example. That is, the first signal input terminal IN ₁₁ is connected to the first NPN
It is connected to the base of the transistor Q ₁₁ , and the second signal input terminal IN ₁₂ is connected to the base of the second NPN transistor Q ₁₂ via the resistor R ₁₁ . These first and second
The emitters of the transistors are connected to each other, and the interconnection point is connected to the ground line GND via the constant current source I ₁₁ . The collector of the first transistor Q ₁₁ is connected to the power supply line V _CC via the load resistor R _12A , and
It is connected to the base of the third NPN transistor Q ₁₃ . Similarly, the collector of the second transistor Q ₁₂ is connected to the power supply line V _CC via the load resistor R _12B and is also connected to the base of the fourth NPN transistor Q ₁₄ .

The collector of the third transistor Q ₁₃ is connected to the power supply line V _CC , and the emitter is the diode D.
_It is connected to the ground line GND via _11A and the constant current source I _12A , similarly, the collector of the fourth transistor Q ₁₄ is connected to the power supply line V _CC , and the emitter thereof is the diode D.
It is connected to the ground line GND through _11B and the constant current source I _12B .

The connection point between the diode D _11A and the constant current source I _12A is connected to the base of the fifth NPN transistor Q ₁₅ , and the connection point between the diode D _11B and the constant current source I _12B is the sixth.
Connected to the base of the NPN transistor Q ₁₆ .
The emitters of the fifth and sixth transistors are connected to each other, and the interconnection point is connected to the ground line GND via the constant current source I ₁₃ . The collector of the fifth transistor Q ₁₅ is connected to the second signal input terminal IN ₁₂
The collector of the sixth transistor Q ₁₆ has a load resistor R _12C.
It is connected to a power supply line V _CC via is connected to the signal output terminal OUT.

In the comparator circuit having such a circuit configuration, the NPN transistor is used, the PNP transistor is not used, and the transistor is used in a non-saturated state, so that it is relatively fast. The hysteresis width is R ₁₁ × I ₁₃ .

[0009]

However, in the conventional comparator circuit as described above, the feedback is applied from the output to the second signal input terminal IN ₁₂ of the two signal input terminals through the resistor R ₁₁ . , There are the following problems. (1) The input impedance of the second signal input terminal IN ₁₂ is low. (2) Characteristics such as hysteresis width change depending on the impedance of the circuit connected to the second signal input terminal IN ₁₂ . (3) Since the impedance of the second signal input terminal IN ₁₂ changes due to the hysteresis operation, the hysteresis operation affects the signal source. (4) Since the first signal input terminal IN ₁₁ and the second signal input terminal IN ₁₂ have different impedances, it is difficult to use for differential signals. Further, when a small hysteresis width is required, it is necessary to reduce the resistance R ₁₁ or the current I ₁₃ ,
Then, the following problems will occur. (5) If the resistance R ₁₁ is reduced, the problems (1) to (4) described above are increased. (6) If the current I ₁₃ is reduced, high speed operation becomes difficult. The present invention has been made in view of the above points, and an object of the present invention is to provide (1) a comparator circuit with hysteresis that enables high-speed operation.

Further, according to the present invention, (2) the input impedances of the two inputs can be equalized so that they can be used with a differential signal, and (3) the input impedance is prevented from changing due to the hysteresis operation. (4) An object of the present invention is to provide a comparator circuit with hysteresis capable of (4) having a circuit configuration suitable for relatively small hysteresis.

[0011]

In order to achieve the above object, a comparator circuit according to the present invention comprises a signal input terminal for receiving two signals to be compared and an input terminal connected to the signal input terminal. A first differential amplifier circuit having, a signal output terminal connected to an output terminal of the first differential amplifier circuit for outputting a signal indicating a comparison result, and an input terminal connected to the signal output terminal And an output terminal connected to the output terminal of the first differential amplifier circuit,
A second differential amplifier circuit having an output amplitude smaller than the output amplitude of the first differential amplifier circuit.

[0012]

That is, in the comparator circuit of the present invention, two differential amplifier circuits are used, and the output of the first differential amplifier circuit and the second differential amplifier circuit are used.
Of the first differential amplifier circuit by forming a positive feedback loop by connecting the output terminals of the differential amplifier circuit and connecting the input terminal of the second differential amplifier circuit to the signal output terminal. The input signal from the signal input terminal is added to the input terminal. Here, if the output amplitudes of the first and second differential amplifier circuits are the same, the output is fixed,
Since it does not operate as a comparator, the output amplitude of the second differential amplifier circuit is set smaller than the output amplitude of the first differential amplifier circuit.

Since the first and second differential amplifier circuits can be constructed by using NPN transistors and can be used without being saturated,
Moreover, since the positive feedback loop does not pass through the first differential amplifier circuit, high speed operation can be enabled.

Further, since the signal input terminal is separated from the hysteresis loop, the input impedances of the two inputs can be made equal so that they can be used for differential signals, and the input impedance does not change due to the hysteresis operation. Can be Further, since the signal is amplified by the first differential amplifier circuit before the hysteresis loop, the circuit configuration suitable for a relatively small hysteresis can be obtained.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1A is a diagram showing a circuit configuration of a first embodiment of the present invention.

The first differential amplifier circuit comprises transistors Q ₁ and Q ₂ , a load resistance _RL , and a constant current source I ₁ , and the second differential amplifier circuit includes transistors Q ₃ and Q ₄ ,
It is composed of a load resistance R _L and a constant current source I ₂ . The load resistance R _L is shared by the two differential amplifier circuits.

That is, the first signal input terminal IN ₁ is connected to the base of the _first NPN transistor Q ₁ , and the second signal input terminal IN ₂ is connected to the base of the _second NPN transistor Q ₂ . . The emitters of the first and second transistors are connected to each other, and the interconnection point is connected to the ground line GND via the constant current source I ₁ . The collector of the first transistor Q ₁ is connected to the power supply line V _CC via the load resistance R _L and is also connected to the second signal output terminal OUT ₂ . Similarly, the collector of the second transistor Q ₂ is connected to the power supply line V _CC via the load resistor R _L and the first signal output terminal O
It is connected to UT ₁ .

The second signal output terminal OUT ₂ has a third terminal
Is connected to the base of the NPN transistor Q ₃ , and similarly, the base of the fourth NPN transistor Q ₄ is connected to the first signal output terminal OUT ₁ . The emitters of the third and fourth transistors are connected to each other, and the interconnection point is connected to the ground line GND via the constant current source I ₂ . The collector of the third transistor Q ₃ is connected to the collector of the second transistor Q ₂ and
The collector of the transistor Q ₂ is connected to the collector of the first transistor Q ₁ .

In order to operate this circuit as a comparator, it is necessary to set the output amplitude width of the second differential amplifier circuit smaller than the output amplitude of the first differential amplifier circuit. The two constant current sources are set so that I ₁ > I ₂ .

In order to perform the hysteresis operation,
It is necessary to make the loop gain of the positive feedback loop larger than “1”, and the condition is (I _{2 RL} / 2V _T )> 1 (where V _T = kT /
q).

Although hysteresis is not required, if a high gain, high speed comparator is required, it can be easily realized by setting this loop gain to "1" or less.

The hysteresis width ΔV is the input voltage when the gain of the positive feedback loop formed by the second differential amplifier circuit exceeds "1" by applying the input signal to the first differential amplifier circuit. So, using a small-signal model and a first-order approximation,

[0023]

[Equation 1]

It is Since the hysteresis width ΔV is proportional to V _T, it has a temperature coefficient, but by giving I ₂ / I ₁ a temperature coefficient, the temperature coefficient can be set to 0 or designed to have a desired temperature characteristic.

FIG. 1B is a diagram showing the configuration of the second embodiment of the present invention. In this embodiment, the output circuit O _{1 is connected} to the common output terminal of the first and second differential amplifier circuits A ₁ and A _2.
Is connected, and the positive feedback is applied to the second differential amplifier circuit A ₂ by the output of the output circuit O ₁ .

That is, the non-inverting input terminal (+) of the first differential amplifier circuit A ₁ is connected to the first signal input terminal IN ₁ , and the inverting input terminal (-) is connected to the second signal input terminal IN ₂ . It is connected. The in-phase output terminal of the first differential amplifier circuit A ₁ is connected to the non-inverting input terminal of the output circuit O ₁ , and the anti-phase output terminal is connected to the inverting input terminal of the output circuit O ₁ . The in-phase output terminal of the output circuit O ₁ is the first signal output terminal OU.
The second differential amplifier circuit is connected to T ₁ and is also connected to the non-inverting input terminal of the second differential amplifier circuit A ₂ , and the negative phase output terminal is connected to the _second output terminal OUT _2. A
It is connected to the inverting input terminal of ₂ . And this second
The in-phase output terminal of the differential amplifier circuit A ₂ the output circuit O ₁
Of the output circuit O ₁ is connected to the non-inverting input terminal of the output circuit O ₁ .

The comparator circuit having such a structure can be realized, for example, by the circuit structure shown in FIG. That is, the first signal input terminal IN ₁ is connected to the base of the _first NPN transistor Q ₁ , and the second signal input terminal IN ₂ is connected to the base of the _second NPN transistor Q ₂ . The emitters of these first and second transistors are connected to each other, and the interconnection point is connected to the ground line GND via the _first constant current source I ₁ . First
The collector of the transistor Q ₁ is connected to the power supply line V _CC via the load resistance R _L, and is also connected to the collector of the _fourth NPN transistor Q _{4 and} the base of the sixth NPN transistor Q ₆ , and similarly. , The collector of the second transistor Q ₂ is connected to the power supply line V _CC via the load resistor _RL , and the third NPN transistor Q 2 is connected.
It is connected to the collector of _{3 and} the base of the fifth NPN transistor Q ₅ .

The second signal output terminal OUT ₂ is connected to the base of the third transistor Q ₃ , and the first signal output terminal OUT ₁ is connected to the base of the fourth transistor Q ₄ . The emitters of the third and fourth transistors are connected to each other, and the interconnection point is connected to the ground line GND via the _second constant current source I ₂ .

The collector of the fifth transistor Q ₅ is connected to the power supply line V _CC , and the emitter is connected to the ground line GND via the _third constant current source I ₃ . Similarly, the collector of the sixth transistor Q ₆ is connected to the power supply line V _CC , and the emitter is connected to the ground line GND via the _third constant current source I ₃ .

In order to operate this circuit as a comparator, the current values of the first and second constant current sources I ₁ and I ₂ are set so that I ₁ > I ₂ . Also, the third
The current value of the constant current source I ₃ is approximately the same as that of the _first constant current source I ₁ .

As described above, the emitter follower circuit is used as the output circuit O ₁ . Since the output impedance can be lowered by this emitter follower, the time constant determined by the product of the parasitic capacitance between the collector and the base of the transistors Q ₃ and Q ₄ and the output impedance can be made small, and by performing the level shift. Since V _CE of the transistors Q ₃ and Q ₄ can be increased, the comparator circuit having the above circuit configuration can operate at a higher speed than the conventional comparator circuit.

FIG. 2 is a simulation result of the circuit of FIG. 1C, showing the input / output characteristics. In this example, the hysteresis width ΔV is set to 50 mV, and the switching speed is as high as that of the differential amplifier circuit having no hysteresis. Further, the comparator circuit of FIG. 1B can also be configured as shown in FIGS. 3 and 4.

That is, in the circuit configuration of FIG. 3, the output amplitude of the _second differential amplifier circuit A ₂ is set to be smaller than the output amplitude of the first differential amplifier circuit A ₁ , so that the circuit shown in FIG. The load resistance R _L is divided into two load resistances R _L1 and R _L2 , and the collectors of the third and fourth transistors Q ₃ and Q ₄ are connected to the connection point of the load resistances R _L1 and R _L2 . . In such a circuit, the current values of the constant current sources I ₁ and I ₂ may be I ₁ = I ₂ or I ₂ / I ₁ may have a temperature coefficient. Also,
In this circuit, the signal output terminals OUT ₃ and OUT ₄ can also be used.

The circuit of FIG. 4 corresponds to the circuit of FIG. 1C with the emitter resistors R _E connected to the emitters of the first and second transistors Q ₁ and Q ₂ , respectively. In this circuit, the relationship between the constant current sources I ₁ and I ₂ is the same as that shown in FIG. With such a circuit configuration, the gain of the first differential amplifier circuit A ₁ can be reduced, so that a large hysteresis width ΔV can be obtained.
Can be easily realized by adopting such a circuit configuration when necessary. That is, the hysteresis width ΔV is

[0035]

[Equation 2] Becomes A diode or the like may be used instead of the emitter resistance R _E.

A differential amplifier circuit can also be used as the output circuit O ₁ of the comparator circuit of FIG. 1B. FIG. 5 shows a circuit configuration example in such a case. That is, the collector of the first transistor Q ₁ is
Collector of NPN transistor Q ₄ and fifth NPN
Similarly, the collector of the second transistor Q ₂ is connected to the base of the transistor Q ₅ , and the collector of the second transistor Q _{2 and} the collector of the third NPN transistor Q ₃ and the sixth NPN transistor Q _{6 are connected.}
Connected to the base of. The emitters of the fifth and sixth transistors are connected to each other, and the interconnection point is connected to the ground line GND via the _third constant current source I ₃ . The collector of the fifth transistor Q ₅ is
It is connected to the power supply line V _CC through the load resistor R _L2 and is also connected to the base of the _seventh NPN transistor Q ₇ . Similarly, the collector of the sixth transistor Q ₆ is connected to the power supply line V _CC via the load resistance R _L2 and is also connected to the base of the _eighth NPN transistor Q ₈ . The collectors of the seventh and eighth transistors Q ₇ and Q ₈ are connected to the power supply line V _CC , and the emitters thereof are connected to the ground line GND through the _fourth constant current source I ₄ . Others are (C) of FIG.
The circuit configuration is the same. As described above, by using the differential amplifier circuit as the output circuit O ₁ , the loop gain can be increased and stable operation can be performed.

Further, as shown in FIG. 2 as a simulation result of the circuit shown in FIG. 1C, this input / output characteristic has a combined characteristic of hysteresis operation and amplifier operation. When such an amplifier operation is unnecessary, the operation shown in FIG.
As shown in, by adding the amplifier A ₃ having a large gain on the output side, it is possible to realize a comparator circuit having only a hysteresis operation.

Further, in the above-described embodiment, the comparator circuit having at least two signal output terminals OUT ₁ and OUT ₂ has been described, but as shown in FIGS. 7 and 8, a comparator circuit having one signal output terminal OUT is used. You can also do it. In this case, the reference voltage signal is applied from the reference signal input terminal REF to the inverting input terminal of the _second differential amplifier circuit A ₂ .

[0039]

As described in detail above, according to the present invention,
(1) It is possible to provide a comparator circuit with hysteresis that enables high-speed operation.

Further, according to the present invention, (2) the input impedances of the two inputs can be made equal so that they can be used with a differential signal, and (3) the input impedance does not change due to the hysteresis operation. (4) It is possible to provide a comparator circuit with hysteresis that can be (4) a circuit configuration suitable for relatively small hysteresis.

[Brief description of drawings]

1A is a circuit configuration diagram of a comparator circuit according to a first embodiment of the present invention, FIG. 1B is a circuit diagram of a comparator circuit according to a second embodiment of the present invention, and FIG. It is a figure which shows the actual circuit structural example of the comparator circuit of 2nd Example.

FIG. 2 is an input / output characteristic diagram showing a simulation result in the circuit configuration of FIG.

FIG. 3 is a diagram showing another circuit configuration example of the comparator circuit according to the second embodiment.

FIG. 4 is a diagram showing still another circuit configuration example of the comparator circuit according to the second embodiment.

FIG. 5 is a diagram showing another circuit configuration example of the comparator circuit of the second embodiment.

FIG. 6 is a circuit diagram of a comparator circuit according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram of a comparator circuit according to a fourth embodiment of the present invention.

FIG. 8 is a circuit diagram of a comparator circuit according to a fifth embodiment of the present invention.

9A is a circuit diagram of a conventional comparator circuit, and FIG. 9B is a diagram showing an actual circuit configuration example of the comparator circuit of FIG.

[Explanation of symbols]

A ₁ , A ₂ ... Differential amplifier circuit, O ₁ ... Output circuit, IN ₁ ,
IN ₂ ... signal input terminal, OUT, OUT ₁ , OUT ₂ ...
Signal output terminals, I ₁ , I ₂ ... Constant current source.

Claims (1)

[Claims] 1. A first differential amplifier circuit having a signal input terminal for receiving two signals to be compared, an input terminal connected to the signal input terminal, and a first differential amplifier circuit. A signal output terminal connected to the output terminal for outputting a signal indicating the comparison result, an input terminal connected to the signal output terminal, and an output terminal connected to the output terminal of the first differential amplifier circuit. And a second differential amplifier circuit having an output amplitude smaller than the output amplitude of the first differential amplifier circuit, and a comparator circuit.