JPH061424B2 - System reset circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system reset circuit, and more particularly to a system reset circuit when powering off a system such as a microcomputer.

Generally, an integrated circuit (IC) does not operate normally when the power supply voltage drops. Especially in a microcomputer or the like, the program may run out of control due to a drop in the power supply voltage. For this reason, when the power supply voltage becomes lower than a predetermined value, a system reset circuit is provided which resets and instantaneously stops the operation to prevent malfunction or program runaway.

Prior Art FIG. 3 is a circuit diagram of an example of a conventional system reset circuit,
FIG. 4 shows a timing chart of the power supply voltage V _cc , the potential V _c , and the output voltage V _out of the output terminal in FIG. 3, respectively.

When the power is turned on at time t ₁ , the power supply voltage V _cc gradually rises, and when V _cc becomes equal to V _S1 determined by the zener diode D _Z and the resistors R ₁ and R ₂ at time t ₂ , the comparator (hereinafter The output of 1 (called comp) changes from H to L. As a result, the transistor Q ₃ which was on before is turned off, and the current of the constant current power supply I _g flowing as the collector current of the transistor Q ₃ is supplied to the capacitor C via the terminal 2 to charge the capacitor C. Along with this, the potential V _c gradually rises.

When the potential V _c becomes equal to the input voltage V _{s2 at} the non-inverting input terminal of comp3 at time t ₃ , the output of comp3 changes from H to L, and the transistor Q ₄ that was on until then is turned off. Where V _s2 is Is represented. When the transistor Q ₄ is turned off at time t ₃ , the output voltage V _out of the terminal 4 is pulled up by the resistor R _L and immediately becomes H.

At time t ₄ , when the power supply voltage V _cc instantaneously becomes V _s1 or less, the output of comp1 becomes H and the transistor Q ₃ is turned on. Therefore, the electric charge charged in the capacitor C passes through the collector of the transistor Q _3. Are discharged and the potential V
_c decreases. When the potential V _c becomes V _s2 or less at time t ₅ , the output of comp3 becomes H, the transistor Q ₄ is turned on, the output voltage V _out becomes L, and the device is reset (low reset).

When V _cc returns to the level of V _s1 or more at time t ₆ , the capacitor C is charged and the potential V becomes _equal to that when the power is turned on.
_c gradually increases, and when V _c = V _s2 at time t ₇ , the output voltage V _out of the terminal 4 immediately returns to H. Here, the operation recovery period t _d ′ from time t ₆ to t ₇ is the capacitance of the capacitor C,
V _s2 determined by the current of the constant current power source I _g and the resistances R ₃ and R ₄
And can be changed depending on how these settings are made.

Since the output voltage V _out of the terminal 4 immediately returns from L to H in this way, even when two microcomputers having different reset threshold voltages V _SH1 and V _SH2 are connected to the terminal 4,
The two microcomputers are released from reset at the times t ₃ and t ₇ and start operating.

The conventional circuit shown in FIG. 3 has the power supply voltage Vc at time t ₄ .
When c is V _s1 below, potential Vc is to decrease gradually due to discharge of the collector-emitter capacitance of the capacitor C and the transistor Q ₃ (indicated by a broken line), the reset of the device rather than the time t _4, the time t ₅ become. That is, time t ₄
~t until ₅ operation delay time △ next comp3, there is a problem that can not be subjected to reset instantly.

An object of the present invention is to provide a system reset circuit that can instantly reset the device when the power supply voltage drops.

Means for Solving the Problems The present invention relates to a first voltage comparison circuit that compares a power supply voltage with a first reference voltage and outputs a binary signal according to the comparison result, and the first voltage comparison circuit. A first transistor that is turned on and off according to an output level of the circuit, a first terminal is connected to one of power supply voltage terminals, and a second terminal is connected to an output of the first transistor. When the power supply voltage is equal to or lower than the first reference voltage according to ON / OFF of the first transistor, the power supply voltage is discharged, while the power supply voltage is charged with a predetermined time constant from the time when the power supply voltage reaches the first reference voltage. And a second voltage comparison circuit that compares the potential of the second terminal of the capacitor with a second reference voltage and outputs a binary signal according to the comparison result; The output voltage is turned on and off by the output of the voltage comparison circuit A system reset circuit for resetting the output voltage when the power supply voltage is lower than the first reference voltage, wherein the output of the first voltage comparison circuit and the output of the first voltage comparison circuit are provided. A gate circuit which is supplied with the output of the second voltage comparison circuit and supplies the output of the first voltage comparison circuit or the output of the second voltage comparison circuit to the input of the second transistor; A third device which is provided between a second terminal and one of the power supply voltage terminals, and which is turned on and off by the output of the first transistor to control charging and discharging of the capacitor.
And a transistor.

When the power supply voltage becomes lower than the first reference voltage, the output of the first voltage comparison circuit is inverted, and the output of the first voltage comparison circuit is supplied to the second transistor via the gate circuit to change the output voltage. At the same time as the instant reset, the capacitor is instantly discharged by the third transistor, the output of the second voltage comparison circuit is inverted with a slight delay to the output of the first voltage comparison circuit, and the second voltage is output via the gate circuit.
Is supplied to the transistor and holds the output voltage in the reset state.

When the power supply voltage reaches the first reference voltage, the output of the first voltage comparison circuit is restored, and in response to this, the third transistor is turned off and charging of the capacitor is started. The second terminal of the capacitor rises with a predetermined time constant in response to the charging, and when the second reference voltage is reached, the output of the second voltage comparison circuit also returns, and the first and second voltage comparison circuits are both After returning, the second transistor is controlled and the output voltage is output.

Thus, according to the system reset circuit of the present invention,
When the power supply voltage is lower than the first reference voltage, the comparison result of the first voltage comparison circuit is supplied to the second transistor via the gate circuit to instantly reset the output voltage,
When the power supply voltage rises above the first reference voltage, the comparison result of the second voltage comparison circuit is restored according to the time constant of the capacitor, and a predetermined time delay occurs after the power supply voltage rises above the first reference voltage. After that, the reset of the output voltage is released.

Therefore, the system can always be operated in a state where the power supply voltage is stable.

Embodiment FIG. 1 shows a circuit diagram of an embodiment of a system reset circuit according to the present invention. In FIG. 1, the same components as those in FIG. 3 are designated by the same reference numerals. FIG. 2 shows an operation timing chart of the circuit shown in FIG.

In FIG. 1, a diode D ₁ forming a gate circuit is connected between the output of the comp1 which is the first voltage comparison circuit and the base of the transistor Q ₄ which is the second transistor, and the second voltage comparison circuit is connected. A diode D ₂ forming a gate circuit is connected between the positive output terminal of comp3 and the base of the transistor Q ₄ . A resistor R ₅ is connected between the terminal 2 and the collector of the transistor Q ₃ which is the first transistor, and a transistor Q ₂ which is the third transistor is connected between the collector of the transistor Q ₃ and the terminal 5. To do. Further, a transistor Q ₁ is connected between the power supply terminal and the collector of the transistor Q ₃ , and its base is connected to the negative output terminal of comp3.

When the power is turned on at time t ₁ , the power supply voltage Vcc gradually rises, and at this time, the transistors Q ₂ and Q ₃ are turned on,
The diode D _{1 is} also turned on. Vcc at time t ₂
Becomes equal to V _s1 , the output of comp1 changes from H to L, whereby the diode D ₁ is turned off, the transistor Q ₃ is turned off, and the potential Vc gradually rises.

When the potential Vc becomes equal to V _s2 at time t ₃ , the output of comp3 changes from H to L, the diode D ₂ is turned off, the transistor Q ₄ is turned off, and the output voltage V _{out of the} terminal 4 is output.
Becomes H. At this time, the transistor Q ₁ is turned on, and the capacitor C is also charged through the transistor Q ₁ , so that the charging speed becomes faster and the potential Vc also rises quickly, improving the operational stability.

When the power supply voltage Vcc instantaneously becomes V _s1 or less at time t ₄ , the output of comp1 becomes H, the diode D ₁ is immediately turned on, the transistor Q ₄ is immediately turned on, and the output voltage V _{out of the} terminal 4 is output. Is L. Thus, c
Since the output H of omp1 is bypassed by the diode D ₁ and supplied to the transistor Q ₄ , the output voltage V _out can be instantly set to L, and the device can be instantly reset regardless of the operation delay of comp3.

On the other hand, it is also possible without providing a diode D ₁ between the base of the output transistor Q ₄ of comp1 obtain the substantially same effect. That is, at time t ₄ , the transistor Q ₃ is turned on, the capacitor C is discharged, and the resistor R 3
Due to the voltage drop across ₅ , the non-inverting input terminal voltage of comp3 becomes lower than V _s2 , which causes the output of comp3 to go high.
And the transistor Q ₄ is turned on, and the output voltage V _out
Becomes L at approximately the same time as time t ₄ .

Further, in the present invention, an effect different from the above effect can be obtained. When the transistor Q ₃ is turned on at time t ₄ , the capacitor C is discharged and the potential Vc drops. At this time, when the transistor Q ₃ is turned on, the transistor Q ₂ is also turned on, and the electric charge of the capacitor C can be discharged through the transistor Q ₂ as well, so that the discharging speed can be made faster than in the conventional example. When Vcc returns to the level of V _s1 or more at time t ₆ , the output of comp1 becomes L, the transistor Q ₃ turns off, the diode D ₁ turns off, the capacitor C is charged, and Vc gradually rises. Vc = at time t ₈
When it becomes V _s2 , the output voltage V _out of the terminal 4 returns to H.

In the present invention, as described above, the capacitor C from time t ₄
Because the discharge is quickly performed, never as recharging is performed while the capacitor C as in the conventional example is not Kira sufficiently discharged, the operation return interval time t ₆ ~t ₈ t
_d can be made constant at all times, that is, variations in the return of the device can be eliminated.

In the above embodiment, the output of comp1 and the transistor Q ₄
, And the gate between the output of comp3 and the base of the transistor Q ₄ are respectively composed of the diodes D ₁ and D _2. However, the present invention is not limited to this. Instead, another gate circuit may be used.

Further, the type of the transistors forming the circuit is not limited to the embodiment shown in FIG. 1, and the NPN type and the PNP type may be reversed.

Further, the H output can be similarly configured.

EFFECTS OF THE INVENTION According to the present invention, the output voltage can be instantly reset when the power supply voltage becomes equal to or lower than a predetermined value, and it is possible to reliably prevent malfunction or program runaway when particularly adapted to a system such as a microcomputer, Also, since the capacitor is quickly discharged by the third transistor when the power supply voltage becomes equal to or lower than the predetermined value, the operation recovery period t _d when the power supply voltage returns to the predetermined value or more can be made constant. It has the features that it can eliminate the variation of recovery and stabilize the operation.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is an operation timing chart of the circuit shown in FIG. 1, FIG. 3 is a conventional circuit diagram, and FIG. 4 is an operation of the circuit shown in FIG. It is a timing chart. 1, 3 ... Comparator, 4 ... Output terminal, 5 ... Power supply terminal,
D _1, D ₂ ... diodes, Q ₁ ~Q ₄ ... transistor, C ...
Capacitors, R ₁ ~R ₅ ... resistance, D _Z ... Zener diode, I _g ... constant-current power supply.

Claims (2)

[Claims] 1. A first voltage comparison circuit that compares a power supply voltage with a first reference voltage and outputs a binary signal in accordance with the comparison result, and a first voltage comparison circuit that outputs an output level of the first voltage comparison circuit. A first transistor that is turned on and off by a power supply voltage terminal, a first terminal is connected to one of the power supply voltage terminals, and a second terminal is connected to the output of the first transistor. A capacitor that is discharged when the power supply voltage is equal to or lower than the first reference voltage in response to turning off, and that starts charging with a predetermined time constant from the time when the power supply voltage reaches the first reference voltage. A second voltage comparison circuit that compares the potential of the second terminal of the capacitor with a second reference voltage and outputs a binary signal according to the comparison result; and an output of the second voltage comparison circuit. Second transistor that is turned on and off by the output voltage And a system reset circuit for resetting the output voltage when the power supply voltage drops below the first reference voltage, wherein the output of the first voltage comparison circuit and the second voltage comparison circuit are provided. And a gate circuit that supplies the output of the first voltage comparison circuit or the output of the second voltage comparison circuit to the input of the second transistor, the second terminal of the capacitor, and A third device that is provided between the power supply voltage terminal and one of the first and second transistors, and that turns on and off by the output of the first transistor and controls charge and discharge of the capacitor.
And a transistor, the power supply voltage is lower than the first reference voltage,
The output of the first voltage comparison circuit is inverted, and the output of the first voltage comparison circuit is supplied to the second transistor via the gate circuit to instantly reset the output voltage, and at the same time The transistor of No. 3 instantaneously discharges the capacitor, the output of the second voltage comparison circuit is inverted with a slight delay from the output of the first voltage comparison circuit, and the second transistor is inverted via the gate circuit. And a system reset circuit for holding the output voltage in a reset state. 2. A resistor is provided between the output of the first transistor and the second terminal of the capacitor, and the voltage across the resistor when the power supply voltage drops below the first reference voltage. The system reset circuit according to claim (1), characterized in that the voltage drop reduces the delay of the inversion of the output of the second voltage comparison circuit.