JPH0614267A - Display device - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a display device capable of realizing both multi-character type display support and high resolution display support for a display device for superimposing display of characters and figures on the screen. [Structure] An area specified by a character code M in the character data storage unit 4 is divided into a plurality of divided areas, and a specified division code C is stored in the address information storage unit 2. Further, the dot data storage unit 4 registers dot data representing one or more characters or figures in a plurality of divided areas as a whole.
The output control unit 3 controls the first control signal F and the second control signal R.
SEL is generated, and dot data representing one character or figure stored in the area designated by the character code M is stored in each of the plurality of areas at the same timing as when the dot data is supplied to the character signal generation unit 7. Control is performed so that dot data representing one character or figure is supplied to the character signal generation unit 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to a display device for superimposing characters and figures on a screen.

An on-screen display device is a display device for superimposing a character or a graphic (hereinafter collectively referred to as "character" in this specification) on a television screen by replacing it with a television image. It is called a controller (OSDC) and is installed in the television receiver to contribute to the high functionality of the television receiver. Such a display device (OSDC) is required to display more and more character types with the recent demand for higher functionality and higher image quality of television receivers.

[0003]

2. Description of the Related Art FIG. 22 is a block diagram showing a schematic configuration of an example of a conventional display device. The timing control unit 1 has a read counter and a raster counter, and this read counter generates a read address R for sequentially fetching data from the address information storage unit 2a composed of a random access memory (RAM). There is. For example, when the address information storage unit 2a has a structure of 5 digits × 2 lines, 0 → 1 → 2 → 3 → ... → 8 → 9 → 0 → 1 → 2 → ... cyclically from 0 to 9 It counts and supplies the count value as a read address R to the address information storage unit 2a.

A character code M is stored in the address information storage section 2a.
And character color information are set and read according to the read address R. Dot data storage unit (Read-only memory (ROM)
Character dot information is stored in 4a, and the character code M is an address indicating each character in the dot data storage unit 4a.
The font ROM area of the character is specified and the character is identified. The raster counter also generates the raster address L of the dot data storage unit 4a.

Here, FIG. 23 is an operation explanatory diagram of the dot data storage section 4a in FIG. Dot data storage unit 4
a is a character “0” to a character code M “00” to “03” read from the address information storage unit 3 as illustrated.
"4" is identified, and dot data corresponding to the raster address L from the timing control unit 1 is sequentially output row by row. In the example of FIG. 23, the raster address L is “0” to “3”.
Are sequentially and cyclically input, and the dot data storage unit 4a
The dot data of horizontal 5 dots shown by is output in parallel at once.

Returning to FIG. 22, the parallel output dot data DP from the dot data storage unit 4a is converted into serial data DS by the parallel / serial conversion unit 6 and output. Although not shown in the figure, the characters are superposed on the television screen by substituting the television signal.

By the way, the above-mentioned OSDC is generally composed of one-chip semiconductor, and the types of characters that can be displayed, the dot structure, and the semiconductor chip area have the following relationships.

Chip area ≧ P (number of character dots) × (character type) + (area of other circuit) (1) (P is a constant depending on the manufacturing process) That is, the dot configuration of all characters in one chip is In order to keep the chip area constant and to support multi-character type display, it is necessary to increase the (character type) and decrease the (character dot number) in equation (1), and the resolution is reduced.
On the other hand, in order to achieve high resolution display, the number of dots of a character is increased and the type of character is decreased to reduce the types of characters that can be displayed.

FIG. 24 is a diagram showing a font ROM area of an example of a conventional display device. FIG. 24A shows a case corresponding to multi-character type display, and FIG. 24B shows a case corresponding to high resolution display.

For example, the upper limit of the font ROM area in one chip is 10 dots in length × 1 in width as indicated by □ in FIG.
Considering 0 dots, in the case of multi-character type display (FIG. 7 (A)), the font ROM area in one chip is divided into 4 areas, and each area is 5 dots vertically x 5 dots horizontally.
The four characters of "1", "2", and "3" are formed, but the dot structure of one character has a low resolution of 5 dots vertically × 5 dots horizontally.
On the other hand, in the case of high resolution display in which the dot configuration of one character is 10 dots in the vertical direction × 10 dots in the horizontal direction ((B) in the same figure), only one character of “0” is configured in one chip.

[0011]

However, in order to realize both the multi-character type display and the high resolution display with the above-mentioned conventional display device, the constant P in the equation (1) must be made small, that is, the manufacturing process must be changed. This necessitates a change in the production plan, manufacturing equipment, etc., resulting in a large cost. Further, if the manufacturing process is not changed, there is a problem that the chip area increases and the device becomes large.

In view of the above points, the present invention provides a display device capable of supporting both multi-character type display and high resolution display without changing the manufacturing process of the device and without increasing the size of the device. To aim.

[0013]

The above problems can be solved by the following constitution.

That is, a dot data storage unit for storing dot data representing a character and / or a graphic and an address information storage for storing a character code designating an area corresponding to the character and / or the graphic in the dot data storage unit. Section and a read address for controlling the reading of the character code from the address information storage unit, and dot data according to the character and / or figure identified by the dot data storage unit based on the character code from the address information storage unit. A display provided with a timing control unit for generating a raster address for controlling the output timing of the image data, and a character signal generation unit for generating a character signal according to the output dot data from the dot data storage unit and supplying it to the external display means. In the device, divide the area specified by the character code of the dot data storage into multiple divided areas. The address data storage unit stores the classification code designated by the above, and the dot data storage unit is configured to register dot data representing one or more characters and / or graphics in a plurality of divided areas as a whole. A selection unit that selectively outputs the output dot data from the dot data storage unit from a plurality of divided regions of the dot data storage unit, and dot data that represents one character and / or figure stored in the region specified by the character code. In order to supply the dot data storage unit with dot data representing one character and / or graphic respectively stored in a plurality of divided areas at the same timing as the character signal generation unit, An output control unit that generates a first control signal that controls output timing and a second control signal that controls switching of the output of the selection unit. It is solved by.

[0015]

According to the present invention having the above-mentioned structure, the dot data representing one or more characters and / or graphics is dot-shaped in the entire divided area in which the area of the dot data storage portion designated by the character code is divided into a plurality of areas. The division code registered in the data storage unit and designating the plurality of divided areas is stored in the address information storage unit.

The output timing of the dot data storage section and the output of the selection section are controlled by the first and second control signals from the output control section, and stored in the area designated by the character code. Dot data representing one character and / or figure stored in each of the plurality of divided areas is supplied to the character signal generation unit at the same timing as when the dot data representing the character and / or graphic is supplied to the character signal generation unit. Acts to be supplied.

[0017]

FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, the same components as those in FIG. 22 are designated by the same reference numerals.

The above-mentioned character code M and character color information are set in the address information storage section 2 constituted by a RAM (sometimes referred to as VRAM (video random access memory)). It is read according to the read address R. Further, the classification code C, which is a feature of the present invention, is set in the address information storage unit 2.

FIG. 2 is a diagram for explaining the classification code. In the figure, the classification code C is composed of 3 bits of C0 to C2, and is an address indicating the font classification in the dot data storage unit (font ROM) 4 of FIG. It is also a code for specifying enlargement when reading data.

Returning to FIG. 1, the output control section 3 is composed of the logic circuits shown in FIGS. 3, 7, 9 and 11 below, and is the first control signal from the classification code C. The font ROM raster address F and the ROM select (RSEL) signal which is the second control signal are generated.

The dot data stored in the dot data storage unit 4 is output as parallel data via the selection unit 5. However, as will be described later in detail, the dot data storage unit 4 is selected according to the resolution required for the characters to be displayed. According to the classification code C and treated as an area of the number of characters of 2 or 4 characters, and the divided characters are automatically enlarged and displayed so that the font ROM raster addresses F and RS are displayed.
Data output is controlled by the EL signal.

The parallel data DP output from the selection unit 5 as described above is converted into serial data DS by the parallel / serial conversion unit 6 and then processed by the character signal generation means 7 to perform trimming, background processing, etc. Is generated and further combined with an analog video signal from the outside. This composite analog video signal is output to a television receiver (not shown), and superimposed characters are displayed on the television image.

Examples of the present invention will be specifically described below. FIG. 3 shows a vertical 1 × that forms a part of the output control unit 3.
FIG. 4 is a timing chart showing the operation of the vertical 1 × / 2 × circuit.

The vertical 1 × 2 × circuit 18 is composed of an enlargement designation signal generation circuit 11, a division designation signal generation circuit 15, a raster counter 16 and a selector 17, and the division codes C0 to C0.
Font ROM raster addresses F0 to F4 are generated from C2 and the horizontal synchronizing signal HSYNC (FIG. 4 (A)) and supplied to the font ROM4. The raster counter 16 is included in the timing control unit 1.

The division codes C0 to C2 correspond to the gate circuit 1
The division designation signal SITA is generated by inputting to the division designation signal generation circuit 15 composed of 2 and 13 and the OR circuit 14.
Each classification code is as shown in FIG. 2, and the classification code C
The output of the gate circuit 12 which inverts 1 and performs a logical product with the division codes C0 and C2 becomes high level in the case of FIG.

The classification code C2 is inverted and the classification code C1 is obtained.
The output of the gate circuit 13 which takes the logical product of and becomes high level in the cases of and in FIG. The classification designating signal SITA is obtained by taking the logical sum of these outputs by the OR circuit 14, and in the cases of and in FIG. 2, that is, when the font classification is "lower left", "lower right" and "left and right lower". High level.

The division codes C1 and C2 are input to the enlargement designation signal generation circuit 15 including the AND circuit 10 to be ANDed with each other to generate the enlargement designation signal V1H1. The enlargement designation signal V1H1 becomes high level only in the case of FIG. That is, the vertical enlargement designation is "1.
When it is "double", it is high level, and when it is "double", it is low level.

As the enlargement designation signal, the above-mentioned V1H1
There are the following two types. The enlargement designation signal V2H2 is obtained by inverting the division code C2, and the enlargement designation signal V2H1 is obtained by inverting the division code C1 and performing a logical product with C2. V2H2 is at a high level in the cases of to in FIG. 2, that is, at a high level when the vertical enlargement designation is "double" and the horizontal enlargement designation is "double". Also,
V2H1 is at a high level in the case of FIG. 2, that is, when the vertical enlargement designation is "double" and the horizontal enlargement designation is "1", it becomes a high level.

On the other hand, as shown in FIG. 4, the raster counter 16 divides the horizontal synchronizing signal HSYNC obtained by separating it from the composite video signal by 2, and divides L0 (FIG. 4B) into L0.
Is further divided by 2 to count L1 (FIG. 4 (C)), L1 is further divided by 2 and L2 (FIG. 4 (D)) is sequentially counted and output.
The bit count values L0 to L4 (raster address) are supplied to the selector 17.

The selector 17 is further provided with a classification designation signal SIT.
A is input, and L0 to L4 or L1 to L4 of these 5-bit inputs is input according to the enlargement designation signal V1H1.
And 5 bits of SITA are output as font ROM raster addresses F0 to F4. The font ROM raster addresses F0 to F4 are supplied to the dot data storage unit (font ROM) 4 of FIG. 1, and the font design (characters, figures, etc.) stored in the dot data storage unit 4 is supplied in accordance with the font ROM raster address. Dot data is read.

FIG. 5 is a diagram for explaining a TV (television) display image for the font ROM raster address. The TV display image of the font design for the output font ROM raster addresses F0 to F4 of the vertical 1 × 2 × circuit 18 of FIG. 4 will be described below with reference to FIG.

As an example, FIG. 5A shows a font design in which a conventional one-character area of a font ROM is vertically divided into two and the numbers "0" and "1" are vertically displayed over the whole area. , The output control unit 3 of FIG.
5 (B) or 5 according to the classification code C input to
As shown in (C) or FIG. 5 (D), dot data is output from the dot data storage unit 4 via the selection unit 5 so as to be displayed on the television screen, and a character signal corresponding to this dot data is converted into a television signal. It is replaced and is displayed superimposed on the television screen.

FIG. 5B shows the classification codes C0 = 1 and C1 =.
1 and C2 = 0, and at this time, the enlargement designation signal V1
H1 becomes high level as described above, and the font ROM raster address is F0 = L0, F1 = L1, F2 = L2.
The selector 17 of FIG. 4 is set so that F3 = L3 and F4 = L4.
Works. As a result, the TV display image has "0" at the top and "1" at the bottom as vertical 1 as shown in the font design.
It is displayed in double magnification.

Further, in FIG. 5C, the classification code C0 = 1,
In the case of C1 = 0 and C2 = 0, the enlargement designation signal V1H
1 becomes the low level as described above, and the font ROM raster address is F0 = L1, F1 = L2, F2 = L3, F.
Selector 1 in FIG. 4 so that 3 = L4 and F4 = SITA
7 works.

At this time, the division designating signal SITA = 0, the font ROM raster addresses F0 to F4 are set to 0 at the highest F4, and the vertical 1 × / double circuit 18 outputs them. As a result, as the TV display image, only "0" at the upper part of the font design is vertically doubled and displayed.

Further, FIG. 5D shows the classification code C0 = 1,
In the case of C1 = 0 and C2 = 1, the enlargement designation signal V1H
1 becomes a low level as in the case of FIG. 5C, and the font ROM raster address is F0 = L1, F1 = L2, F.
2 = L3, F3 = L4, F4 = SITA. The division designation signal SITA = 1, the font ROM raster addresses F0 to F4 are set to 1 at the highest F4, and are output from the vertical 1 × 2 × circuit 18 as illustrated. As a result,
As the TV display image, only the lower part "1" of the font design is vertically enlarged and displayed twice.

As described above, when the designation of enlargement of the division code shown in FIG. 2 is vertically doubled, the font design is divided into the upper and lower designs and vertically enlarged and displayed twice. , Classification code C (C0 to C3) as shown in FIG.
In response, the output control unit 3 outputs the font ROM raster address F (F0 to F4), and based on this, the font ROM (dot data storage unit) 4 supplies parallel dot data DP to the selection unit 5.

In the description of FIG. 5, the font ROM has a configuration of vertical 32 dots × horizontal 7 dots as shown by ◯, but in the present embodiment, the font ROM 4 is actually vertical 32 dots × vertical.
As shown in FIG. 6 shown below, the horizontal 24 dots are divided into left and right 12 dots each, and are output to the selection unit 5 from a bus line having a bus size of 12 bits.

FIG. 6 is a block diagram of a font ROM access circuit which is a main part of the device of the present invention.

The font ROM access circuit 9 comprises a dot data storage unit (font ROM) 4 and a selection unit 5.

The dot data storage unit 4 is the ROM as described above.
The character code M and the classification code C (C0 to C3) from the address data storage unit 2 and the raster address L from the timing control unit 1 are used to divide the image into 12 horizontal dots for each 2 minutes depending on the font design to be displayed. The left font data (dot data) and the right font data thus generated are output to the selection unit 5 by 12 bits each.

However, since the bus size of the ROM is generally 8 bits, it is considered that the circuit can be configured more easily by dividing the bus size into 8 bits.

As will be described below, the selection unit 5 switches to A or B according to the RSEL signal from the output control unit 3, and converts either the left or right font data from the 12-bit bus line to parallel-to-serial according to the classification code. Output to the unit 6.

FIG. 7 shows an RS forming a part of the output control unit 3.
FIG. 8 is a circuit diagram of the EL signal generation circuit, and FIG. 8 is a timing chart showing the operation of the RSEL signal generation circuit.

The RSEL signal generation circuit 19 includes a counter 2
6, AND circuits 24 and 25, a gate circuit 27, an OR circuit 28, and horizontal division decoding circuits 29 and 30, which generate a ROM select signal (RSEL) from the division codes C0 and C2 and the dot clock DCK, and select in FIG. Supply to part 5.

The division codes C0 and C2 are assigned to the gate circuit 20.
And horizontal timing decoding circuit 2 including timing circuit 21
9 and the horizontal division decode signal HID is generated. The division codes C0 and C2 are the same as those shown in FIG. 2, and the output of the gate circuit 20 which inverts C0 and C2 to take the respective logical products becomes the high level in the cases of and in FIG. 21 outputs HID in synchronization with the dot clock DCK, and when the font classification is "upper left" and "lower left", HID becomes high level.

Further, the division codes C0 and C2 are input to the horizontal division decoding circuit 30 including the gate circuit 22 and the timing circuit 23, and the horizontal division decoding signal MIG is generated. The output of the gate circuit 22 which inverts the division code C2 and obtains the logical product with the division code C0 becomes high level in the cases of and in FIG. 2, and the timing circuit 23 outputs MIG in synchronization with the dot clock DCK. That is, when the font classification is "upper right" and "lower right", MIG becomes high level.

The counter 26 supplies a Q output obtained by dividing the dot clock DCK (FIG. 8A) by 12 to the gate circuit 27. The gate circuit 27 uses the horizontal division decode signal HI.
Invert D and MIG and take the logical product with this Q output. The OR circuit 28 takes the logical sum of the outputs of the AND circuits 24 and 25 and the gate circuit 27, and outputs the RSEL signal (FIG. 8 (B)).
Output as.

Therefore, the RSEL signal is normally the one shown in FIG.
As shown at middle time t _{0 to} t ₁ , H → L → H every 12 dots
→ is repeated, whereby the left and right font data of the font ROM are alternately selected and output and taken in the parallel-serial conversion unit 6.

Further, the horizontal division decode signal HID (FIG. 8C) is generated as shown at times t _{1 to} t ₂ in FIG. 8 and the horizontal division decode signal MIG (FIG. 8C is shown as shown at times t _{2 to} t ₃ ). 8 (D)), only the left or right 12-dot data is selected and output, and the parallel-serial conversion unit 6
Is taken into.

The SLD signal generation circuit and SCK signal generation circuit shown below are included in the output control section 3 of FIG. 1, and generate a fetch signal and a clock and supply them to the parallel-serial conversion section 6.

FIG. 9 is a circuit diagram of the SLD signal generation circuit, FIG.
Reference numeral 0 is a timing chart showing the operation of the SLD signal generation circuit.

The SLD signal generation circuit 36 is composed of a shift register 35 having a well-known configuration including D-type flip-flops 31 and 32 and an inverter 33, and a coincidence circuit 34.
Capture signal SL from EL signal and dot clock DCK
D is generated and supplied to the parallel-serial conversion unit 6 in FIG.

The RSEL signal (FIG. 10 (B)) is the matching circuit 3
4 is supplied to one input of the shift register 3
After being delayed by 5 for one cycle of the dot clock DCK (FIG. 10A), it is supplied to the other input of the coincidence circuit 34. As a result, the fetch signal SLD (FIG. 10C) which is at the low level for one cycle of the dot clock DCK is obtained near the rising edge and the falling edge of the RSEL signal.

FIG. 11 is a circuit diagram of the SCK signal generation circuit, and FIG. 12 is a timing chart showing the operation of the SCK signal generation circuit.

The SCK signal generating circuit 37 is composed of the frequency dividing circuit 4
2, inverter 43, OR circuit 44, switch circuit 45
The parallel-serial conversion clock (SCK signal) is generated from the dot clock DCK and the horizontal division decoding signals HID and MIG, and is supplied to the parallel-serial conversion unit 6 in FIG.

The switch circuit 45 is composed of an AND circuit 46, a gate circuit 47 and an OR circuit 48, and the divide-by-2 circuit 42 is composed of D-type flip-flops 38 and 40 and inverters 39 and 41. Dot clock DC
K (FIG. 11 (A)) is frequency-divided into two by the frequency-dividing circuit 42 to be DCK (1/2) and supplied to the AND circuit 46. Further, the dot clock DCK is supplied to one input terminal of the gate circuit 47 via the inverters 41 and 43 in series.

The horizontal division decode signals HID and MIG are
The OR circuit 44 takes the respective logical ORs and supplies them to the switch circuit 45, and either the dot clock DCK of the normal cycle or the dot clock DCK (1/2) divided by 2 is output according to the output of the OR circuit 44. Is S from the switch circuit 45
It is generated and output as a CK signal (FIG. 11B).

That is, if both the horizontal division decode signal HID (FIG. 11C) and MIG (FIG. 11D) are low level, the output of the OR circuit 44 (low level) is input to the AND circuit 46. The output of the divided DCK (1/2) is prohibited. On the other hand, the output of the OR circuit 44 is inverted and set to the high level and input to the AND circuit 45. Therefore, the dot clock DCK input to the AND circuit 45 as described above is output via the AND circuit 45 and the OR circuit 48. It

Further, the horizontal division decode signals HID, MIG
If any of the above is high level, the output (high level) of the OR circuit 44 is inverted and input to the gate circuit 47, so that the output of the dot clock DCK from the gate circuit 47 is prohibited. At this time, one input of the AND circuit 46 is at a high level, and the dot clock DCK (1/2) divided by 2 is output via the AND circuit 46 and the OR circuit 48.

As described above, as shown in FIG.
The signal usually has the same cycle as the dot clock DCK,
When the horizontal division decode signal HID or MIG is generated, it is generated so as to have a period twice that of the dot clock DCK.

FIG. 13 is a diagram showing the configuration of the parallel-serial conversion unit 6, (A) is a block diagram, and (B) is a concrete circuit diagram of the main part.

In FIG. 13A, the parallel-serial conversion unit 6 has twelve shift registers 49 ₁ , 49 ₂ , 49 ₃ , in which the Q1 output of the previous stage is cascaded to the D1 input of the next stage.
..., and it is composed of 49 _12. The D1 input of the first-stage shift register 49 ₁ is grounded.

A capture signal (SLD signal) from the SLD signal generation circuit 36 (FIG. 9) is input to each conversion input S, and the SCK signal generation circuit 37 (FIG. 1 is input to each clock input.
The parallel-to-serial conversion clock (SCK signal) from 1) is input, and the parallel data DP (D1 to D12) from the font ROM 4 input to each D2 input.
Is converted to serial data DS and is output from the Q1 output of the shift register 49 ₁₂ at the final stage.

Each shift register 49n (n is an integer from 1 to 12) has an AND circuit 5n as shown in FIG.
0, gate circuit 51, NOR circuit 52, inverter 53,
54 and 56, and D-type flip-flops 55 and 57.

FIG. 14 is a timing chart (No. 1) showing the operation of the parallel / serial conversion unit 6, showing the parallel / serial conversion timing in the normal (no horizontal division) case. Further, FIG. 15 shows the parallel-serial conversion unit 6
3 is a timing chart (No. 2) showing the operation of the above, showing the parallel-serial conversion timing in the case of horizontal division.

The parallel-serial conversion clock (SCK signal) of FIG. 14B has a constant cycle which is the same as that of the dot clock DCK as described with reference to FIG. In addition, the capture signal (SLD signal) in FIG.
As described with reference to FIG. 0, one cycle of dot clock DCK (that is, S) from the rising edge and the falling edge of the RSEL signal not shown in FIG.
It is kept at a low level for one CK signal cycle).

For example, at time t ₀ in FIG. 14, RSE
L signal becomes high level and SLD signal becomes SCK signal 1
When it becomes low level during the cycle, font ROM4
The left font data D1 to D12 (FIG. 14A) which is 12-bit parallel data DP from
D1, D2, ..., in synchronization with the rising edge of the K signal
It is converted into serial data bit by bit in the order of D12 and output.

At time t ₁ in the figure, when the RSEL signal is inverted and the SLD signal is again at the low level for one cycle of the SCK signal, the right font data d1 to d which is the 12-bit parallel data DP from the font ROM4.
12 (FIG. 14 (A)) comes in, and is converted into serial data bit by bit in the order of d1, d2, ..., D12 in synchronization with the rising edge of the SCK signal and output.

In this way, the data for 24 dots in the horizontal direction is converted into the 24-bit serial data DS (FIG. 14 (D)) and output, and hereinafter, the data for 32 dots in the vertical direction is serial data of 24-bit. Is converted to and output. Therefore, in the above case, the magnification of the display on the television screen is set to 1 × in the horizontal direction.

Next, with reference to FIG. 15, for example, a horizontal division decode signal HID (not shown in the figure) indicates time t _0.
15B, the parallel-serial conversion clock (SCK signal) in FIG. 15B has a period twice that of the dot clock DCK as described with reference to FIG. Also, R
The SEL signal (not shown) is the HID as described in FIG.
High level is synchronized with.

Therefore, the SLD signal of FIG. 15C becomes low level for 1/2 cycle of the SCK signal from the time t _{0 in} FIG. 15, and the left font which is the 12-bit parallel data DP from the font ROM. Data d1 to d
12 (FIG. 15 (A)) comes in, and is converted into serial data DS (FIG. 15 (D)) bit by bit in the order of d1, d2, ..., d12 in synchronization with the rising edge of the SCK signal and is output. .

Thus, every 12 cycles of the SCK signal,
Font RO equivalent to 12 dots out of 24 horizontal dots
12-bit parallel font data from the left half area of M4 is converted into 12-bit serial data and output.
It is converted to bit serial data and output.

At this time, FIG. 1 in the case of normal (no horizontal division)
As is clear from 4 (D), the serial data DS is converted and output bit by bit in a cycle twice as long as the dot clock DCK, and the conversion speed is twice as high as when the enlargement designation is horizontal one time. Therefore, the display on the television screen is enlarged twice in the horizontal direction.

Next, FIG. 16 shows the font RO described above.
It is a figure which shows the M area division method, (A) shows a division code, (B), (C), (D) shows the font ROM area division corresponding to each division code.

The classification code C (FIG. 16 (A)) set in the address information storage unit 2 is, as described with reference to FIG. 2, one character font ROM area (vertical 32 dots × horizontal 24 dots) as shown in FIG. It is a 3-bit code that is designated in 7 ways as shown in B) to (D).

For example, when registering a low-resolution font design such as numbers or alphabets, "upper left" shown by "upper left", "upper right" shown by "lower left" shown by ". It is divided into four "lower right" areas (FIG. 16B) and registered in the font ROM area for one character.

When registering medium-resolution font designs such as hiragana, katakana, and simple kanji with a small number of strokes such as "mountain" and "river", they are respectively indicated according to the classification code of. The character RO is divided into two areas (Fig. 16 (C)) divided into "left and right lower" areas indicated by "left and right upper".
Register in the M area.

Furthermore, when registering a high-resolution font design of a complicated Chinese character with a large number of strokes, such as "complex" or "miscellaneous", the "left, right, top, bottom" indicated by is not divided according to the classification code of 1 character font ROM area whole area (Fig. 1
6 (D)).

Then, the font data (dot data) is read from the font ROM 4 and enlarged and displayed at the timings described above in accordance with the classification code C in each case, thereby displaying characters from low resolution to high resolution on the television screen. It can be discriminated as a natural shape, and the limited font ROM area can be effectively used.

Therefore, even when the OSDC is composed of a semiconductor, it is possible to realize both multi-character type display and high resolution display without changing the manufacturing process and without increasing the size of the device.

By the way, in the address information storage unit 2 of the present embodiment, the conventional character code unit for designating each character in the unit of the font ROM area of one character (32 dots vertically × 24 dots horizontally) is described above. The division code section and the section will be set.

FIG. 17 is a diagram showing the correspondence between the VROM (address information storage unit 2) and the dot data storage unit 4 in the font ROM section. In the figure, the character code portion 80 of the value of VRAM is the 4-bit character code “000
0 "," 0001 "," 0101 "," 1010 ", etc., respectively, font ROM areas 82, 83 for one character,
84 and 85 are designated.

Then, the classification code section 81 replaces each font ROM area of one character designated by the character code with
3-bit classification code “000”, “011”, “10”
As shown in FIG. 16, it is divided into seven types and designated by “0”, “110”, and the like.

Next, the TV display image of the font design according to the present embodiment configured as described above will be described. 18 to 20 show a TV as an example of font design.
It is a figure which shows a display image.

FIG. 18A shows a font design in which a circle "○" is displayed in the font ROM area for one character. FIG. 16B shows a TV display image when the enlargement designation is twice the height and twice the width. As described above with reference to FIGS. 1 and 16, when the division code is “000” (), the font division is “ "Upper left", and a quarter of the circumference of the upper left portion of the circle in FIG. 18A is vertically doubled and horizontally doubled to be displayed on the television screen.

The classification code is "001" (), "01"
In the case of "0" () and "011" (), 1/4 of the circumference of the "upper right", "lower left", and "lower right" portions is also twice the vertical and 2 horizontal depending on the font classification. It is magnified twice and displayed on the television screen.

FIG. 9C shows a TV display image when the enlargement designation is twice the length and one time the width, and the division code is "10".
18 ”, the font classification is“ upper left and right ”, and FIG.
The semicircle above the circle in (A) is vertically doubled and displayed on the television screen. Also, the classification code is "101"
In the case of (), the font classification is "left bottom right", and
The lower half circle of the circle of 8 (A) is vertically doubled and displayed on the television screen.

FIG. 9D shows a TV display image when the enlargement designation is 1 time in the vertical direction and 1 time in the horizontal direction, and the division code is "11".
0 ”() indicates that the font classification is“ left, right, top and bottom ”.
The entire 8 (A) circle is displayed on the television screen without being expanded vertically and horizontally.

FIG. 19A shows each character code "000."
"0", "0001", ..., "0101", ..., "101"
Each one-letter font R shown in FIG. 17 designated by "0"
An example in which various font designs are registered in the OM areas 82, 83, ..., 84 ,.

In the font ROM areas 82 and 83, low resolution font designs "0", "1", "2",
“3” and “4”, “5”, “6”, “7”, medium resolution font designs “A” and “I” in the font ROM area 84, and high resolution font design in the font ROM area 85. The font design "Kan" is registered as shown.

With respect to these font designs, when the dot data is read from the font ROM 4 by the division code of each area shown by hatching in the drawing, that is, "000", "011", "100", "110" in order,
The TV display image is as shown in FIG. That is, as described above, in the case of low resolution, the font designs “0” and “7” are enlarged and displayed twice in the vertical and horizontal directions,
In the case of medium resolution, the font design “A” is vertically enlarged to be doubled and displayed, and in the case of high resolution, the font design “Kan” is not enlarged and displayed as it is.

As described above, when the classification code is correctly set according to the resolution of the font design, low-resolution to high-resolution characters such as "07 Akan" shown in the figure have a natural shape on the television screen. It is displayed in a distinguishable manner, and the font ROM 4 can be used efficiently.

Next, in FIG. 20A, as in FIG. 19A, the font ROM areas 82, 83, ...
84, ..., 85 show other examples in which various font designs are registered. The font ROM area 82 has medium resolution font designs "A" and "I", the font ROM area 83 has high resolution font design "Kan", and the font ROM areas 84 and 85 have low resolution font design "A". "0", "1", "2",
“3” and “4”, “5”, “6”, “7” are registered as illustrated. In this case, the division codes are mismatched with respect to these font designs and are not used correctly, and the division codes of each area indicated by hatching in the figure, that is, “000”, “011”, “10” in order.
When the dot data is read from the font ROM by "0" and "110", the TV display image is as shown in FIG. In this way, if the classification code is used incorrectly, the font design cannot be identified on the television screen.

Next, the detailed structure of an example of the OSDC to which the device of the present invention is applied will be described with reference to FIG. In the figure, an OSDC 60 is a serial interface unit 61, a dot clock generation unit 62, a color burst clock generation unit 63, an NTSC / PAL timing generation unit 64, a memory sequencer unit 65, a display memory 66, an address buffer 67, a parallel-serial conversion. A character modification unit 68, an analog video signal generation unit 69, and a font ROM 70.
Consists of.

The serial interface unit 61 receives the command and data input by 8-bit serial transfer, analyzes the command by the command decoder, and sorts the data. The dot clock generator 62 oscillates and outputs a dot clock (DCK) that is a basic clock of the memory timing system based on the oscillation signal EX from the external oscillator. The color burst clock generator 63 generates a repeating frequency of 4F _SC (where F _SC is a color subcarrier frequency), which is the basic clock of the synchronization signal system, based on the oscillation signal EXSC from the external oscillator.

NTSC / PAL timing generator 64
Is a composite sync signal input from an NTSC or PAL color video signal.
It generates synchronizing signals such as horizontal synchronizing signals and vertical synchronizing signals that comply with the AL method.

The memory sequencer section 65 generates a timing control signal for the display operation and controls the operation of each block. The memory sequencer block 65 corresponds to the timing control unit 1 and the output control unit 3 in FIG. 1, and has the raster counter, the read counter, and the logic circuit described above.

The display memory 66 is a 24.times.12.times.19 bit VRAM, which corresponds to the address information storage unit 2 and has a 12-bit character code and a 3-bit character color together with the 3-bit classification code which is a feature of the present invention. A 3-bit character background color and a 1-bit character attribute are stored.

The address buffer 67 outputs an address signal and a read signal to an external font ROM 70 (corresponding to the dot data storage unit 4 in FIG. 1), and also performs tristate control from the TSC terminal of the font ROM 70.

The parallel / serial conversion / character modification unit 68 includes the selection unit 5 and the parallel / serial conversion unit 6 of FIG.
After the parallel-serial conversion is performed on the dot data from the external font ROM 70 as described above, the trimming, the background, and the like are processed to generate a character signal. The character signal generator 7 of FIG. 1 is constituted by the character modifier of the parallel / serial conversion / character modifier 68 and the following analog video signal generator 69.

The analog video signal generator 69 synthesizes the externally input analog video signals VIN, Y / CI and the character signal, or internally synthesizes the generated analog video signal and the character signal. The synthesized analog video signals VOUT, Y / CO thus obtained are output to a television receiver (not shown) to display the superimposed characters on the television image.

In the above embodiment, the enlargement designation is set in three ways according to the resolution of the font design (three ways of setting low resolution, medium resolution, and high resolution). It may be configured to set four or more ways and set the enlargement designation according to this.

[0104]

As described above, according to the present invention, the dot data representing one character and / or figure stored in the area of the dot data storage section designated by the character code is supplied to the character signal generation section. At the same timing as the above, the dot data representing one character and / or figure stored in each of the plurality of areas designated by the division code is supplied to the character signal generation section, thereby the dot data storage section It is possible to store the dot data by dividing this area into multiple character areas and store it as a character area.Also, it can be output so that it can be enlarged and displayed as a normal character size. There is a feature that many kinds of characters and / or graphics can be displayed in high resolution without increasing the size and without changing the manufacturing process.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram illustrating a classification code according to an embodiment of the present invention.

FIG. 3 is a circuit diagram of a vertical 1 × / 2 × circuit according to an embodiment of the present invention.

4 is a timing chart showing the operation of the vertical 1 × / 2 × circuit of FIG.

FIG. 5 is a diagram illustrating a TV display image for a font ROM raster address.

FIG. 6 is a block diagram of a font ROM access circuit.

FIG. 7 is a circuit diagram of an RSEL signal generation circuit according to an embodiment of the present invention.

8 is a timing chart showing an operation of the RSEL signal generation circuit of FIG.

FIG. 9 is a circuit diagram of an SLD signal generation circuit according to an embodiment of the present invention.

10 is a timing chart showing the operation of the SLD signal generation circuit of FIG.

FIG. 11 is a circuit diagram of an SCK signal generation circuit according to an embodiment of the present invention.

12 is a timing chart showing the operation of the SCK signal generation circuit of FIG.

13A and 13B are diagrams showing a configuration of a parallel-serial conversion unit according to an embodiment of the present invention, FIG. 13A is a block diagram, and FIG. 13B is a specific circuit diagram of a main part.

FIG. 14 is a timing chart (No. 1) showing the operation of the parallel / serial conversion unit in FIG.

FIG. 15 is a timing chart (No. 2) showing the operation of the parallel / serial conversion unit in FIG.

FIG. 16 is a diagram showing a font ROM area division method.

FIG. 17 is a diagram showing correspondence between VRAM and font ROM classification.

FIG. 18 is a diagram (part 1) showing a TV display image of an example of a font design.

FIG. 19 is a diagram (part 2) showing a TV display image of an example of the font design.

FIG. 20 is a diagram (No. 3) showing a TV display image of an example of the font design.

FIG. 21 is a block diagram showing a detailed configuration of an example of an OSDC to which the present invention is applied.

FIG. 22 is a block diagram showing a schematic configuration of an example of a conventional display device.

FIG. 23 is an operation explanatory diagram of the dot data storage unit 4a in FIG. 22.

FIG. 24 is a diagram showing a font ROM area of an example of a conventional display device.

[Description of Reference Signs] 1 timing control unit 2, 2a address data storage unit 3 output control unit 4, 4a dot data storage unit 5 selection unit 6, 68 parallel / serial conversion unit 7 character signal generation means 9 font ROM access circuit 18 vertical 1 Double / Double circuit 19 RSEL signal generation circuit 36 SLD signal generation circuit 37 SCK signal generation circuit 65 Memory sequencer section 66 Display memory 68 Parallel / serial conversion section 70 Font ROM 80 Character code section 81 Classification code section 82, ..., 85 font ROM area (area) C, C0, ..., C2 Classification code F, F0, ..., F4 Font ROM raster address (first control signal) L, L0, ..., L4 raster address R Read address HID, MIG horizontal division decoding Signal RSEL ROM select signal (first Control signal) SITA Zoning signal V1H1 expanded designation signal

Claims (3)

[Claims] 1. A dot data storage unit (4, 70) in which dot data representing a character and / or a graphic is stored, and an area corresponding to the character and / or graphic in the dot data storage unit (4, 70). An address information storage unit (2, 66) in which a character code (M) designating (82, 83, 84, 85) is stored, and the character code (M) from the address information storage unit (2, 66) A read address (R) for controlling the reading of the character is generated, and the dot data storage unit (4, 70) identifies the character identified based on the character code (M) from the address information storage unit (2, 66). And / or a timing control section (1, 65) for generating a raster address (L, L0, L1, L2, L3, L4) for controlling the timing of dot data output according to a figure, and the dot data storage section ( Four , 70), and a character signal generator (7, 68, 69) for generating a character signal (CH) according to the output dot data from the dot data storage unit The area (82, 83, 84, designated by the character code (M) of (4, 70)
The division code (C, C0, C1, C2) for dividing and designating 85) into a plurality of divided areas is stored in the address information storage unit (2, 66) and the dot data storage unit (4, 70). Is configured to register the dot data representing one or more characters and / or figures in the entire plurality of divided areas, and the output dot data from the dot data storage unit (4, 70) A selection section (5) for selectively outputting from the plurality of divided areas of the data storage section (4, 70), and the area (82, designated by the character code (M).
83, 84, 85), the dot data representing one character and / or figure stored in the character signal generator (7, 6).
8, 69) and the dot data representing one character and / or figure stored in each of the plurality of divided regions at the same timing as the character data generation unit (7, 6).
8, 69) and a first control signal (F, F0, F1, F2, F3, F4) for controlling the timing of output from the dot data storage section (4, 70), and the selection section. A display device comprising: an output control section (3) for generating a second control signal (RSEL) for switching control of the output of (5). 2. One stored in each of the plurality of divided areas
The dot data representing one character and / or a figure is stored in the entire area (82, 83, 84, 85) in which the one character and / or figure is designated by the character code (M). The first control signal (F, F0, F1, F2, F2, F0, F1, F2
F3, F4) allows the dot data storage unit (4, 7)
0) output timing is controlled, and the output of the selection unit (5) is switching-controlled by the second control signal and is supplied to the character signal generation unit (7, 68, 69). The display device according to claim 1. 3. The display device according to claim 1, wherein the plurality of divided areas are divided into equal parts in the row direction and / or the column direction of the dot data storage section (4, 70). .