JPH0614348B2 - Buffer memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer memory device used for data interpolation of an ultrasonic diagnostic apparatus when writing data of one scanning line arranged in time series into a two-dimensional image memory. It is a thing.

2. Description of the Related Art In recent years, as the frequency of ultrasonic diagnostic equipment has increased, it has become necessary to write a high-resolution tomographic image in an image memory.
For example, when ultrasonic waves of 20 MHz are used, it is necessary to display a 1 cm × 1 cm area in an image memory having a 512 × 512 bit map capacity. Depth 1 in medium such as living body
The time required to obtain the reflected signal of the ultrasonic pulse in the cm area is 13 μsec. Therefore, when writing the data in this period to, for example, 390 pixels, 13/390 = 0.033 (μsec / pixel ) = It is necessary to write at the speed of 1/30 (MHz). FIG. 3 shows how a data string obtained by fan-shaped scanning of an ultrasonic transducer in an ultrasonic diagnostic apparatus is written in a bit mat arranged in a grid pattern. When the direction of A is A, it is assumed that the data string sampled at 30 MHz is written in the pixel indicated by the thick frame. It is assumed that the data string in the case where the direction of the write vector is the direction B inclined by the angle θ with respect to the grid is similarly written in the pixel indicated by the thick frame. In this case, the sampling rate of the data may be 30 MHz / cos θ (1). However, it is very difficult to change the high sample rate in accordance with the change of the direction of the write vector, that is, the angle θ, as in the equation (1). For this reason, in the conventional method, data is sampled at a constant sampling rate, and the data at the position closest to the grid point on the bitmap in the obtained data sequence of the write vector is written instead. Has been taken.

Problems to be Solved by the Invention However, according to this method, for example, in the example shown in FIG. 3, the position error of the sample point becomes about ± 1/2 pixel size,
There is a problem that the grayscale boundary part in the image is displayed unnaturally.

Therefore, the present invention performs temporary storage of a data string obtained at a constant sample rate and performs interpolation calculation between data,
A data string corresponding to an arbitrary sample rate can be obtained by interpolation, and a high-resolution tomographic image can be written in the image memory. Especially, a buffer suitable for writing a high-speed data string in the image memory. It is intended to provide a memory device.

Means for Solving Problems The constitution of the present invention for solving the above problems is as follows.
The scanning line data sequence is set as time-series data and sequentially held at 1 o'clock N
The register group composed of (≧ 3) registers and the register input whose input / output relationship is n are n registers.
-The 1st register output and the 1st register input has an input / output connection structure that is an input data bus, and a simultaneous phase register that stores N register outputs that form a register group at one time, and a simultaneous phase register N memory for storing one scan line data sequence which is the output of the above, a data selector composed of two registers and connected to N-1 outputs of said memory, respectively, and connected to the data selector The interpolation arithmetic unit for interpolating the one-scan-line time-series data and the adder, the upper bits are the read address signals of the N memories, and the next 1 bit is the selection signal of the data selector. A plurality of lower bits of the address generator for generating an address respectively indicating an interpolation coefficient.

The present invention takes the time-series digital data input to the data bus into the N registers, writes the data in parallel to the N memories, and outputs the data by the address read from the address generator. N pieces of data are read, (N-1) pieces of data are selected by the data selector using the specific bit of the same address as the data selection signal, and the interpolation calculation section is based on the interpolation coefficient indicated by the lower bit of the same address. (N−2) th interpolation is calculated to generate interpolation data.

Embodiment One embodiment of the present invention will be described in detail below with reference to the drawings. In FIG. 1, reference numeral 1 is an input data bus, 2 is a register group connected to the input data bus 1, and is composed of registers 3, 4 and 5 connected in cascade.
Is composed of a D-type flip-flop. The registers 3 and 4 each have a clock input terminal a, and the register 5 has a clock input terminal b. Reference numeral 10 is a quadrature register connected to the outputs 7, 8 and 9 of the registers 3, 4, and 5, which is composed of a D-type flip-flop and has a clock input terminal c and an output enable terminal d. Reference numerals 14, 15 and 16 denote memories connected by data buses 11, 12 and 13 of N columns (three columns in the illustrated example) of the quadrature register 10, each having a chip select terminal e and a write enable terminal f. . 17 is a memory 14,
A data selector connected to an output data bus of N columns 15 and 16 and composed of registers 18 and 19 and an inverter 20. The register 18 has a clock input terminal g and an output enable terminal i, and the register 19 is a clock. The inverter 20 has an input terminal j and an output enable terminal h, and the inverter 20 has an input terminal j. An interpolation calculator 23 is connected to the output data buses 21 and 22 of the N-1 column of the data selector 17, and can output interpolation data from the output bus 25. An address generator 27 outputs a memory address to the memories 14, 15 and 16, a data selection signal to the data selector 17, and an interpolation coefficient to the interpolation calculator 23. The address generator 27 includes a counter 31, an adder 35, a register 36, a register 37 with a clear function, and the like. A data buffer 39 connected to a data generator 40 outputs a register 36 and inputs a register 37 by a data bus 38. It is connected to the. The output of the register 36 is connected to one data input of the adder 35, the output data bus 34 of the adder 35 is connected to the input of the register 36, and the output of the register 36 is connected to the other data input of the adder 35. ing. The read address bus 32 connected to the output data bus 34 is connected to the counter 31, and the counter 31 is connected to the memories 14, 15 and 16 by the common address bus 28. The output vertical bus 34 is connected to the output enable terminal h of the register 19 and the input terminal j of the inverter 20 by the data selection signal line 26. The output data bus 34 is connected to the register 30 by the interpolation coefficient output bus 23, and the register 30 is connected to the interpolation calculator 23 by the interpolation coefficient bus 24. The register 30 has a clock input terminal g, the counter 31 has a clock terminal k and a load terminal l, the register 37 has a clock input terminal n and a clear terminal m, and the register 36 has a clock input terminal p and an output enable. The data buffer 39 has a terminal g and an enable terminal s. A timing signal generator 41 generates a timing signal at each of the terminals a to s.

Next, the operation of the above embodiment will be described. The input data bus 1 has a sample rate F _s , eg M with 30 MHz.
Digital data with a bit data width is input. As the value of M, about 4 to 6 is usually selected. This digital data is taken into each register 3, 4, 5 at the sample rate F _s . The outputs of these registers 3, 4 and 5 are fetched by the quadrature register 10 at the same timing. If the clock cycle of the clock input terminal c of the quadrature register 10 is 1/2 of the sample rate F _s , it will be 15 MHz in this example. In that case, the cycle time of the memories 14, 15, 16 for writing data is Approximately 67 nsec is sufficient, which is the speed that can be realized with standard CMOS-IC memory (30 MHz
When writing the data string of z directly to the memory, a very high-speed memory with a cycle time of 33 nsec is required. ).

The operation of the registers 3, 4, 5 and the quadrature register 10 will be described below with reference to the timing chart of FIG. It is assumed that the input data bus 1 receives, for example, a data string that increases by 0, 1, 2 for each sample. Register 3, 4,
A clock synchronized with the sample rate F _s is applied to the clock input terminals a and b of No. 5. A data string delayed by one sample is output to the outputs 7, 8, and 9 of the registers 3, 4, and 5. Therefore, in the quadrature register 10,
If a clock having a half speed of the sample speed F _s is applied to the clock input terminal c, its outputs 11, 12, 13 are output.
The contents of are as shown in the figure. The output will be the same even if a clock having a half speed of the sample speed F _s shown in the figure is added to the clock input terminal b. At this time, the phase register 1
The output enable terminal d of 0 is set to the output determination level. Hereinafter, the degree of data parallelism in the quadrature register 10 is represented by N (N = 3 in this embodiment).

The data strings thus changed are stored in the memories 14, 15, 16
Written in. A necessary timing signal is applied to the chip select terminal e and the write enable terminal f of each of the memories 14, 15 and 16. Data is in memory 1 for a certain period
After being written to 4, 15, 16 the read operation is started. In the read mode, the quadrature register 10 is set to the output open state. Thus, these operations are performed by the data sent from the address generator 27 as described later. That is, when the speed of the clock at the clock terminal k of the counter 31 in the address generator 27 is made equal to 1/2 of the sampling speed F _s , the counter 31 operates in the count mode in the memory write mode and the write address data is transferred to the address bus 28. Output to. In the memory read mode, the counter 31 operates in the load mode and outputs the read address data of the read address bus 32 to the address bus 28. By the output of the read address data, N (=) read from the memories 14, 15 and 16
3) The data selector 17 selects N-1 from the parallel data sequence.
(= 2) Parallel data strings are selected. At this time, the clock input terminals g of the registers 18 and 19 of the data selector 17
A clock synchronized with the memory read cycle F _r is input to the. The data select signal line 26 is connected to the output enable terminal h of the register 19 and the input j of the inverter 20.
Are connected and a data selection signal is sent from the address generator 17. Therefore, a control signal having a polarity opposite to that of the register 19 is applied to the enable terminal i of the register 18, and only the output of either one of the registers is determined, that is, selected. The data of the data selection unit 17 is input to the interpolation calculator 23 via the N-1 parallel M-bit data buses 21 and 22, and the interpolation coefficient from the address generator 27 is passed through the register 30 to the interpolation coefficient bus 24. 23
To the output bus 2
It is output to 5.

Next, the process in which the data is read from the memories 14, 15, 16 and the interpolation data is output from the interpolation calculator 23 will be described in detail. First, a clear signal is applied to the clear terminal n of the register 37 to set the output of the register 37 to "zero", the output enable terminal s of the data buffer 39 is set to the output definite level, and the output enable terminal g of the register 36 is set to the output open level. By doing so, the start position data generated by the data generator 40 is input to the register 36 via the adder 35. At this time, if a clock is applied to the clock input terminal p of the register 36, the start position data is taken into the register 36. Next, the pitch data generated by the data generator 40 is input to the register 37, and the pitch data is fetched in the register 37 by applying a clock to the clock input terminal m. Next, the output enable terminal s of the data buffer 39 is set to the output open level, and the output enable terminal q of the register 36 is set to the output fixed level. In this state, the result obtained by adding the start position data and the pitch data is output to the output data bus 34. Thereafter, when the clock synchronized with the memory read cycle F _r is applied to the clock input terminal p of the register 36, the period F _r is the output data bus 34
Outputs data that increases in increments of pitch data.

In the following, the address calculation will be performed using a numerical example. For example, from the reading start point "8.25" to the sample pitch "1.125"
It is assumed that data is read from the memories 14, 15 and 16.
The read start point “8.25” is a virtual sample position, which is at the midpoint between the true sample positions 8 and 9, and the part 0.25 after the decimal point specifies the intermediate distance in more detail. It is a thing. In order to make it possible to perform addition of data including a decimal point by fixed-point arithmetic, the reading start point and the sample pitch are multiplied by a large constant, for example, 2 9 = 512, and the fractional part is rounded off. The obtained data correspond to the above-mentioned start position data and pitch data, respectively,
The obtained numerical value is represented by a binary number. First, the read start point “8.25” can be expressed as start position data of 0101000000000000 sample pitch as pitch data of 00001100000000. The result obtained by successively adding the pitch data to the start position data in the adder 35 is the first
It is shown in the table (however, LSB is the bit position φ).

On the other hand, Table 2 shows how the data at the sample position (0, 1, 2, ...) I is stored in each address value of the memories 14, 15, and 16.

In addition, the relationship between the level of the data selection signal line 26 and the memories 14, 15 and 16 corresponding to the selected data sequence is
Shown in the table.

Of the calculation results shown in Table 1 (output to the output data bus 34 of the adder 35), the higher bit side of the bit position 10 is the read address bus 32, and the bit position 9 is the data selection signal line 26. , A bit position lower than 8 bits, for example, a portion of 8 to 6 bits is interpolated coefficient output bus 3
Data can be read from the memories 14, 15 and 16 at desired sample positions and sample intervals by connecting to the memory device 3. Here, the data selector 17 is controlled by the register 30 in the middle of the interpolation coefficient output bus 33 and the interpolation coefficient bus 24.
The data process delay time in can be compensated.

The manner in which data is specifically read from the memories 14, 15 and 16 will be described in detail below. The sample position of the data sampled fourth from the sample position “8.25” at the sample pitch “1.125” is 8.25 + 1.125 × 4 = 12.75 (3). In Table 1, the read address is 0110 = 6, the level of the data selection signal is φ, and the interpolation coefficient is 110 from the calculation result when the number of additions is 4. As a result, the data having the address value 6 in the memory numbers 14 and 15, that is, the data at the sample positions 12 and 13 are read out simultaneously from Tables 2 and 3. Further, the interpolation coefficient corresponds to the part after the decimal point of the sample position. In this case, 1.0 corresponds to the interpolation coefficient 1000 (= 8) represented by a binary number, so that 110 (= 6) does not correspond to 0. .75, and the above result corresponds to the result of the above equation (3). Hereinafter, the part after the decimal point of the sample position corresponding to the interpolation coefficient is represented by the normalized interpolation coefficient WD.

Next, the operation of obtaining the interpolation data by the interpolation coefficient is shown below. In this case, since the interpolation is between two points, it is a linear interpolation calculation. If the data at the true sample position I is D (I), it is in the middle of the sample positions I and I + 1, and the interpolation coefficient W
In the case of D, the interpolation data INTD is INTD = D (I) × (1-WD) + D (I + 1) × WD (4) The interpolation calculator 23 may execute the calculation of equation (4). Alternatively, the calculation result can be stored in advance in a look-up table, for example, a read only memory (ROM). In this case, 2 is applied to the interpolation calculator 23.
The column M-bit data buses 21 and 22 and one column interpolation coefficient bus 24 are input, but M = 4, the interpolation coefficient bus 24 is 3
If bits, all inputs are 4 × 2 + 3 = 11 bits (= 2
K), and it is possible to use a ROM of 2K × 8 bits, for example. In this way, a data sequence having a high sample rate is output as a data sequence corresponding to that obtained at an arbitrary sample rate and sample position.

Although an example of linear interpolation calculation is shown in the above description, higher-order interpolation is also possible. For example, increase the parallelism N of data,
If N = 4, three M-bit data buses are input to the interpolation calculator 23. A quadratic interpolation calculation is generally used to obtain the interpolation data between the three data, and the result of this calculation can be prepared in advance in the ROM. In the above embodiment, the interval of the data string obtained at the sample rate F _s of 30 MHz is divided into 3 bits (= 8), which is equivalent to the sample rate of 30 MHz × 8 = 240 MHz. This is the sample position accuracy, and this accuracy can be realized by a logic IC, a memory, or the like having a general operation speed.

EFFECTS OF THE INVENTION As is apparent from the above description, according to the present invention, the data input to the data bus is taken into the register group and the quadrature register, and the data is written in the memory in parallel.
This data is read by the read address from the address generator, selected by the data selector from the read parallel data string by the data selection signal from the address generator, and based on this data and the interpolation coefficient from the address generator. Then, the interpolation calculation unit performs the interpolation. Since arbitrary interpolation data is generated from a data string obtained at a constant sample rate in this way, the circuit configuration is simpler than when a circuit that generates a variable sample rate is used, and a highly accurate tomographic image is stored in the image memory. You can write to. Moreover, since the circuit can be realized by a logic IC, a memory or the like having a general operating speed even though its equivalent sample rate is very high, it is particularly used for inputting the image memory of the high frequency ultrasonic diagnostic apparatus. Are suitable.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a buffer memory device of the present invention, FIG. 2 is a timing diagram for explaining the operation of a register for input data and a quadrature phase register, and FIG. 3 is a write vector on a bitmap. FIG. 1 ... Input data bus, 2 ... Register group, 10 ... Quadrature register, 14-16 ... Memory, 17 ... Data selector, 18, 19 ... Register, 20 ... Inverter,
23 ... Interpolation calculator, 27 ... Address generator, 40 ...
... data generator, 41 ... timing signal generator.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tsutomu Yano 3-10-10 Higashisanda, Tama-ku, Kawasaki City, Kanagawa Matsushita Giken Co., Ltd. (56) Reference JP-A-57-73785 (JP, A) JP-A-52-3345 (JP, A) JP-A-51-140520 (JP, A)

Claims (2)

[Claims] 1. A register group composed of N (≧ 3) registers that sequentially output one scanning line data sequence output to an input data bus and digitally converted at a constant sampling rate as time series data for one hour. And the input / output relationship of the register group is such that the n-th register input is the (n-1) -th register output and the first register input is the input data bus. Do N
Each register output is composed of two registers: a quadrature register for storing one register output at one time; N memories for storing one scan line data sequence output from the quadrature register; 1) A data selector connected to the outputs, an interpolation calculator connected to the data selector for interpolating one scanning line time series data, and an adder, and the upper bits are read from the N memories. Scan signal connected to an adder of the address generator, and an address generator for generating an address in which another specific bit is the selection signal of the data selector and the remaining lower bits are the interpolation coefficient. A buffer memory device for an ultrasonic diagnostic apparatus, comprising: a data generator that generates initial data according to the above. 2. A register group composed of three registers and three memories, wherein when the interpolation coefficient is WD for the time series data D (I), D (I) × (1- The buffer memory device according to claim 1, wherein the buffer memory device comprises an interpolation calculator that calculates the first interpolation data by (WD) + D (I + 1) × WD.