JPH0614515B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor device which enables high integration and high speed of LSI. Particularly, it is effective in an LSI in which MOSFETs having a low contact resistance and a low diffusion layer are highly integrated.

Conventionally, the impurity diffusion layer of the semiconductor substrate has been formed by an ion implantation method or a thermal diffusion method. However, in the ion implantation method, in the trench formed in the semiconductor substrate, impurity ions cannot be implanted into the side surface of the trench. In addition, the thermal diffusion method can diffuse impurities into the bottom and side regions of the groove, but the thermal diffusion method requires heat treatment at high temperature for a long time, so that the impurity diffusion region expands to form a source / drain of a miniaturized MOSFET. Is difficult to use. Therefore, in the conventional method of manufacturing a semiconductor device, it is impossible to form a groove in a semiconductor substrate and form a shallow impurity diffusion layer in the bottom and side surface regions of the groove.

According to the present invention, after forming a groove in a semiconductor substrate and filling the groove with an organic solvent containing diffusion impurities or silicon dioxide,
A method of manufacturing a semiconductor device is characterized in that a shallow impurity diffusion layer is formed on the bottom and side surfaces of the groove by short-time annealing. In particular, it is most suitable for a method of manufacturing an LSI including a low resistance source / drain diffusion layer and a miniaturized MOSFET having a low contact resistance.

An example will be described below.

FIG. 1 shows an ion implantation method for forming an impurity diffusion layer on a conventional semiconductor substrate. A groove is formed in the semiconductor substrate 1 using the resist 2 as a mask. Then, the impurity ions 3 are implanted by the ion implantation device. In the ion implantation method, since the impurity ions 3 go straight, a diffusion layer can be formed only on the bottom surface 4 of the groove, and the diffusion layer is not formed on the side surface of the groove. Further, according to the thermal diffusion method, an impurity diffusion layer can be formed on the bottom surface and the side surface of the groove, but since the thermal diffusion method requires heat treatment at high temperature for a long time, the impurity ions spread in the depth direction and the lateral direction, and the shallow diffusion layer is formed. Source of a miniaturized MOSFET
It is difficult to apply it to the formation of the drain diffusion layer.

2 to 8 show a method of manufacturing a semiconductor device according to the present invention. In FIG. 2, after forming the SiO ₂ film 7 on the semiconductor substrate 5, a groove is dug, an organic solvent containing a diffusion impurity and silicon oxide is applied to the groove region, and the groove is filled with the organic solvent 6. After that, high-temperature annealing (900 ° C or more and within 10 seconds) is performed for a short time using a halogen lamp.
A shallow diffusion layer 8 is formed on the bottom surface and the side surface of the groove formed in the semiconductor substrate 5 (FIG. 3). In the present invention, since the liquid organic solvent having low viscosity is used, the groove formed in the semiconductor substrate can be completely filled. Therefore, the diffusion impurities contained in the organic solvent can uniformly form the diffusion layer on the bottom surface and the side surface of the groove by the heat treatment. Also,
In the present invention, since the heat treatment is performed in a short time, the spread of impurity ions is small. Thus, by using the method for manufacturing a semiconductor device according to the present invention, a shallow diffusion layer can be formed on the bottom surface and the side surface region of the groove formed in the semiconductor substrate.

4 to 8, the present invention is applied to the manufacture of miniaturized MOSFETs.

In the conventional MOSFET, the source / drain diffusion layer becomes shallower as the LSI is highly integrated, and the contact hole connecting the AL wiring and the source / drain diffusion layer is further miniaturized. Therefore, in the diffusion layer formed by the conventional ion implantation method, the resistance of the P-type diffusion layer having a junction depth of 0.3 μm or less and the resistance of the N-type diffusion layer having a junction depth of 0.2 μm or less. Is greater than 50Ω / □. Further, the contact resistance between the AL and the Si semiconductor substrate diffusion layer is 100Ω when the contact hole is smaller than 1 μm ^□.
Over. Therefore, in the conventional manufacturing method, the MOSFE
As the LSI consisting of T becomes finer, diffusion resistance and contact resistance increase, which prevents the LSI from operating at higher speed.
It limited the high integration of T. In the present invention, the source / drain is formed by forming a shallow diffusion layer on the bottom surface and the side surface of the groove formed in the semiconductor substrate in the contact hole region that connects the metal substrate and the semiconductor substrate diffusion layer separated by the interlayer insulating film. The diffusion layer and contact resistance are reduced.
Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS.

In FIG. 4, the gate film 1 is formed on the Si semiconductor substrate 11.
4, the gate electrode 13 and the source / drain diffusion layer 12 formed by ion implantation are formed. After accumulating the interlayer insulating film 15, a contact hole is formed by patterning the photoresist 16 and subsequently a groove is formed in the contact hole region of the Si semiconductor substrate (FIG. 5). continue,
After applying the organic solvent 17 containing the diffusion impurities 17 and filling the contact hole and the groove of the semiconductor substrate, annealing is performed for a short time using a halogen lamp (Sixth).
Figure). In FIG. 7, a shallow diffusion layer 18 is formed on the bottom and side surfaces of the groove of the Si semiconductor substrate by this annealing. After removing the organic solvent 17 and the resist 16, the AL wiring 19 is formed, and the contact hole and the groove of the semiconductor substrate are filled with AL. FIG. 8 is a sectional view of a MOSFET manufactured by the method of the present invention. According to the invention,
A shallow diffusion layer is formed on the bottom surface and side surface area of the groove of the Si semiconductor substrate in the contact hole area, and AL is embedded in the groove. Therefore, the resistance of the source / drain diffusion layer of the MOSFET is very small due to the embedded AL.
Further, the contact area between the AL wiring 19 and the diffusion layers 12 and 18 is 5 μm ² if the groove depth is 1 μm even if the contact hole is miniaturized to 1 μm ^□ . Therefore, by digging the groove deeply, a contact resistance of 20Ω / □ or less becomes possible. In the present invention, the material containing impurities refers to an organic solvent containing diffusion impurities, silicon dioxide, or the like.

As described above, the method for manufacturing a semiconductor device according to the present invention enables the manufacture of a high-speed and highly integrated LSI including a source / drain diffusion layer having a low resistance and a miniaturized MOSFET having a low contact resistance.

[Brief description of drawings]

FIG. 1 is a sectional view of a conventional method for forming an ion-implanted diffusion layer. FIGS. 2 and 3 are sectional views of a manufacturing method for forming a shallow diffusion layer on the bottom and side surfaces of a groove according to the present invention. 6, 7 and 8 are MOSFETs according to the present invention.
Manufacturing method cross-section 1,5,11 ... Semiconductor substrate 2,16 ... Resist 3 ... Ion implantation 4,8,12,18 ... Diffusion layer 6,17 ... Diffusion impurity-containing organic solvent 7 ... ... SiO ₂ 13 ... gate electrode 14 ... gate film 15 ... interlayer insulating film

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device in which a semiconductor substrate is provided with at least a source impurity diffusion layer and a drain impurity diffusion layer, wherein one or both of the source impurity diffusion layer and the drain impurity diffusion layer are penetrated. Furthermore, a step of forming a contact hole reaching the semiconductor substrate and having an area of 1 μm ^□ or less, a step of filling the contact hole with a material containing an impurity of the same conductivity type as the impurity of the diffusion layer, the semiconductor substrate Heating by light irradiation to perform heat treatment to form a shallow impurity diffusion layer on the side surface and the bottom surface of the contact hole, a step of removing a material containing the impurities filled in the contact hole, and a wiring in the contact hole A method of manufacturing a semiconductor device, comprising the step of forming.