JPH0614537B2 - I▲Bottom 2▼L Semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD OF THEINVENTION The present invention relates to an I ² L semiconductor device that reduces power consumption.

[Technical Background of the Invention and Problems Thereof] Recently, in order to increase the integration density and functionality of analog LSIs, various attempts have been made to incorporate so-called ^I2L digital elements, which can easily coexist with analog elements and have the features of high integration density and low power consumption.
55 and the like are known.

4 is a cross-sectional view showing a conventional example of the structure of a so-called ^I2L semiconductor device that is formed on the same substrate as an analog circuit (not shown) and that constitutes, for example, a logic circuit. In the figure, 101 is a P-type silicon substrate (hereinafter referred to as "substrate"), an N ⁺ diffusion region (hereinafter referred to as "N ⁺ buried layer") 103 for burying is formed on this substrate 101, an N ^- epitaxial layer (hereinafter referred to as "N ^- epi layer") 105 is formed on the upper part of this N ⁺ buried layer ¹⁰³ , and an N-type region (hereinafter referred to as "N well") 107 is formed in this N-epi layer 105. An NPN bipolar transistor (hereinafter referred to as "inverse transistor") 109 having a multi-collector and a PNP bipolar transistor (hereinafter referred to as "lateral transistor") 111 are formed in this inverse transistor 107.
09 and a lateral transistor 111 form an I ² L circuit.

The inverted transistor 109 has a P-type region formed in the N-well 107 as a base region 113, and two N ⁺ -type regions are formed in the P ^- type region at a predetermined distance.
The base region 113, the first collector region 117, and the second collector region 119 are formed as a first collector region 117 and a second collector region 119, and the N well 107 is formed as an emitter region. Aluminum wirings 115a, 115b, and 115c are formed in the base region 113, the first collector region 117, and the second collector region 119 to connect the respective regions to peripheral circuits formed on the same substrate 101. In the N well 107, N ⁺ type regions 121a and 122a are formed by diffusion at a high concentration so as to surround the inverse transistor 109 and the lateral transistor 111.
121b are formed, and each N ⁺ type region 121a
, 121b includes an N ⁺ type contact region 123a
, 123b are formed, and an N ⁺ type contact region 123a is in contact with an aluminum wiring 125, and the emitter region of the inverse transistor 109 is connected to the ground via this wiring 125.

The lateral transistor 111 is formed so that the N-well 107 is its base region, the P-type base region 113 of the inverted transistor 109 is its collector region, and the P-type region formed in the N-well 107 is its emitter region 127, to which a bias current is supplied via an aluminum wiring 129. That is, in one ^I2L circuit, the base region of the lateral transistor 111 and the emitter region of the inverted transistor 109 are formed so that the N-well 107 is a common region, and further, the collector region of the lateral transistor 111 is formed so as to become the base region of the inverted transistor 109. Reference numeral 131 denotes an oxide film (Si
13 is a P ⁺ _type element isolation region for isolating peripheral circuits formed on the substrate 101 from one another.

By the way, by forming an N well 107 having a higher impurity concentration than the N ^epitaxial layer 105 in this way,
When the inverted transistor 109 and the lateral transistor 111 are formed in this N well 107, the impurity concentration in the emitter region of the inverted transistor 109 increases,
The emitter injection efficiency is improved. Therefore, the current amplification factor of the inverted transistor 109 can be increased and the amount of holes injected into the emitter region can be reduced, which has the advantage of increasing the response speed. On the other hand, since the emitter region of the inverted transistor 109 is also the base region of the lateral transistor 111, the emitter injection efficiency of the lateral transistor 111 decreases and the current amplification factor decreases. Therefore, it is possible to form the N-well 107 without forming the N ^-well.
In order to obtain the same response speed as when the inverse transistor 109 and the lateral transistor 111 are formed in the epitaxial layer 105, a larger bias current is required compared to when the N-well 107 is not formed, resulting in a problem of increased power consumption.

[Object of the Invention] The present invention has been made in consideration of the above, and an object of the invention is to provide an I ² L semiconductor device that reduces power consumption while maintaining a high response speed.

[Summary of the Invention] In order to achieve the above object, the present invention provides a semiconductor device comprising a first conductivity type semiconductor substrate, a second conductivity type epitaxial layer formed on the semiconductor substrate, a second conductivity type buried layer formed between the epitaxial layer and the semiconductor substrate,
a well region of a second conductivity type formed in a part of the epitaxial layer in contact with the buried layer and having a higher impurity concentration than the epitaxial layer;
a diffusion region of a conductive type, at least one diffusion region of a second conductive type formed in the diffusion region and constituting a collector of a transistor having the well region as an emitter and the diffusion region of the first conductive type as a base; and a diffusion region of a second conductive type formed in the epitaxial layer and constituting the diffusion region of the first conductive type as a collector.
and a diffusion region of a first conductivity type constituting an emitter of a transistor based on the epitaxial layer.

[Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a cross-sectional structure of an ^I2L semiconductor device according to one embodiment of the present invention. The ^I2L semiconductor device is composed of a multi-collector NPN bipolar transistor (hereinafter referred to as an "inverse transistor") 3 formed on a P-type silicon substrate (hereinafter referred to as the "substrate") 1, and a PNP bipolar transistor (hereinafter referred to as the "lateral transistor") 5 formed adjacent to this inverse transistor 3.

An N ⁺ type diffusion region (hereinafter referred to as an “N ⁺ buried layer”) 7 is formed in a portion located below where the lateral transistor 5 on the substrate 1 is formed, and an N ⁺ buried layer 7 is formed in a portion located below where the inverse transistor 3 is formed by using, for example, phosphorus as an impurity.
⁺ type diffusion region (hereinafter referred to as "thick N ⁺ buried layer") 9
An N ^- epitaxial layer (hereinafter referred to as "N ^- epi layer") 11 is formed on the thick N ⁺ buried layer 9 and the N ⁺ buried layer 7. The N ^{-epi layer 11 on the thick N+ buried} layer 9 has a depth of, for example, 5 to 6 μm.
A shallow N-type region (hereinafter referred to as an "N well") 13 having a depth of about 1000 nm is formed in contact with the thick N ⁺ buried layer 9. A P-type diffusion region 15 is formed in this N well 13. At least one N ⁺ type diffusion region 17, 19 is further formed in this P-type diffusion region 15. The N well 13 serves as an emitter region, the P-type diffusion region 15 serves as a base region, and the N ⁺ type diffusion regions 17, 19 serve as an emitter region.
The inverted transistor 3 is formed with the first and second collector regions 9 and 10, respectively. The base region and the first and second collector regions of the inverted transistor 3 are provided with aluminum wirings 21a, 21b, and 21c for connecting the base region and the first and second collector regions to the peripheral circuits formed on the substrate 1. In the N ^- epi layer 11, highly diffused N ⁺ regions 23a and 23b are formed so as to surround the regions in which the inverted transistor 3 and the lateral transistor 5 are formed, and N ⁺ contact regions 25a and 25b are formed in the N ⁺ regions 23a and 23b, respectively. The N ⁺ contact region 25a is contacted with an aluminum wiring 27, and the N well 13, i.e., the emitter region of the inverted transistor 3, is connected to ground via the aluminum wiring 27.

In addition, a P-type diffusion region 29 is formed in the N ^- epi layer 11 at a predetermined distance from the N-well 13.
The N-type diffusion region 29 is used as an emitter region, and the N ^- epi layer 11
is a base region, and a P-type region 1
The lateral transistor 5 is formed with the P-type diffusion region 29 contacting the aluminum wiring 31. Therefore, the collector region of the lateral transistor 5 is formed to be the base region of the inverse transistor 3. The reference numeral 33 denotes an oxide film (S
₂ film), and 35 is a P ⁺ type element isolation region for isolating peripheral circuits formed on the substrate 1 from each other.

FIG. 2 is an equivalent circuit diagram of the ^I2L semiconductor device shown in the cross-sectional structure in FIG.
The base 37 of the first collector 41 is connected to the aluminum wiring 21a, and the second collector 43 is connected to the aluminum wiring 2
The emitter 49 is connected to the ground via the aluminum wiring 27. The base 51 of the lateral transistor 5 is connected to the inverse transistor 3
The collector 53 is connected to the base 37 of the inverting transistor 3, and the emitter 55 is connected to the aluminum wiring 31 (injector terminal) to receive a bias current.

In the ^I2L semiconductor device having such a configuration,
Since the well 13 is formed only in the portion where the inverted transistor 3 is formed, with a shallow diffusion depth, so as to be in contact with the thick N ⁺ buried layer 9, the impurity concentration of the N well 13 is high, for example, about 10 ¹⁶ to ^{10 17} cm ^-3 , and a sufficient transistor emitter installation current amplification factor can be obtained.
Furthermore, the response is improved because the accumulation of holes is reduced.
Since the ^epitaxial layer 11 is used, the efficiency of hole injection from the P-type region 29 is increased, and the grounded emitter current amplification factor of the lateral transistor 5 is also increased to, for example, 4 to 5. Furthermore, the reverse injection current (base current) of electrons into the emitter is reduced, thereby reducing power consumption.

In this embodiment, the thick N ⁺ -type buried layer 9 is formed immediately below the region where the inverse transistor 3 is formed. However, a thick N + -type buried layer may also be formed immediately below the region where the lateral transistor 5 is formed. In addition, the N ⁺ -type diffusion regions 23 a and 23 b diffused at a high concentration may be formed at a ^low concentration.
Alternatively, the regions in which the inverse transistor 3 and the lateral transistor 5 are formed may be surrounded by the N ⁺ type diffusion regions 25a and 25b without forming the N+ type diffusion regions 25a and 25b.

Next, an example of the manufacturing process for the ^I2L semiconductor device of this embodiment will be described with reference to Figs.

This manufacturing process is based on the commonly used so-called bipolar process. First, an oxide film 33a is formed on the surface of a P-type silicon substrate 1, and a reverse transistor 33b is formed on the surface of the P-type silicon substrate 1.
The oxide film 33a in the region where the lateral transistor 5 is to be formed is removed by etching, and phosphorus ions are implanted in the region where the inverse transistor 3 is to be formed.
In addition, arsenic or antimony is diffused in the region where the lateral transistor 5 is to be formed, and N ⁺ type buried layers 7 and 9 for burying are formed (FIG. 3(A)). After the formation, the oxide film 33a is removed, and an N ^- epi layer 11 having a resistivity of, for example, 2 Ωcm and a thickness of, for example, 12 μm is formed on the surface of the substrate 1 (FIG. 3(B)). Next, an oxide film 33b is formed on the surface of this N ^- epi layer 11, and the oxide film 33b in the region where the element isolation region 35 is to be formed is removed, and boron, for example, is diffused in the removed portion to form a P ⁺ type element isolation region 35 (FIG. 3(C)). And then. The oxide film 33b in the region where the reverse transistor 3 is to be formed is removed, and for example, phosphorus ions are implanted into the removed portion (FIG. 3(D)). A thick N ⁺ buried layer 9 thicker than the buried layer 7 is formed by outward diffusion during drive-in, and an N well 13 with a shallow diffusion depth is formed so as to contact the thick N ⁺ buried layer 9, and the oxide film 33b is then removed (FIG. 3(E)). Next, a new oxide film 33c is formed, and for example, phosphorus is diffused to surround the region where the reverse transistor 3 and the tetrahedral transistor 5 are to be formed.
High concentration N ⁺ type regions 23a and 23b are formed (third
Next, the oxide film 33d in the portion that will become the N well 13 and the emitter region of the lateral transistor 5 is removed, and in the removed portion, buried diffusion is performed to form P type diffusion regions 15, 29 (FIG. 3(G)). N ⁺ type regions 17, 19 are formed in this P type diffusion region 15, and further, a highly diffused N ⁺ type region 23 is formed.
Then, contact holes are formed in the oxide film 33 on the P-type region 29, the N ⁺ -type regions 17, 19, 25a, and the P ^{-type region 15 formed in the N-} well 13, and aluminum wirings 21a, 21b, 21c, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109 ...
31 is formed (FIG. 3(I)). Finally, P
An SG film 37 is applied, and holes are opened for the bonding pads, completing the process as shown in Fig. 1 (Fig. 3(J)).

Effect of the Invention As described above, according to the present invention, of the two transistors constituting an ^I2L semiconductor device, the emitter of one of the transistors is formed in a region having a higher impurity concentration than the region in which the base of the other transistor is formed. This makes it possible to significantly reduce the base current of the other transistor while maintaining the response speed of one of the transistors, thereby providing an ^I2L semiconductor device that is capable of reducing power consumption and heat generation.

[Brief description of the drawings]

Fig. 1 is a cross-sectional view of an ^I2L semiconductor device according to one embodiment of the present invention, Fig. 2 is an equivalent circuit diagram of the ^I2L semiconductor device of Fig. 1, Figs. 3(A)-(J) are diagrams showing the manufacturing process of the ^I2L semiconductor device of Fig. 1, and Fig. 4 is a cross-sectional view showing a conventional example of an ^I2L semiconductor. (Explanation of symbols showing main parts of the figure) 1... P-type silicon substrate 3... NPN-type bipolar transistor 5... PNP-type bipolar transistor 11... Epitaxial layer 13... N-well

Claims (1)

[Claims] [Claim 1] An I2L semiconductor device comprising: a semiconductor substrate of a first conductivity type; an epitaxial layer of a second conductivity type formed on the semiconductor substrate; a buried layer of a second conductivity type formed between the epitaxial layer and the semiconductor substrate; a well region of a second conductivity type formed in a part of the epitaxial layer in contact with the buried layer and having a higher impurity concentration than the epitaxial layer; a diffusion region of a first conductivity type formed in the well region; at least one diffusion region of a second conductivity type formed in the diffusion region and constituting the well region as an emitter and the diffusion region of the first conductivity type as a base of a transistor; and a diffusion region of a first conductivity type formed in the epitaxial layer and constituting the diffused region of the first conductivity type as a collector and the emitter of a transistor based on the ^epitaxial layer.