JPH0614625B2 - Digitally controlled adaptive AGC system - Google Patents

Description

Description: (a) Technical Field of the Invention The present invention relates to a discrete equalization characteristic of a PCM relay transmission device or the like that receives a signal obtained by converting a 1,0 signal into an RZ code at a transmission side. Control type adaptive AG for line equalizer
The present invention relates to the C method and relates to a digital control type adaptive AGC method in which the peak value of the received signal itself has a desired amplitude even when stationary noise is added to the equalized output signal.

(b) Prior art and problems In the conventional digital control type adaptive AGC system, for example, it is judged whether the peak value of "1" of the equalized output signal exceeds a desired output amplitude, The number of times is counted at every fixed time, and if it exceeds a predetermined number, the gain of the line equalizer is controlled to be decreased, and if it is not exceeded even once, the gain is controlled to be increased. In this method, when external noise such as broadcast waves and disturbance noise such as power supply switching noise are constantly present (0 in terms of direct current), the output signal including the noise becomes the desired output amplitude. However, since the original signal amplitude becomes smaller, it is visible as deterioration of the eye, and there is a drawback that the identification margin becomes smaller.

(c) Object of the Invention In view of the above drawbacks, the object of the present invention is to disturb noise (DC component =
There is a provision of a digital control type adaptive AGC system capable of controlling so that the peak value of the equalized output signal itself has a desired amplitude even when 0) is constantly added.

(d) Structure of the Invention In order to achieve the above-mentioned object, the present invention focuses on the fact that the disturbance noise has a DC component of 0, that is, an average value of 0 and is asynchronous with the received signal. First pulse output means for outputting a pulse when the peak value of the output amplitude of the output signal of the line equalizer is larger than the desired equalized output amplitude, and "1""of the output signal of the line equalizer. Distinguish 0 ",
When it is "1", the second pulse output means for outputting a pulse, and the count value is initially set to the center value, the pulses from the first and second pulse output means are input, and the second pulse is output. When a pulse is input from the output means, it counts up if the pulse from the first pulse output means is input, and it counts down if no pulse is input, and when the counted value overflows, the line And a control means for controlling the gain of the line equalizer to be increased when the underflow occurs in the direction of decreasing the gain of the equalizer.

(e) Embodiment of the Invention One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a digital control type adaptive AGC according to an embodiment of the present invention.
FIG. 2 is a block diagram of the circuit, and FIG. 2 is a time chart of the waveform of each part in FIG. 1 VR ₁ , VR ₂ , a, P ₁ , P ₂ , CLK, P ₃ , P ₄ , P ₅ , b, P ₆ , P ₇ , c
Correspond to the same symbols in FIG. 1, respectively.

In the figure, 1 and 2 are comparators, 3, 8 and 12 are knot circuits, and 4,
5 is a NAND circuit, 6 is an OR circuit, 7 is a D-type flip-flop (hereinafter referred to as FF), 9 is an AND circuit, 10 is an up / down counter, 11 is an overflow underflow detection circuit, and 13 is an up / down counter for coefficients. Show.

The reference voltage VR 1 in FIG. ₁ is a voltage equal to the desired equalized output swing, and the reference voltage VR ₂ is the identification level of the equalized output signal and is usually half the reference voltage VR ₁ . This state is shown in Fig. 2 VR
Shown in ₁ and VR ₂ . The output P ₁ of the comparator ₁ is shown in FIG.
Is a signal obtained by slicing the equalized output signal shown in FIG. 2 with the reference voltage VR ₁ , and as shown in P ₁ of FIG.
It becomes 1 level when it is larger than VR ₁ and 0 level when it is smaller.
The output P ₂ of the comparator ₂ is a signal obtained by slicing the equalized output signal shown in FIG. 2A with the reference voltage VR ₂ , and the equalized output signal a is larger than the reference voltage VR _{2 as} shown in P ₂ of FIG. It is 1 level when it is small and 0 level when it is small. The output P ₆ of the overflow underflow detection circuit 11 becomes overflow (count value = + N) or underflow (count value = −N) in the overflow underflow detection circuit 11 as shown by P ₆ in FIG. It is a signal that is 1 level at the time, and is 0 level at other times. When it becomes 1 level, the up / down counter 10 is reset. The output P ₇ of the overflow underflow detection circuit 11 is 1 level when the overflow underflow detection circuit 1 overflows and 0 level when the overflow underflow detection circuit 1 overflows, as shown in P ₇ of FIG.

The operation will be described below. When the equalized output signal shown in Figure 2 a exceeds the reference voltage VR _1, the output P ₃ of the NAND circuit 4, as shown in FIG. 2 P _3, the 1 level. The FF 7 detects one level of the reception data P ₂ output from the comparator 2 as shown in P ₄ of FIG. 2, and the output P of the NAND circuit 4 at that time is detected.
See if ₃ is 0 level or 1 level. That is, if P ₃ = 0 at the rising edge of the output signal P ₅ of the AND circuit 9, one up / down counter 10 is down-counted, and if P ₃ = 1, 1
Count up. The state of this count value is shown in FIG. 2b, and this count value is sent to the overflow underflow detection circuit 11. When this count value overflows (count value = + N), it is determined that the equalized output signal amplitude is larger than the desired amplitude, and the outputs P ₆ and P ₇ of the overflow underflow detection circuit 11 are shown in FIG. P ₆ ,
As shown in P ₇ , the level becomes 1 and the coefficient up / down counter 13 is down-counted by 1 to reduce the gain of the line equalizer to 1
Step down. When the count value in the opposite underflows (count value = -N) is equalized output signal Fuhaba is determined to do more desired Fuhaba, the output P ₆ is 1 level overflow underflow detection circuit 11, P ₇ becomes 0 level, the coefficient up / down counter 13 is counted up by one, and the gain of the line equalizer is increased by one step. Simultaneously with the update of the gain, the output signal P ₆ resets the up / down counter 10 to 0 and continues counting. In other words, when noise is superimposed on the peak portion of the equalized output signal, the peak value becomes large when the noise is positive, and the peak value becomes small when the noise is negative.

Generally, the number of times the noise becomes positive is equal to the number of times the noise becomes negative, so that the number of times the peak value of the equalized output signal increases due to the noise becomes substantially equal to the number of times the peak value decreases.

Therefore, in the case of the present invention, the value of the up / down counter 10 is up-counted when the peak value of the equalized output signal exceeds a voltage equal to the desired equalized output amplitude, and down-counted when the value does not exceed. Therefore, the count value may be biased in the direction of up-counting or down-counting in terms of time, but if the value that the up-down counter 10 overflows or underflows is set large enough to ignore this bias, Overflow due to noise,
Underflow does not occur and control for changing the gain of the equalizer is not performed. By doing so, the influence of the disturbance noise having an average value of 0 is canceled, the gain of the line equalizer is updated by the peak value of the equalized output signal itself, the eye deterioration is eliminated, and the discrimination margin is not reduced. .

(f) Effect of the Invention As described in detail above, according to the present invention, even if the received signal is disturbed, the influence of the disturbed noise is canceled and the peak value of the received signal itself becomes a desired amplitude. Since it is controlled, there is an effect that the deterioration of the eye is eliminated and the discrimination margin is not reduced.

[Brief description of drawings]

FIG. 1 shows a digital control type adaptive AGC according to an embodiment of the present invention.
FIG. 2 is a block diagram of the circuit, and FIG. 2 is a time chart of the waveform of each part of FIG. In the figure, 1 and 2 are comparators, 3, 8 and 12 are knot circuits, and 4,
5 is a NAND circuit, 6 is an OR circuit, 7 is a D-type flip-flop, 9 is an AND circuit, 10 is an up / down counter,
Reference numeral 11 is an overflow underflow detection circuit, and 13 is an up / down counter for coefficients.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshitaka Tsuda 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (72) Inventor Kazuo Yamaguchi 1015 Kamedotaka, Nakahara-ku, Kawasaki, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Setsu Fukuda 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Akihiko Takada, 1015, Kamikodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Kimura, Tadakatsu Kanagawa Prefecture 1839 Ono, Atsugi City, Atsugi Telecommunications Research Institute, Nippon Telegraph and Telephone Corporation (72) Masayuki Ishikawa, 1839, Ono City, Atsugi City, Kanagawa Prefecture

Claims (1)

[Claims] 1. A first pulse output means for outputting a pulse when a peak value of an output amplitude of an output signal of a line equalizer having a discrete equalization characteristic is larger than a desired equalized output amplitude, The output signal of the line equalizer, "1" or "0", is discriminated by whether it is larger or smaller than 1/2 of the desired equalized output amplitude.
In the case of, the second pulse output means for outputting a pulse, and the count value is initialized to the center value, the pulses from the first and second pulse output means are input, and the second pulse output means When a pulse is input from the first pulse output means, the counter counts up if the pulse is input from the first pulse output means, and if the pulse is not input, the counter counts down, and when the count value of the counter overflows, A digital control type adaptive AGC system comprising: a control means for controlling the gain of the line equalizer to be reduced and, when an underflow occurs, controlling the gain of the line equalizer to be increased.