JPH0614636B2 - Sync timing generator - Google Patents

Description

Detailed Description of the Invention A. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization timing generation circuit used in a receiver of a data communication device.

B. SUMMARY OF THE INVENTION According to the present invention, in a synchronization timing generation circuit for generating a synchronization timing signal synchronized with each bit of input data input bit by bit, data of each bit is sampled for about 1 bit time. Further, if the sample value of the first half stage of the shift register and the sample value of the second half stage of the shift register do not match, the sample value is input to the shift register and sequentially shifted, and a missing portion or noise is included in the 1-bit input data. Is determined to have not existed, the clock signal of a predetermined cycle is divided, and the frequency division counter that generates the synchronization timing signal is reset, and the frequency division operation of the frequency division counter is performed by the input timing of each bit of the input data. Since the input data has a missing part or noise is superimposed, In which synchronization timing signal is to be prevented from being generated I.

C. 2. Description of the Related Art In data communication in which data is transmitted and received bit by bit in a time series, if the read timing of the data is set at a change point where the data of each bit changes, the data is not sufficiently stable and the read result is There is an error.

Therefore, in order to read at a timing substantially in the middle of each bit, a synchronization timing generation circuit that generates a synchronization timing signal synchronized with the input timing of each bit has been conventionally used.

FIG. 3 shows the structure of a conventional synchronous timing generation circuit, which includes a D-type flip-flop 11 and an exclusive OR gate.
It consists of 12 and the frequency division counter 13, and the time series input data D
Is sampled bit by bit in the flip-flop 11, for example, by the clock signal CLK having a cycle of 1/2 of the 1-bit time width. Then, the sample value is compared with the input data D after 1/2 clock period in the exclusive OR gate 12. As a result of the comparison, if the two levels are different, it is determined that the input data D has changed,
The frequency division counter 13 is reset by the signal of the determination result. During this period, the frequency division counter 13 keeps the clock signal CL.
Although K is frequency-divided and a synchronization timing signal synchronized with the input timing of each bit is output, it is reset by the output signal of the exclusive OR gate 12 due to a change in the input data D. As a result, the frequency division counter 13 frequency-divides the clock signal CLK in synchronization with the input timing of new input data.

In this way, the frequency division counter is reset every time the input data changes, so that the synchronization timing signal as its output signal is synchronized with each bit of the input data. Therefore, by using this synchronization timing signal to generate a timing signal for reading at a timing almost in the middle of each bit, it is possible to read time-series data bit by bit without error.

D. The problem to be solved by the invention is that, in the above-described synchronization timing generation circuit, whether or not there is a change in the input data by comparing the input data 1/2 clock period before and the current input data. Therefore, if noise is superimposed 1/2 clock cycle before or at the current time, or if data is partially missing, it is determined that the input data has changed. . Therefore, there is a problem in that the generation timing of the synchronization timing signal is deviated.

E. Means for Solving the Problems The present invention has a clock generator that generates a clock signal having a cycle of 1 / n times the time width of 1 bit of input data, and a storage location of n stages. A shift register for sequentially shifting each stage while sampling input data by the clock signal, a frequency dividing counter for dividing the clock signal to generate a periodic signal synchronized with each bit of the input data, and a shift register for the shift register. The sample value of the first half stage is compared with the sample value of the latter half stage, and if they do not match, the frequency division counter is reset and the frequency division operation of the frequency division counter is synchronized with the input timing of each bit of the input data. And a data mismatch detection circuit.

F. Function The input data of each bit is sampled at a cycle of 1 / n by the clock signal and sequentially shifted to each stage of the shift register. At this point, if the input data has no noise or missing at the end of the shift of n / 2 stages, the sample values of the first half stage and the second half stage will not always match, and conversely if there is noise or loss. Will appear to match any stage. Therefore, if there is a match in any of the stages, by not resetting the frequency division counter, it is possible to prevent the frequency division counter from generating the synchronization timing signal at an incorrect timing due to noise, etc. And the frequency division operation of the frequency division counter can be synchronized only with normal input data when the sample values of the latter half stage match.

G. Embodiment 1 FIG. 1 is a circuit diagram showing an embodiment of the present invention, in which a clock generator 1 for generating a clock signal CLK having a cycle 1/16 times the time width of 1 bit of input data RD and 16 stages Shift register 2 for sequentially shifting each stage while sampling the input data RD of each bit by the clock signal CLK, and dividing the clock signal CLK by 16 to obtain each bit of the input data RD. A frequency dividing counter 3 for generating a synchronized periodic signal RTL,
The shift register 2 has eight exclusive OR gates G1 to G8 and one NAND gate G9, and the sample values of the first half stages Q1 to Q8 and the second half stages Q9 to Q16 of the shift register 2 are Q1 and Q8, Q2. Q9, Q3 and Q10, ... Q8 and Q
It is composed of a data mismatch detection circuit 4 which outputs a reset signal RS from the NAND gate G9 and resets the frequency division counter 3 when all 16 mismatches are compared and compared.

In the above configuration, the clock generator 1 generates the clock signal CLK having a period of 1/16 of the 1-bit data time width as shown in FIG. 2 (a), and the clocks of the shift register 2 and the frequency dividing counter 3 are generated. Feeding the input. Now, at the timing t ₁ as shown in FIG. 2B, the input data R
Assuming that D changes to "1", the input data RD of "1" is sampled every time the clock signal CLK is generated, and is sampled through the first stage Q1 of the shift register 2 to the 16th stage.
It is sequentially shifted toward stage Q16.

As a result, the first stage Q1, the eighth stage Q8, the
The output signal of the 16-stage Q16 changes as shown in FIGS. 2 (c), (d), and (e), but in the data mismatch detection circuit 4, the signal of each stage of the shift register 2 changes sequentially. As a result, the output signals C1 to C8 of the exclusive OR gates G1 to G8 also sequentially change to "1" at the timings shifted by one clock cycle as shown in FIGS. 2 (f) to (m). Then, at time t ₂ has been reached exactly half of one bit time width output signals of all of the exclusive OR gates G1 to G8 C
1 to C8 are “1”.

That is, since the output signals of the first half stages Q1 to Q8 are all "1" and all the output signals of the second half stages Q9 to Q16 are "0", the comparison results are all inconsistent.
Therefore, the signal C1~C8 all at the timing of time t ₂ becomes "1".

On the other hand, the frequency division counter 3 frequency-divides the clock signal CLK,
A synchronization timing signal R having a cycle 16 times as long as the clock signal CLK (that is, a cycle equal to a 1-bit data time width)
The TL is output via the inverter 5. However, when the signals C1 to C8 are all set to "1" in the data mismatch detection circuit 4 and the logical product condition of the NAND gate G9 is satisfied, it is reset by the reset signal RS output from the NAND gate G9. That is, the frequency division operation of the frequency division counter 3 is forcibly synchronized by the reset signal RS after the lapse of 8 clock cycles after the input data RD rises to "1".

However, when noise is superimposed on the input data RD or there is a partial missing, the signal of the stage corresponding to the sampling timing of such noise or the missing part is matched with the signal of the latter half stage. Becomes
The logical product condition of the NAND gate G9 is no longer satisfied. Therefore, the reset signal RS is not generated, and the frequency dividing counter 3
Continues the frequency division operation at the timing synchronized with the previous bit. Therefore, the frequency division counter 3 will not be erroneously synchronized even if noise is superimposed on the input data or if there is a missing portion, and synchronization that changes at a predetermined cycle as shown in FIG. 2 (u). The timing signal RTL can be output. In this case, by monitoring the reset signal RS, it is possible to detect that there is a missing portion in the input data due to the superposition of noise. 2 (o) to (t) are waveforms of the terminals of the frequency dividing counter 3, and FIG. 2 (t) is a carry.

H. As described above, according to the present invention, the data of each bit is sampled for about 1 bit time, the sample value is input to the shift register and sequentially shifted, and the first half stage of the shift register is shifted. If the sample value and the sample value of the latter half stage do not match, it is determined that there is no missing portion or noise in the 1-bit input data, the clock signal of a predetermined cycle is divided, and the synchronization timing signal is obtained. Since the frequency division counter that is generated is reset and the frequency division operation of the frequency division counter is synchronized with the input timing of each bit of the input data, when there is a missing portion in the input data or noise is superimposed, It is possible to prevent the synchronization timing signal from being generated by mistake. Therefore, if it is applied to a data communication device in a place where the usage environment is bad, the reliability can be further improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing diagram of input / output signals of respective parts in the embodiment of FIG. 1, and FIG. 3 is a configuration diagram showing a conventional synchronization timing generating circuit. . 1 ... Clock generator, 2 ... Shift register, 3 ...
Frequency division counter, 4 ... Data mismatch circuit.

Claims (1)

[Claims] 1. A synchronization timing generation circuit for generating a synchronization timing signal synchronized with each bit of input data input time-sequentially bit by bit, wherein a clock having a cycle of 1 / n times the width of 1 bit of the input data. A clock generator that generates a signal, a shift register that has n stages of storage locations, sequentially shifts to each stage while sampling input data of each bit by the clock signal, and divides and inputs the clock signal. A frequency division counter that generates a periodic signal synchronized with each bit of data and a sample value of the first half stage and a sample value of the second half stage of the shift register are compared bit by bit, and if they do not match, the frequency division is performed. The counter is reset and the frequency division operation of the frequency division counter is synchronized with the input timing of each bit of input data. A synchronization timing generation circuit having a data mismatch detection circuit for synchronization.