JPH0614659B2 - Parallel reader - Google Patents

Description

The present invention relates to a parallel reading device suitable for use in a document reading device such as a facsimile.

2. Description of the Related Art For example, a document reading unit of a conventional facsimile apparatus has a third
As shown in FIG.
Number of lenses 2 to 5, four CCD sensors 6 to 9 provided corresponding to each of these lenses, four amplifiers 10 to 13 and a gain control circuit 14 to provided corresponding to each of these sensors.
17, a comparator 18 to 21, an A / D converter 22 to 25, a line memory circuit 26 to 29, and a clock generator 30, each of which scans one line by four independent reading blocks, Image data is sequentially output from the line memory circuits 26 to 29 of each block, and the data is combined in the output order to obtain image data PI × 1 for one line.

Here, an example of a composite waveform of the image data PI × 1 is shown by reference numeral 35 in FIG. In the figure, it is shown by CCD1
31 is the image signal waveform of the output of the amplifier 10 (1-1, 1-2, 1-3, ... 1-121
5,1-1216), 32 shown by CCD2 is the image signal waveform of the output of the amplifier 11 (2-1, 2-2, 2-3, ... 2-1215, 2-1216), and 33 shown by CCD3 is the output of the amplifier 12 Image signal waveform (3-1, 3-2,… 3-121
6), 34 shown by CCD4 is the image signal waveform (4
-1,4-2, ... 4-1216).

In each of the reading blocks, the reflected light from the original 1 is imaged by the lenses 2 to 5, and the light is photoelectrically converted by the CCD sensors 6 to 9 which are driven by the clock φ from the clock generator 30, and this is amplified. Amplify 10 to 13.

The original image signal waveform of the amplified amplifier 10-13 output (image signal waveform before gain control) is as shown in FIG. 5 (a). In FIG. (A), 36 is an image signal reference level V _R, 37 set by the comparator 18 to 21 peak level V _P 1 and 38 of the amplifier 10 output is the peak level V _P 2,39 amplifier 11 output amplifier
The 12 output peak level V _P 3, 40 is the amplifier 13 output peak level V _P 4, 41 is the original image signal waveform of the amplifier 10 output, 42 is the amplifier 11 output, 43 is the amplifier 12 output,
Reference numeral 44 is each original image signal waveform output from the amplifier 13.

The original image signals output from the amplifiers 10 to 13 are supplied to the A / D converter 22 to
At 25, it is converted into a digital image signal.

The converted digital image signal is compared with the image signal reference level V _R (coincidence voltage) set therein in the comparators 18 to 21, and the peak level V _P of the original image signal in the gain control circuits 14 to 17. Gain control is performed so that ₁ to V _P 3 become the image signal reference level V _R.

Gain controlled image data (CCD1 to CC in FIG. 4)
D4) is once stored in the line memory circuits 26 to 29, and then the image data at the beginning of the line (1 of CCD 1 in FIG. 4).
-1)), image data PI × 3 for one line (see signal waveform 35 in FIG. 4).

FIG. 5B shows the line memory circuits 26 to 29 after gain control.
This figure shows the output image signal waveform.
Image signal reference 5 was set by the comparator 18 through 21 levels V _R, 46
Is the corrected output image signal waveform of the line memory circuit 26 output, 47
Is a line memory circuit 27 output, 48 is a line memory circuit 28
Reference numeral 49 of the output is the corrected output image signal waveform of the output of the line memory circuit 29.

However, according to such a configuration, the gain control circuit is independently connected to the four sets of reading blocks and operates independently, so that the C of each of the four sets of blocks is independent.
If there are variations in the characteristics of the CD sensor, the amplifier, etc., the gains of the gain control circuits do not match, and the image data for one line synthesized by the outputs of the four line memory circuits is the same density original document. Even if there are CCDs next to each other
There is a problem that a level difference occurs at each joint of the sensor (see FIG. 5 (a)).

The present invention has been made in view of the above problems, and an object of the present invention is to provide an image at each joint of N sets (4 sets in the conventional example) of reading blocks (CCD sensors adjacent to each other). An object of the present invention is to provide a parallel reading device capable of eliminating the data level difference.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention uses N (N ≧
The driving timing of the line sensor (CCD sensor) of 2) is shifted by 1 / N of the image signal period of one pixel, and N sets of image signals output from the CCD sensor are changed to C
In synchronism with the drive cycle of the CD sensor, selective synthesis is performed by a sampling pulse having a pulse width of 1 / N or less of the image signal cycle of one pixel, and the synthesized image data is subjected to gain control by one gain control circuit. It was done.

Operation According to the present invention, the gain control of the image signals of the N CCD sensors can be performed by the single gain control circuit by the above-described configuration, whereby the level of the image data at the joint between the CCD sensors adjacent to each other can be achieved. It is possible to eliminate the birth.

Embodiment FIG. 1 is a schematic block diagram showing an example of a document reading apparatus suitable for carrying out the present invention. In the figure, 51 is a document placed on the back side of the reading position, and 52 to 55 are reflected lights from the document 51. , 56-59 are line sensors (CCD sensors) for photoelectrically converting the images from the lenses 52-55, and 60-63 are CCs.
Amplifiers for amplifying the original image signals output from the D sensors 56 to 59, and 64 to 67 are sampling pulse generating circuits 73 described later.
Is an analog switch which is turned on when each of the sample clocks φ _{5 to} φ ₈ from “H” is “H”.

68 is a gain control circuit, and this gain control circuit 68 is an A / D
The image signal level V _D A / D converted by the converter 69 is compared with the reference level V _R by the comparator 70. When V _D > V _R , the comparator 7
Gain control signal output from the 0 lowers the gain slightly by the active state, the gain control signal output from the V _D ≧ V _R eaves comparator 70 to gain by a state not active state It has a function to control the gain so that it is raised little by little.

Reference numeral 71 is a line memory circuit, and the line memory circuit 71 selectively synthesizes the image signals output from the amplifiers 60 to 63 by the analog switches 64 to 67 so as to be arranged in the pixel order, and image data PI × 2 (see FIG. 2). At the same time as storing the image data PI × 2 in pixel order stored one line before,
The CCD sensors 56 to 59 are rearranged in this order and output as image data PI × 3 (see FIG. 2) for one line.

Reference numeral 72 denotes a clock generator that generates drive clocks φ _{1 to} φ ₄ that are shifted by 1/4 of the image signal period of one pixel.
CCD sensors 56 to 59 depending on the driving clocks φ _{1 to} φ ₄
Is driven.

Reference numeral 73 denotes a sampling pulse generation circuit which is synchronized with the driving cycle of the clock generator 72 and generates sampling pulses (sample clocks φ _{5 to} φ ₈ ) having a pulse width of ¼ or less of the image signal cycle of one pixel.

FIG. 2 shows an example of the main signal waveform in FIG. 1, in which S1 is the waveform of the sample clock φ ₅ and S2 is
Is the sample clock φ ₆ and S3 is the sample clock φ ₇
, S4 is each waveform of the sample clock φ ₈ , and CCD 5 is the image signal waveform of the amplifier 60 output, CC
D6 is an amplifier 61 output, CCD7 is an amplifier 62 output, C
CD8 is each image signal waveform of the output of the amplifier 63, and here, it is shifted by 1/4 and outputted. In addition, the PI × 2 outputs the image signals (see CCD5 to CCD8) output from the amplifiers 60 to 63 by the analog switches 64 to 67 in the pixel order (1-1, 2-1, 3-1, 4-1, 1-).
2, 2-2, ...) is a sequence (combined waveform) of the image data selectively combined, and the image signals output from the amplifiers 60 to 63 are sampled at the same sampling point in the image signal cycle of one pixel. Has been done.
PI × 3 is image data for one line rearranged by the line memory circuit 71.

Next, the operation of the parallel reading method in the apparatus configured as described above will be described below.

First, the reflected light from the original 51 is imaged by the lenses 52 to 55, and this is driven by the drive clocks φ _{1 to} φ _4.
Photoelectric conversion is performed by the CD sensors 56 to 59, and this is output to the amplifiers 60 to 63 as a document image signal. Amplifiers 60-63 amplify the original image signal and output it to analog switches 64-67.

4 output from four sets of CCD sensors 56 to 59 at this time
As shown in CCD5 to CCD8 in FIG. 2, the driving timing of the CCD sensors 56 to 59 is CC when the set of document image signals is CC.
Based on the D sensor 56, the image signal cycle of 1 pixel is CCD
The length divided by the number of the sensors 56 to 59, that is, shifted by ¼ pixel in this embodiment, the sample clocks φ ₅ to φ ₈ to the analog switches 64 to 67 are also shown in FIG. As shown in S1 to S4 of FIG.

Next, the four sets of original image signals input to the analog switches 64-67 are selectively combined by the sample clocks φ ₅ -φ ₈ to form one image data PI × 2.

The column of image data PI × 2 at this time is PI × 2 in FIG.
As shown in FIG. 2, each CCD sensor 56 to 59 has the same number (for example, 1-1, 2-1, 3-1, 4-1 in the example of FIG. 2).
Pixels are combined in the direction of main scanning of the CCD sensors 56 to 59.

This image data PI × 2 is then sent to the A / D converter 69 for A
Image signal level (peak level) V after being D / D converted
_{In the case of D, the} comparator 70 compares it with the reference level V _R set there.

In this case, the gain control signal output from the V _D> V _R If the comparator 70 in the active state, the V _D ≦ V _R if the gain control signal to a state not active state. The comparator 70 inputs the gain control circuit 68.

The gain control circuit 68 lowers the gain of the image signal PI × 2 by the conversion rate τ ₁ when the input gain control signal is in the active state, and raises the gain by the conversion rate τ _{2 when} it is not in the active state.

At this time, if τ ₁ << τ ₂ and τ ₂ is set to the same level as the reading time for one line, the peak level V _{D of the} image signal is maintained at the reference level V _R.

The A / D-converted image data PI × 2 is stored in the line memory circuit 71.

The line memory circuit 71 has a double structure, and at the same time the image data PI × 2 is input to one of the line memory circuits, the image data PI × of one line before stored in the other line memory circuit. 2 is rearranged so that the image data of the same CCD sensor arranged in pixel order is arranged in the order of CCD sensors 56 to 59 as shown in PI × 3 in FIG. 2 (1-1, 1 in the second example). -2, ... 1-1212, 2-1, 2
-2, ... 2-1212, ...), and outputs this as one line of image data.

As a result, one line of image data PI × 3 is obtained.

EFFECTS OF THE INVENTION As is clear from the above description, according to the present invention, the driving timing of N line sensors is set to 1 of the image signal period of one pixel.
/ N shifts, and the N sets of image signals of the line sensor output which are driven by it are synchronized with the driving period of the line sensor and have N pulse widths of 1 / N or less of the image signal period of one pixel. Since the selected image is synthesized by the sampling pulse, the synthesized image data is inputted to one gain control circuit, and the gain control is performed by the gain control signal obtained as a result, each joint of the line sensors adjacent to each other. This has the effect of eliminating the level difference of the conventional image data that has occurred in a portion. Further, by shifting the image signal by 1 / N, each of the N sets of image signals can be sampled at the same sampling point in the image signal cycle of one pixel, so that ideal sampling can be performed. it can. Therefore, there is also an effect that the processing speed can be increased.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an example of an apparatus suitable for carrying out the parallel reading method according to the present invention, FIG. 2 is a signal waveform diagram of essential parts of the apparatus shown in FIG. 1, and FIG. 3 is a conventional method. 4 is a schematic configuration block diagram showing an example of an apparatus applied to the implementation of FIG.
FIG. 5 is a signal waveform diagram of a main part of the apparatus shown in FIG. 3, FIG. 5 (a) is an image signal waveform diagram before gain control in FIG.
(b) is a diagram of the image signal waveform after the gain control. 51 ... original, 52-55 ... lens, 56-59 ... line sensor (CCD sensor), 60-63 ... amplifier, 64-67 ... analog switch, 68 ... gain control circuit, 69 ... A / D
Converter, 70 ... Comparator, 71 ... Line memory circuit, 72 ...
… Clock generator, 73… Sampling pulse generator.

Claims (1)

[Claims] 1. An image signal for one line of a document is divided into N signals, which are output in parallel while shifting each by 1 / N pixel.
Reading means, a selecting / combining means for sampling the output of each reading means to selectively combine the same pixel in the main scanning direction, and a predetermined reference voltage for the image signal of the selected and combined one line. And a gain control means for adjusting the gain, wherein the selective synthesizing means performs timing shifting by 1 / N pixel for sampling.